From nobody Tue Dec 30 14:36:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40C18C2BB3F for ; Wed, 15 Nov 2023 17:17:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232820AbjKORRf (ORCPT ); Wed, 15 Nov 2023 12:17:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232740AbjKORRU (ORCPT ); Wed, 15 Nov 2023 12:17:20 -0500 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1326AD6D for ; Wed, 15 Nov 2023 09:17:13 -0800 (PST) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-5afa071d100so148844227b3.1 for ; Wed, 15 Nov 2023 09:17:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1700068633; x=1700673433; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Qy3zX0s6ALtK+DaG4wUXBjQ8F6aHRpWpiFcWV1cr/U0=; b=nR6PK/+008SAq1seEfnKT0/2+xngpAiBhIDUKWLk9c1hrMWjUTVQYqYRgJPk4tVW2X izvzNx860G2ZjZzxR0ovojefWBqeKkw/Xb38sxkommQqbLg0oLn1R6Pe4ktjQ0igd5ny X9iSg79JjqQII7PDb8NorG8pxLRsl/ieLWAtGaetNLzdyiLB+55rUvJyH7GRZCjkD1wG J3U+DHc2ngwQ5MHrTmAu+z1qGuMymab3Bni8qMG0Lm376qooO7uV/cOps0YK90h0KXUi FJSkFrS5qM3jXwktXZORAD8rzUAV7KhHNFoT/IXxBvWM+nydqE5Ozcn8w5zZEnBXQbly VYjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700068633; x=1700673433; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Qy3zX0s6ALtK+DaG4wUXBjQ8F6aHRpWpiFcWV1cr/U0=; b=LCqowOE5zxCwDybV+7YiLP6yQr7fyMdepqrmRImy75iQYxiz66mgXA8DDid2/JqYER w2BZCtYArvj0Ed3gycXbuceR6lpvF6a5uxfqKo/2+zOUGp9KERFYvw4hqpHfM/5dMqCd pZm2x8cozquyDU4r4Z0paXoZRqmkv7fq/lv20y7OXOcvYfO7B/e9jXcEncJa25gvWsMi OLqW8md3dN7m5wKuo92qR3D1VPM+wGCACnntEtKUsQHJ5qt3In6Pgz9VuEj9wRvGXafJ cGBs8jaZtkMoc0EfU46Ke/TM9/Qa+5bV9hkCfHtk/LpQwPfNmEVgrAziAVSPLaC4yB6l 0KFw== X-Gm-Message-State: AOJu0YxoQZ7ElQGQ6IW1XEF+/WagcK1h/Q83A21friVyG4SXYfrC95Tq 0g/G+3NL3A2XvprZ6FF6vQtKq7E/FSHk+2fpb7w= X-Google-Smtp-Source: AGHT+IH15zotRvXqa3gGL+erJN8kJ8qtR4AedLWdqyhduoqwJwWiS5LNpUVQnjgpQUblW7SZJCRmmCsMHRZC6boVABk= X-Received: from sebkvm.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:cd5]) (user=sebastianene job=sendgmr) by 2002:a0d:d7c3:0:b0:5a7:b672:4d88 with SMTP id z186-20020a0dd7c3000000b005a7b6724d88mr356731ywd.0.1700068633096; Wed, 15 Nov 2023 09:17:13 -0800 (PST) Date: Wed, 15 Nov 2023 17:16:38 +0000 In-Reply-To: <20231115171639.2852644-2-sebastianene@google.com> Mime-Version: 1.0 References: <20231115171639.2852644-2-sebastianene@google.com> X-Mailer: git-send-email 2.43.0.rc0.421.g78406f8d94-goog Message-ID: <20231115171639.2852644-10-sebastianene@google.com> Subject: [PATCH v3 08/10] arm64: ptdump: Interpret memory attributes based on runtime configuration From: Sebastian Ene To: will@kernel.org, Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , catalin.marinas@arm.com, mark.rutland@arm.com, akpm@linux-foundation.org, maz@kernel.org Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel-team@android.com, vdonnefort@google.com, qperret@google.com, smostafa@google.com, Sebastian Ene Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When FWB is used the memory attributes stored in the descriptors have a different bitfield layout. Introduce two callbacks that verify the current runtime configuration before parsing the attribute fields. Add support for parsing the memory attribute fields from the page table descriptors. Signed-off-by: Sebastian Ene --- arch/arm64/mm/ptdump.c | 65 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/arm64/mm/ptdump.c b/arch/arm64/mm/ptdump.c index 9f88542d5312..ec7f6430f6d7 100644 --- a/arch/arm64/mm/ptdump.c +++ b/arch/arm64/mm/ptdump.c @@ -89,11 +89,19 @@ struct pg_state { struct ptdump_info_file_priv *f_priv; }; =20 +/* + * This callback checks the runtime configuration before interpreting the + * attributes defined in the prot_bits. + */ +typedef bool (*is_feature_cb)(const void *ctx); + struct prot_bits { u64 mask; u64 val; const char *set; const char *clear; + is_feature_cb feature_on; /* bit ignored if the callback returns false= */ + is_feature_cb feature_off; /* bit ignored if the callback returns true = */ }; =20 static const struct prot_bits pte_bits[] =3D { @@ -175,6 +183,34 @@ static const struct prot_bits pte_bits[] =3D { } }; =20 +static bool is_fwb_enabled(const void *ctx) +{ + const struct pg_state *st =3D ctx; + struct ptdump_info_file_priv *f_priv =3D st->f_priv; + struct kvm_pgtable_snapshot *snapshot =3D f_priv->file_priv; + struct kvm_pgtable *pgtable =3D &snapshot->pgtable; + + bool fwb_enabled =3D false; + + if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) + fwb_enabled =3D !(pgtable->flags & KVM_PGTABLE_S2_NOFWB); + + return fwb_enabled; +} + +static bool is_table_bit_ignored(const void *ctx) +{ + const struct pg_state *st =3D ctx; + + if (!(st->current_prot & PTE_VALID)) + return true; + + if (st->level =3D=3D CONFIG_PGTABLE_LEVELS) + return true; + + return false; +} + static const struct prot_bits stage2_pte_bits[] =3D { { .mask =3D PTE_VALID, @@ -216,6 +252,27 @@ static const struct prot_bits stage2_pte_bits[] =3D { .val =3D PTE_TABLE_BIT, .set =3D " ", .clear =3D "BLK", + .feature_off =3D is_table_bit_ignored, + }, { + .mask =3D KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR | PTE_VALID, + .val =3D PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_VALID, + .set =3D "DEVICE/nGnRE", + .feature_off =3D is_fwb_enabled, + }, { + .mask =3D KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR | PTE_VALID, + .val =3D PTE_S2_MEMATTR(MT_S2_FWB_DEVICE_nGnRE) | PTE_VALID, + .set =3D "DEVICE/nGnRE FWB", + .feature_on =3D is_fwb_enabled, + }, { + .mask =3D KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR | PTE_VALID, + .val =3D PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_VALID, + .set =3D "MEM/NORMAL", + .feature_off =3D is_fwb_enabled, + }, { + .mask =3D KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR | PTE_VALID, + .val =3D PTE_S2_MEMATTR(MT_S2_FWB_NORMAL) | PTE_VALID, + .set =3D "MEM/NORMAL FWB", + .feature_on =3D is_fwb_enabled, }, { .mask =3D KVM_PGTABLE_PROT_SW0, .val =3D KVM_PGTABLE_PROT_SW0, @@ -267,13 +324,19 @@ static struct pg_level pg_level[] =3D { }; =20 static void dump_prot(struct pg_state *st, const struct prot_bits *bits, - size_t num) + size_t num) { unsigned i; =20 for (i =3D 0; i < num; i++, bits++) { const char *s; =20 + if (bits->feature_on && !bits->feature_on(st)) + continue; + + if (bits->feature_off && bits->feature_off(st)) + continue; + if ((st->current_prot & bits->mask) =3D=3D bits->val) s =3D bits->set; else --=20 2.43.0.rc0.421.g78406f8d94-goog