From nobody Fri Dec 19 04:51:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2937C54FB0 for ; Wed, 15 Nov 2023 14:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344385AbjKOOlr (ORCPT ); Wed, 15 Nov 2023 09:41:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234984AbjKOOlI (ORCPT ); Wed, 15 Nov 2023 09:41:08 -0500 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CDE6D6A; Wed, 15 Nov 2023 06:40:41 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 77594FF819; Wed, 15 Nov 2023 14:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700059240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/iDpXiT5kizq64XeJ5sa38GNeM54k0DmxA9+90HSriY=; b=SKfB/GSMi41/0sVcuhpSQv9tLdToZM5z9Zo/s0awY5frNMmLGvUQhDqaaTwJsIxFab39IC kUR7PJOBbk/cKbXdQQW9MLTTDF5O95buwRmjyEQSt9cJukDsXjtxLr/ewxhIlszxC/Axd3 NncUcwgQN/Xw41hlXEFlXsbuc9KiegFcRPZYIQr3T8i8ra7NyHcr9yTOpD9KTq1pxT0lsk UNVUdaYgXg9FwBufysKCpfccA8ufKY/dPPd6eM33jb2G2gmHtwcAZQ50lleiLBfIv0pxmF 1J9olj64OjUf+Dcb7K9xvWUzdC2aGxHdLz1/+wqmKgvRNRFMWmUuyTL8Vm6JXA== From: Herve Codina To: Herve Codina , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Linus Walleij , Qiang Zhao , Li Yang , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Christophe Leroy , Randy Dunlap Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, Simon Horman , Christophe JAILLET , Thomas Petazzoni Subject: [PATCH v9 15/27] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Date: Wed, 15 Nov 2023 15:39:51 +0100 Message-ID: <20231115144007.478111-16-herve.codina@bootlin.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231115144007.478111-1-herve.codina@bootlin.com> References: <20231115144007.478111-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Tx and Rx entries for a given channel are set in one function. In order to modify Rx entries and Tx entries independently of one other, split this function in one for the Rx part and one for the Tx part. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 49 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index c1318fad296b..5ca4120779f8 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -610,14 +610,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan = *chan, const struct tsa_ser return 0; } =20 -static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struc= t tsa_serial_info *info, - bool enable) +static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct tsa= _serial_info *info, + bool enable) { unsigned int i; u16 curr; u16 val; =20 - /* Use a Tx 32 entries table and a Rx 32 entries table */ + /* Use a Rx 32 entries table */ =20 val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); =20 @@ -633,6 +633,30 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_cha= n *chan, const struct tsa_ return -EBUSY; } } + + /* Set entries based on Rx stuff */ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), + ~QMC_TSA_WRAP, enable ? val : 0x0000); + } + + return 0; +} + +static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa= _serial_info *info, + bool enable) +{ + unsigned int i; + u16 curr; + u16 val; + + /* Use a Tx 32 entries table */ + + val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); + /* Check entries based on Tx stuff */ for (i =3D 0; i < info->nb_tx_ts; i++) { if (!(chan->tx_ts_mask & (((u64)1) << i))) @@ -646,14 +670,6 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_cha= n *chan, const struct tsa_ } } =20 - /* Set entries based on Rx stuff */ - for (i =3D 0; i < info->nb_rx_ts; i++) { - if (!(chan->rx_ts_mask & (((u64)1) << i))) - continue; - - qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), - ~QMC_TSA_WRAP, enable ? val : 0x0000); - } /* Set entries based on Tx stuff */ for (i =3D 0; i < info->nb_tx_ts; i++) { if (!(chan->tx_ts_mask & (((u64)1) << i))) @@ -680,9 +696,14 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, b= ool enable) * Setup one common 64 entries table or two 32 entries (one for Tx * and one for Tx) according to assigned TS numbers. */ - return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? - qmc_chan_setup_tsa_64rxtx(chan, &info, enable) : - qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable); + if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32) + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); + + ret =3D qmc_chan_setup_tsa_32rx(chan, &info, enable); + if (ret) + return ret; + + return qmc_chan_setup_tsa_32tx(chan, &info, enable); } =20 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) --=20 2.41.0