From nobody Tue Dec 30 14:57:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4321C07548 for ; Wed, 15 Nov 2023 09:28:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234782AbjKOJ2e (ORCPT ); Wed, 15 Nov 2023 04:28:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234771AbjKOJ21 (ORCPT ); Wed, 15 Nov 2023 04:28:27 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9DA01FC; Wed, 15 Nov 2023 01:28:23 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7A2C1595; Wed, 15 Nov 2023 01:29:08 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.37.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 689733F7B4; Wed, 15 Nov 2023 01:28:17 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Mark Rutland , Will Deacon , Russell King , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm: perf: Remove PMU locking Date: Wed, 15 Nov 2023 14:58:04 +0530 Message-Id: <20231115092805.737822-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231115092805.737822-1-anshuman.khandual@arm.com> References: <20231115092805.737822-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PMU is disabled and enabled, and the counters are programmed from contexts where interrupts or preemption is disabled. The functions to toggle the PMU and to program the PMU counters access the registers directly and don't access data modified by the interrupt handler. That, and the fact that they're always called from non-preemptible contexts, means that we don't need to disable interrupts or use a spinlock. This is very similar to an earlier change on arm64 platform. commit 2a0e2a02e4b7 ("arm64: perf: Remove PMU locking"). Cc: Mark Rutland Cc: Will Deacon Cc: Russell King Cc: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Anshuman Khandual Acked-by: Mark Rutland --- arch/arm/kernel/perf_event_v6.c | 28 ++++-------------- arch/arm/kernel/perf_event_v7.c | 44 ----------------------------- arch/arm/kernel/perf_event_xscale.c | 44 ++++++----------------------- 3 files changed, 13 insertions(+), 103 deletions(-) diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v= 6.c index 1ae99deeec54..8fc080c9e4fb 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c @@ -268,10 +268,8 @@ static inline void armv6pmu_write_counter(struct perf_= event *event, u64 value) =20 static void armv6pmu_enable_event(struct perf_event *event) { - unsigned long val, mask, evt, flags; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long val, mask, evt; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 if (ARMV6_CYCLE_COUNTER =3D=3D idx) { @@ -294,12 +292,10 @@ static void armv6pmu_enable_event(struct perf_event *= event) * Mask out the current event and set the counter to count the event * that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D armv6_pmcr_read(); val &=3D ~mask; val |=3D evt; armv6_pmcr_write(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static irqreturn_t @@ -362,26 +358,20 @@ armv6pmu_handle_irq(struct arm_pmu *cpu_pmu) =20 static void armv6pmu_start(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D armv6_pmcr_read(); val |=3D ARMV6_PMCR_ENABLE; armv6_pmcr_write(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void armv6pmu_stop(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D armv6_pmcr_read(); val &=3D ~ARMV6_PMCR_ENABLE; armv6_pmcr_write(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static int @@ -419,10 +409,8 @@ static void armv6pmu_clear_event_idx(struct pmu_hw_eve= nts *cpuc, =20 static void armv6pmu_disable_event(struct perf_event *event) { - unsigned long val, mask, evt, flags; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long val, mask, evt; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 if (ARMV6_CYCLE_COUNTER =3D=3D idx) { @@ -444,20 +432,16 @@ static void armv6pmu_disable_event(struct perf_event = *event) * of ETM bus signal assertion cycles. The external reporting should * be disabled and so this should never increment. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D armv6_pmcr_read(); val &=3D ~mask; val |=3D evt; armv6_pmcr_write(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void armv6mpcore_pmu_disable_event(struct perf_event *event) { - unsigned long val, mask, flags, evt =3D 0; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long val, mask, evt =3D 0; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 if (ARMV6_CYCLE_COUNTER =3D=3D idx) { @@ -475,12 +459,10 @@ static void armv6mpcore_pmu_disable_event(struct perf= _event *event) * Unlike UP ARMv6, we don't have a way of stopping the counters. We * simply disable the interrupt reporting. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D armv6_pmcr_read(); val &=3D ~mask; val |=3D evt; armv6_pmcr_write(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static int armv6_map_event(struct perf_event *event) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v= 7.c index eb2190477da1..c890354b04e9 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -870,10 +870,8 @@ static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_p= mu) =20 static void armv7pmu_enable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { @@ -886,7 +884,6 @@ static void armv7pmu_enable_event(struct perf_event *ev= ent) * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* * Disable counter @@ -910,16 +907,12 @@ static void armv7pmu_enable_event(struct perf_event *= event) * Enable counter */ armv7_pmnc_enable_counter(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void armv7pmu_disable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { @@ -931,7 +924,6 @@ static void armv7pmu_disable_event(struct perf_event *e= vent) /* * Disable counter and interrupt */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* * Disable counter @@ -942,8 +934,6 @@ static void armv7pmu_disable_event(struct perf_event *e= vent) * Disable interrupt for this counter */ armv7_pmnc_disable_intens(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu) @@ -1009,24 +999,14 @@ static irqreturn_t armv7pmu_handle_irq(struct arm_pm= u *cpu_pmu) =20 static void armv7pmu_start(struct arm_pmu *cpu_pmu) { - unsigned long flags; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); - - raw_spin_lock_irqsave(&events->pmu_lock, flags); /* Enable all counters */ armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void armv7pmu_stop(struct arm_pmu *cpu_pmu) { - unsigned long flags; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); - - raw_spin_lock_irqsave(&events->pmu_lock, flags); /* Disable all counters */ armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, @@ -1492,14 +1472,10 @@ static void krait_clearpmu(u32 config_base) =20 static void krait_pmu_disable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); =20 /* Disable counter and interrupt */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* Disable counter */ armv7_pmnc_disable_counter(idx); @@ -1512,23 +1488,17 @@ static void krait_pmu_disable_event(struct perf_eve= nt *event) =20 /* Disable interrupt for this counter */ armv7_pmnc_disable_intens(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void krait_pmu_enable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); =20 /* * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* Disable counter */ armv7_pmnc_disable_counter(idx); @@ -1548,8 +1518,6 @@ static void krait_pmu_enable_event(struct perf_event = *event) =20 /* Enable counter */ armv7_pmnc_enable_counter(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void krait_pmu_reset(void *info) @@ -1825,14 +1793,10 @@ static void scorpion_clearpmu(u32 config_base) =20 static void scorpion_pmu_disable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); =20 /* Disable counter and interrupt */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* Disable counter */ armv7_pmnc_disable_counter(idx); @@ -1845,23 +1809,17 @@ static void scorpion_pmu_disable_event(struct perf_= event *event) =20 /* Disable interrupt for this counter */ armv7_pmnc_disable_intens(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void scorpion_pmu_enable_event(struct perf_event *event) { - unsigned long flags; struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); =20 /* * Enable counter and interrupt, and set the counter to count * the event that we're interested in. */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); =20 /* Disable counter */ armv7_pmnc_disable_counter(idx); @@ -1881,8 +1839,6 @@ static void scorpion_pmu_enable_event(struct perf_eve= nt *event) =20 /* Enable counter */ armv7_pmnc_enable_counter(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void scorpion_pmu_reset(void *info) diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_eve= nt_xscale.c index f6cdcacfb96d..7a2ba1c689a7 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c @@ -203,10 +203,8 @@ xscale1pmu_handle_irq(struct arm_pmu *cpu_pmu) =20 static void xscale1pmu_enable_event(struct perf_event *event) { - unsigned long val, mask, evt, flags; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long val, mask, evt; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 switch (idx) { @@ -229,20 +227,16 @@ static void xscale1pmu_enable_event(struct perf_event= *event) return; } =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale1pmu_read_pmnc(); val &=3D ~mask; val |=3D evt; xscale1pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void xscale1pmu_disable_event(struct perf_event *event) { - unsigned long val, mask, evt, flags; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long val, mask, evt; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 switch (idx) { @@ -263,12 +257,10 @@ static void xscale1pmu_disable_event(struct perf_even= t *event) return; } =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale1pmu_read_pmnc(); val &=3D ~mask; val |=3D evt; xscale1pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static int @@ -300,26 +292,20 @@ static void xscalepmu_clear_event_idx(struct pmu_hw_e= vents *cpuc, =20 static void xscale1pmu_start(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale1pmu_read_pmnc(); val |=3D XSCALE_PMU_ENABLE; xscale1pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void xscale1pmu_stop(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale1pmu_read_pmnc(); val &=3D ~XSCALE_PMU_ENABLE; xscale1pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static inline u64 xscale1pmu_read_counter(struct perf_event *event) @@ -549,10 +535,8 @@ xscale2pmu_handle_irq(struct arm_pmu *cpu_pmu) =20 static void xscale2pmu_enable_event(struct perf_event *event) { - unsigned long flags, ien, evtsel; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long ien, evtsel; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 ien =3D xscale2pmu_read_int_enable(); @@ -587,18 +571,14 @@ static void xscale2pmu_enable_event(struct perf_event= *event) return; } =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); xscale2pmu_write_event_select(evtsel); xscale2pmu_write_int_enable(ien); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void xscale2pmu_disable_event(struct perf_event *event) { - unsigned long flags, ien, evtsel, of_flags; - struct arm_pmu *cpu_pmu =3D to_arm_pmu(event->pmu); + unsigned long ien, evtsel, of_flags; struct hw_perf_event *hwc =3D &event->hw; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); int idx =3D hwc->idx; =20 ien =3D xscale2pmu_read_int_enable(); @@ -638,11 +618,9 @@ static void xscale2pmu_disable_event(struct perf_event= *event) return; } =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); xscale2pmu_write_event_select(evtsel); xscale2pmu_write_int_enable(ien); xscale2pmu_write_overflow_flags(of_flags); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static int @@ -663,26 +641,20 @@ xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc, =20 static void xscale2pmu_start(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; val |=3D XSCALE_PMU_ENABLE; xscale2pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static void xscale2pmu_stop(struct arm_pmu *cpu_pmu) { - unsigned long flags, val; - struct pmu_hw_events *events =3D this_cpu_ptr(cpu_pmu->hw_events); + unsigned long val; =20 - raw_spin_lock_irqsave(&events->pmu_lock, flags); val =3D xscale2pmu_read_pmnc(); val &=3D ~XSCALE_PMU_ENABLE; xscale2pmu_write_pmnc(val); - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); } =20 static inline u64 xscale2pmu_read_counter(struct perf_event *event) --=20 2.25.1