From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC6AEC46CC7 for ; Tue, 14 Nov 2023 23:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234105AbjKNXAg (ORCPT ); Tue, 14 Nov 2023 18:00:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233920AbjKNXAd (ORCPT ); Tue, 14 Nov 2023 18:00:33 -0500 Received: from mail-qv1-xf34.google.com (mail-qv1-xf34.google.com [IPv6:2607:f8b0:4864:20::f34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D07CDB for ; Tue, 14 Nov 2023 15:00:28 -0800 (PST) Received: by mail-qv1-xf34.google.com with SMTP id 6a1803df08f44-66d122e0c85so35843386d6.3 for ; Tue, 14 Nov 2023 15:00:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002827; x=1700607627; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HCsm7VCedF16OrkkHsKZ3GlEGsmWacvBMw8jR+/V2pU=; b=I/lWWWwAR4elrbtN89w7VqSMtCkx3kQYTC+bfalx4c+YY+iwWL2T0ADaN08nPgTgqY 4+s7gCEZaWk/OJLv7FJmQun+M3KycBI7DWNREapELvaX8098ckeAjlO5VG8bwo6Vi0yQ 4mXhZCYalsBg98MQF7R0bzADg7NZm49v/aLJPaceqm9PUMX4eOM0V9Z0IPiNY51kbQcJ QtyM1kXh91majHRz67vX1YH+UmPTb7gtpuxsb4p5g6HL91prNeglhu5RMvSx6TukXtcI kfjMGT3kyHig/G4toLn+Jh8Zc15ulufkbbxIr3wpKcKe/l3CRJCSbj9lP94sIkTCqMcI yNFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002827; x=1700607627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HCsm7VCedF16OrkkHsKZ3GlEGsmWacvBMw8jR+/V2pU=; b=qZoWCSWHOuKzxsfo3k0Kozw4BbB0ih4MSF7OHoVhep1o+Z+vWx9e1K6BOPIo3dZTf5 M42osKyqpR3bOOKWrBZPiNoIgRLYuKVXiPYfkIE947FBprA7y+7mE4VxFi/+E9vQyT0j ZWopjAqzot/HILTmKPSWqBWvA3iTh3tmEdeYXa92h8bBCZWOjzrC/7ThB6zLoPno0K1H mkGbDHoMWbYTOfljjeFlAt5nXpu+WnFYvN1zmUKwJcvlnRUpHslb+vJiL17whcIQFAuB nqq660hF2fFUYHd8/pn4Dzp+Z40W0/wL7ewmFD6quYBH5PMqfLnXZRCV3z9pZdVvt7io uu0Q== X-Gm-Message-State: AOJu0Yyhyh964fQhQsQYPzuVnPOML1xnak7ZJS+VF88+FUHASPexeY9S ejYjUIzZX/CA0ofg89dxi4qH1g== X-Google-Smtp-Source: AGHT+IGhxfGR9iFdmqeZtNyN8JXoHEt4QSyhdvoHgLMcAm8gIgPgRQ/R51UTcNkf5EfuQLRv6LpEbw== X-Received: by 2002:a0c:be88:0:b0:677:9fb2:26e9 with SMTP id n8-20020a0cbe88000000b006779fb226e9mr3489562qvi.14.1700002827707; Tue, 14 Nov 2023 15:00:27 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:27 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Kuogee Hsieh , Jessica Zhang , Vinod Polimera , Kalyan Thota , Konrad Dybcio , Arnaud Vrac , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/6] drm/msm/dpu: fix video mode DSC for DSI Date: Tue, 14 Nov 2023 17:58:29 -0500 Message-Id: <20231114225857.19702-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add necessary DPU changes for DSC to work with DSI video mode. Note this changes the logic to enable HCTL to match downstream, it will now be enabled for the no-DSC no-widebus case. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 ++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + 5 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 1cf7ff6caff4..d745c8678b9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2477,7 +2477,7 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct d= rm_encoder *encoder) return INTF_MODE_NONE; } =20 -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phy= s_enc) { struct drm_encoder *encoder =3D phys_enc->parent; struct dpu_encoder_virt *dpu_enc =3D to_dpu_encoder_virt(encoder); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 6f04c3d56e77..7e27a7da0887 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -332,7 +332,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( * used for this encoder. * @phys_enc: Pointer to physical encoder structure */ -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phy= s_enc); =20 /** * dpu_encoder_helper_split_config - split display configuration helper fu= nction diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index a01fda711883..df10800a9615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -100,6 +100,8 @@ static void drm_mode_to_intf_timing_params( } =20 timing->wide_bus_en =3D dpu_encoder_is_widebus_enabled(phys_enc->parent); + if (dpu_encoder_helper_get_dsc(phys_enc)) + timing->compression_en =3D true; =20 /* * for DP, divide the horizonal parameters by 2 when @@ -112,6 +114,15 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch =3D timing->h_front_porch >> 1; timing->hsync_pulse_width =3D timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. + */ + if (phys_enc->hw_intf->cap->type !=3D INTF_DP && timing->compression_en) { + timing->width =3D timing->width / 3; /* XXX: don't assume 3:1 compressio= n ratio */ + timing->xres =3D timing->width; + } } =20 static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *ti= ming) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index e8b8908d3e12..d6fe45a6da2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -166,10 +166,21 @@ static void dpu_hw_intf_setup_timing_engine(struct dp= u_hw_intf *ctx, * video timing. It is recommended to enable it for all cases, except * if compression is enabled in 1 pixel per clock mode */ + if (!p->compression_en || p->wide_bus_en) + intf_cfg2 |=3D INTF_CFG2_DATA_HCTL_EN; + if (p->wide_bus_en) - intf_cfg2 |=3D INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; + intf_cfg2 |=3D INTF_CFG2_DATABUS_WIDEN; =20 data_width =3D p->width; + if (p->wide_bus_en && !dp_intf) + data_width =3D p->width >> 1; + + if (p->compression_en) + intf_cfg2 |=3D INTF_CFG2_DCE_DATA_COMPRESS; + + if (p->compression_en && dp_intf) + DPU_ERROR("missing adjustments for DSC+DP\n"); =20 hsync_data_start_x =3D hsync_start_x; hsync_data_end_x =3D hsync_start_x + data_width - 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.h index c539025c418b..15a5fdadd0a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params { u32 hsync_skew; =20 bool wide_bus_en; + bool compression_en; }; =20 struct dpu_hw_intf_prog_fetch { --=20 2.26.1 From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95FCBC46CC8 for ; Tue, 14 Nov 2023 23:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234212AbjKNXAj (ORCPT ); Tue, 14 Nov 2023 18:00:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbjKNXAg (ORCPT ); Tue, 14 Nov 2023 18:00:36 -0500 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22D19E1 for ; Tue, 14 Nov 2023 15:00:33 -0800 (PST) Received: by mail-qk1-x72c.google.com with SMTP id af79cd13be357-778711ee748so395804285a.2 for ; Tue, 14 Nov 2023 15:00:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002832; x=1700607632; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w/GFqO4G/MklaH9jw4JV/Pzz1KPVstRySwUanh5xWC0=; b=ZtISVJTJCYZ6elDfWkkj9pMRaQj8ZioTh87/QBFBA+Gyzikb7AWrcgrEPKvpJakv21 HQK0j9aczdpBOXBCRFxn1gPW7nGRAhKjZbWMyNjT2CcWtKmIDL5/itoVUTuuAy8BDK88 SqYlIjZdbXtcucm7TAC/zS9HwXeydJyAkRO5DVD6F5AUaNB91sXw6mFCPKv6RIBIFTjY YFQy6irU8RPj+CtG0Wp49yeq3BPVyzzACOgcvWq9UZE/SC2n0OUkwvF5tnx0w5e32yhZ 2Gk/vH2NnslvKMNc7csFCI+xx5eTafoIIFL0eoavaqlapmAUauVy+WlopKNKINBmaAdp /UPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002832; x=1700607632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w/GFqO4G/MklaH9jw4JV/Pzz1KPVstRySwUanh5xWC0=; b=CKQsVi8UB9BvCzspb/dowgklCsb5FbX7k2rP7gA8catH75px3rSlKgr803WCVE1ED+ D46AUZUhRuWPNzLOA/aJn9+3vCTwjEmvnEVEQPgn1k2xrN44BFPRh5ZXze17ZC0ivAQa ZBh2rFvx1m4kKKSLiodY9a9iUUtUyZViDJfswAWV60Hp0tTFacZkTt3YuRWMxdR3KaeB x2xQOdjRug88nZKehjZCQnncQL50OkraMcs8GMIhQTNt9WoaNIn0bs3oeRPLYUKJ5TDe Tdb6w6j8gPsiVdBGcMiwf00KCq/FqIYbqfVBZbM2DPZyGwReee/ZU7QMFRi9B1sAjEWI l+XA== X-Gm-Message-State: AOJu0Yz5Au0XFAz9CG5QIGlQpG62xcssXav1jYVxH6iKVYsqfMpisw/a xlidRXfF4PnzWHhjc53z3InEkQ== X-Google-Smtp-Source: AGHT+IGs8pOHCMY63Ix8FFyLk36FFEv+XiIXC0agrgFQ+oxUKW/tRhs6EBRxYa3gRpVrFgUGoNzaIw== X-Received: by 2002:ad4:5987:0:b0:677:a0a5:c226 with SMTP id ek7-20020ad45987000000b00677a0a5c226mr3522207qvb.19.1700002832113; Tue, 14 Nov 2023 15:00:32 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:31 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled Date: Tue, 14 Nov 2023 17:58:30 -0500 Message-Id: <20231114225857.19702-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The value returned by msm_dsi_wide_bus_enabled() doesn't match what the driver is doing in video mode. Fix that by actually enabling widebus for video mode. Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/ds= i.xml.h index 2a7d980e12c3..f0b3cdc020a1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -231,6 +231,7 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum d= si_traffic_mode val) #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 +#define DSI_VID_CFG0_DATABUS_WIDEN 0x02000000 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 =20 #define REG_DSI_VID_CFG1 0x0000001c diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index deeecdfd6c4e..f2c1cbd08d4d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -745,6 +745,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_ho= st, data |=3D DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); data |=3D DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); data |=3D DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); + if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) + data |=3D DSI_VID_CFG0_DATABUS_WIDEN; dsi_write(msm_host, REG_DSI_VID_CFG0, data); =20 /* Do not swap RGB colors */ --=20 2.26.1 From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9F84C46CCB for ; Tue, 14 Nov 2023 23:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234215AbjKNXAq (ORCPT ); Tue, 14 Nov 2023 18:00:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234216AbjKNXAl (ORCPT ); Tue, 14 Nov 2023 18:00:41 -0500 Received: from mail-qv1-xf2f.google.com (mail-qv1-xf2f.google.com [IPv6:2607:f8b0:4864:20::f2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23B7FE7 for ; Tue, 14 Nov 2023 15:00:35 -0800 (PST) Received: by mail-qv1-xf2f.google.com with SMTP id 6a1803df08f44-66d0169cf43so37059056d6.3 for ; Tue, 14 Nov 2023 15:00:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002835; x=1700607635; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3bXNM4Q60WzU91mEPZf4VyqZpLI234VBPPnXZJAmol4=; b=R8MWxDcMWe1VEmAnOehN4DLkrTan11W0aUc3k7OwL8Cpdc46fN6MwRWzdT0eCHU2aZ ocpQtVtA02xwq1HVOmg/hYd0jg9lB7YCLzyyRkiLk9x74CJft+Drs7MnacJDDYD/QnX9 oKC4S0ZWbgjIMj6bgS2O4ElFPDj8MpNuya+3OyaPJS+RR2CkCGnrgmjbgrdg+/1ZcyBl k95gy28+a0tBXq0tQKXzmrmy5vw+/a4EHLvqXhLF6bh2ArFvVvuM9CSXX0IS0SgEamBT jmFoQ2irlhQ+r+Y6RqlAg2kV570gNR/z3+3/gkOd49Uy9dvxXof5uJdzCYOUOIBPsLUt 308g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002835; x=1700607635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3bXNM4Q60WzU91mEPZf4VyqZpLI234VBPPnXZJAmol4=; b=bxP8y3pVSLZe2l7XApU+V+usJLvSXZJ6t9fb0XstQJ/OJGttaOjHKyJ8VqZ/2c7/ob c+C5hbZMvP13NgBHkL5vj/TtD2p88/QmygQoq8xvjb2U8zAjqa6ovNvGGBjSJ08Dqx0g KpFv2SC7RlFa2kQVZjSTSrguISPET6Ir7OB7ZFcOLFlyA0mW+JtGv29EmuNRIpZ1ku4P NXf7hDm7UC6wJZtku0DDXHiM8HBamEJTYIyTkvqNu+Xk8Q2b8fy63KOu4j7vMqsRU0DD uP1PBdklgsIPu2wFdtBRDZ3B3BKSmzqYzYYYFKbYUtp6ubXInBcXPUKfpWG4UDO/rMgu w2ww== X-Gm-Message-State: AOJu0YzcSxEaZzQQs70rhGz18HV0o25Fmiue2dxOXHGAJDLoqe/sW3Mr P+8kc9cB/Xt27yWCu87aD44i8A== X-Google-Smtp-Source: AGHT+IHCQG3eL93xOKOvyP2tHydGdXl7lNnMKJaAkchLjAmxahJp9qdvYkmh1PrCIEgA8PmuVIkUJA== X-Received: by 2002:ad4:544b:0:b0:677:af51:da43 with SMTP id h11-20020ad4544b000000b00677af51da43mr3858770qvt.0.1700002834910; Tue, 14 Nov 2023 15:00:34 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:34 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , Vinod Koul , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC) Date: Tue, 14 Nov 2023 17:58:31 -0500 Message-Id: <20231114225857.19702-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt=3D=3D1 cases at least). Fixes: 08802f515c3 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index f2c1cbd08d4d..66f198e21a7e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -849,6 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *= msm_host, bool is_cmd_mod u32 slice_per_intf, total_bytes_per_intf; u32 pkt_per_line; u32 eol_byte_num; + u32 bytes_per_pkt; =20 /* first calculate dsc parameters and then program * compress mode registers @@ -856,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *= msm_host, bool is_cmd_mod slice_per_intf =3D msm_dsc_get_slices_per_intf(dsc, hdisplay); =20 total_bytes_per_intf =3D dsc->slice_chunk_size * slice_per_intf; + bytes_per_pkt =3D dsc->slice_chunk_size; /* * slice_per_pkt; */ =20 eol_byte_num =3D total_bytes_per_intf % 3; =20 @@ -893,6 +895,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *= msm_host, bool is_cmd_mod dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); } else { + reg |=3D DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); } } --=20 2.26.1 From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A18CC46CC8 for ; Tue, 14 Nov 2023 23:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234198AbjKNXAu (ORCPT ); Tue, 14 Nov 2023 18:00:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234233AbjKNXAm (ORCPT ); Tue, 14 Nov 2023 18:00:42 -0500 Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95E1F100 for ; Tue, 14 Nov 2023 15:00:38 -0800 (PST) Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-5a82f176860so71592837b3.1 for ; Tue, 14 Nov 2023 15:00:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002838; x=1700607638; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cpJg20SvqJHFde7hdRwbQhfmXK7eKDJA+6y+igvktAk=; b=CaIrtYL5zP0EobCPzSK6v6WsO7JTWvxsYT2Fk+qkRLqrw8VCSNwwlWuBlhvXZMTRp1 TqAZbUOTuW0OOJvdX5DTGc8ow89MFeXVDCwzfS+z1QqnZhroFynj/pLQfTkjUvTqv/Xl lNXfDC7TbkWDJUYCtrihj7tMBipBRxaAmts6TAtUaspKMyHjkvD2N7G5gH7X+98NliLA tp/yXHHr36EZxroiykF33hgrv25gzDV4cp3qge/d14LASuA/eCq8z32bUbkkjzPMlzpq oSYkENDpt3F3JyDHDbSZlBYSjk2V2GeWmsfumMZUOFNKZibTv7YNaAtgG3iDqbynJ6y0 EKIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002838; x=1700607638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cpJg20SvqJHFde7hdRwbQhfmXK7eKDJA+6y+igvktAk=; b=Vn7YtOzBDZeLBGOJfeP46ILbO8Qn5mWxPLqQw5QuPgeCG0bgnUOG0Hw0IBfENmgmlu W/SjigRAJvurLwZpwKUFup042u7W4PYc+eCPqRp+yimjoQ6vEiheC7US4vqvQkHiuB76 RT2Rw9zrYBNEX0p0ZuBpTSNJM9XEi25lIoGH7p/RO3uf1EPnXHrliuC3haQlSJmeGFNu j64Ue63+WnVzmC9DNDplc2l/4IdyttcPakInHUtyecNsZUqF+q0LTAMkHdTxvK0KfU+V q5/2gQURwu2mvBhRaioD5KYskLipifompfVKnklG3KCz7vjB2lkV/xoxMDGtzWtYDjfS S6Gw== X-Gm-Message-State: AOJu0Yzr5EWPHUTwRM7sQzgIFlTQhkVqTOj3BirsYTdXDgQLP/wiA/ES UWmiZF+JkAJp6HI1aLxgdQWuGQ== X-Google-Smtp-Source: AGHT+IF625S3cBQuZUFbUGBAhZkGCmiGu+ZC9noNuDSK6oc2pQ7dDTxwb4mFW7Ih4VTIW4LqjLUQKA== X-Received: by 2002:a0d:ca84:0:b0:5a7:bfbf:1bbb with SMTP id m126-20020a0dca84000000b005a7bfbf1bbbmr11185827ywd.17.1700002837716; Tue, 14 Nov 2023 15:00:37 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:37 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding Date: Tue, 14 Nov 2023 17:58:32 -0500 Message-Id: <20231114225857.19702-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 66f198e21a7e..842765063b1b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -877,6 +877,8 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *= msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits + * + * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ reg |=3D DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |=3D DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); --=20 2.26.1 From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D444FC46CC7 for ; Tue, 14 Nov 2023 23:00:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234238AbjKNXA5 (ORCPT ); Tue, 14 Nov 2023 18:00:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234229AbjKNXAt (ORCPT ); Tue, 14 Nov 2023 18:00:49 -0500 Received: from mail-yw1-x1134.google.com (mail-yw1-x1134.google.com [IPv6:2607:f8b0:4864:20::1134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2ECA10B for ; Tue, 14 Nov 2023 15:00:41 -0800 (PST) Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-5a7b3d33663so72278737b3.3 for ; Tue, 14 Nov 2023 15:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002841; x=1700607641; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QnYJwckhVUb/hQ+VqWd+HwwnYfkR02viqwW11QKBHpA=; b=UPLkPeCLKjdHSxSONMgOALl44MCDYR2/xtta79y9c8MHsYov2B+4wcGxY7ibBfHBpa fXxeFAUTz38x93wIil+fU81nn4Z9Vh4cQJJP3yM0O/MxG+w5SbIMKdFkXz4lu6L6kcrn LattTY1ozD6jZ8Q1l58qO0kDsumdz1LmK+KiwLy0K/DTCic8hFgGunKtpqIAXwyu6v9o 5K5J6fSA2329RlST2/CzaJM5DBqSol3bfRp85AM4fN6U7rLfV4NjmuJ8PPSyfjoJK/+T Jv853r1jaloyLlnRQClQvbHFZbpL9l6/ifKNOt5gBe85V/9KY5VPQY/I+6dcaUbRVpo7 /6wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002841; x=1700607641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QnYJwckhVUb/hQ+VqWd+HwwnYfkR02viqwW11QKBHpA=; b=hrvYMRsj3tqFaBu+ABdNgbBrtY7EM4xuV7mZYDVdMK7MncYzzrz8z2MHmEQKu32+4n 0ysCPMna8IYbO5rLcIoOQCZCHTA7iOzo+yf71vE0Z5eoi/2hAm9gKD7oHMMWnqnZGUXe ZDfuJk7vYp2TngBfCCwW/Ll7xJJGMXUmRKW5c6UvhAo1NiYngSAufpxAI+M92Bt59PoX UgVPRn7ICdYGWylTltx92Hf9Um0k2TrbIkLYolV+WI7+GcomdddedW4zWJ0lVmPyanMi L6pCrgzLeZYDbbSeVKlkZzPj46Kyq0YSVjkxQGVP/QM6LNzojzJaqgmiTTrYxzgfrPmJ L1pQ== X-Gm-Message-State: AOJu0YxGvIGni/00puD/FS1ZraBmJXyeBBoO1XZcIH0PZiNmQd4Rxfgv vPByO59mvCtqcjNcZyNRJrsNew== X-Google-Smtp-Source: AGHT+IF5YfJuojzCU5ZWpyNCZKZW27YiSBpBSE/rs8E1m68mg6G6/rODESlNkQJ5KMcm5C8qahqevA== X-Received: by 2002:a81:5241:0:b0:5be:94a6:d919 with SMTP id g62-20020a815241000000b005be94a6d919mr12307437ywb.25.1700002840841; Tue, 14 Nov 2023 15:00:40 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:40 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 Date: Tue, 14 Nov 2023 17:58:33 -0500 Message-Id: <20231114225857.19702-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a dsc_slice_per_pkt field to mipi_dsi_device struct and the necessary changes to msm driver to support this field. Note that the removed "pkt_per_line =3D slice_per_intf * slice_per_pkt" comment is incorrect. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi_host.c | 25 ++++++++++--------------- include/drm/drm_mipi_dsi.h | 1 + 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 842765063b1b..892a463a7e03 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -161,6 +161,7 @@ struct msm_dsi_host { =20 struct drm_display_mode *mode; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; =20 /* connected device info */ unsigned int channel; @@ -857,17 +858,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host= *msm_host, bool is_cmd_mod slice_per_intf =3D msm_dsc_get_slices_per_intf(dsc, hdisplay); =20 total_bytes_per_intf =3D dsc->slice_chunk_size * slice_per_intf; - bytes_per_pkt =3D dsc->slice_chunk_size; /* * slice_per_pkt; */ + bytes_per_pkt =3D dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; =20 eol_byte_num =3D total_bytes_per_intf % 3; - - /* - * Typically, pkt_per_line =3D slice_per_intf * slice_per_pkt. - * - * Since the current driver only supports slice_per_pkt =3D 1, - * pkt_per_line will be equal to slice per intf for now. - */ - pkt_per_line =3D slice_per_intf; + pkt_per_line =3D slice_per_intf / msm_host->dsc_slice_per_pkt; =20 if (is_cmd_mode) /* packet data type */ reg =3D DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_= LONG_WRITE); @@ -1004,12 +998,8 @@ static void dsi_timing_setup(struct msm_dsi_host *msm= _host, bool is_bonded_dsi) else /* * When DSC is enabled, WC =3D slice_chunk_size * slice_per_pkt + 1. - * Currently, the driver only supports default value of slice_per_pkt = =3D 1 - * - * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info - * and adjust DSC math to account for slice_per_pkt. */ - wc =3D msm_host->dsc->slice_chunk_size + 1; + wc =3D msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + = 1; =20 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | @@ -1636,8 +1626,13 @@ static int dsi_host_attach(struct mipi_dsi_host *hos= t, msm_host->lanes =3D dsi->lanes; msm_host->format =3D dsi->format; msm_host->mode_flags =3D dsi->mode_flags; - if (dsi->dsc) + if (dsi->dsc) { msm_host->dsc =3D dsi->dsc; + msm_host->dsc_slice_per_pkt =3D dsi->dsc_slice_per_pkt; + /* for backwards compatibility, assume 1 if not set */ + if (!msm_host->dsc_slice_per_pkt) + msm_host->dsc_slice_per_pkt =3D 1; + } =20 /* Some gpios defined in panel DT need to be controlled by host */ ret =3D dsi_host_init_panel_gpios(msm_host, &dsi->dev); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index c9df0407980c..3e32fa52d94b 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -193,6 +193,7 @@ struct mipi_dsi_device { unsigned long hs_rate; unsigned long lp_rate; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; }; =20 #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:" --=20 2.26.1 From nobody Sat Feb 7 11:18:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C20EEC46CC7 for ; Tue, 14 Nov 2023 23:01:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234271AbjKNXBH (ORCPT ); Tue, 14 Nov 2023 18:01:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234279AbjKNXA5 (ORCPT ); Tue, 14 Nov 2023 18:00:57 -0500 Received: from mail-vk1-xa2e.google.com (mail-vk1-xa2e.google.com [IPv6:2607:f8b0:4864:20::a2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3E9E191 for ; Tue, 14 Nov 2023 15:00:48 -0800 (PST) Received: by mail-vk1-xa2e.google.com with SMTP id 71dfb90a1353d-4af5ea40b7bso1457337e0c.2 for ; Tue, 14 Nov 2023 15:00:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek.ca; s=google; t=1700002847; x=1700607647; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YR/mkTlXJRgIJS/EJMZQRz4ww5S2W5Npa8fLQfW52YM=; b=MS2inVkaeDGbJxVw5+PruF/NKQKcPRJECBHuO9yFmSXxrAe3+5QnsdXeq9J7IqECHk Y07HjLDNF+1xfeiYQh/MNn6SxcuPlHMqvmJmoiFRqlcjFLVwgkfW9UHfIKFL/7K0+NyR GXvg87qHmmqeai5eSmkH4+50V5ZeIZRTUZqCFszCzF4D/7ZCv3VkIYAYcL7fjVfTfX9m 5IwHxXko7gFzA1N9AvC0j5thyA9sZXR6HAq1G6TlOEYOVrA1upNchVTbvBzw0fT18Y5n GZA7Sg5HeC22w87JjpaRN0jjj66+K9WjsDjLTKUCnonwjFeVnaCay72kkeu4lLGOBnQa Vdrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700002847; x=1700607647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YR/mkTlXJRgIJS/EJMZQRz4ww5S2W5Npa8fLQfW52YM=; b=pJf2XuuRsbblaAcfZPSuKv9Z5sDK7o91in0cFPGWZBawnIEes9fXORLADzffEwSZhY ZM9veYS+kU6bglCiw6jzdproJX8HfkBOalA7jiS2HDKIF9fK0H30UxDJnM1cE3SjW7Uh gOJl748JhqExvuRcZI4F2FAVfbjGK/uJtFYbeN/hlWBcvgNd/SIJFC8RnddClDv9Z3Kj 2uJ9K6Qzugn0ERdjRkucFh9xA/FfPnu2/VtS5VI77WNCTdw6oHjfVMm5AT23e5N1crOM EpUuLCmSY/OmlAnNvrlW+2kQR0GbEFV8n3oYkUNeu98GlpsT2w4UcN5zfJ7P/eweiiya +TVw== X-Gm-Message-State: AOJu0YzTKBjqcDaRsCA+igmhzVCgt7vUkNKoOtPsKKbDmiKRvbVy6iBh P6/RMe+PIoijACwZu4/2GZLtfA== X-Google-Smtp-Source: AGHT+IGEipMZ0wWdCFEW37YaqFstmZB087eBM8BroWKdjsRAujSSep+py5so9+Y1GvtCk8GaGlxZ6A== X-Received: by 2002:a67:e002:0:b0:45d:8f83:e10f with SMTP id c2-20020a67e002000000b0045d8f83e10fmr10524052vsl.4.1700002847082; Tue, 14 Nov 2023 15:00:47 -0800 (PST) Received: from localhost.localdomain (modemcable125.110-19-135.mc.videotron.ca. [135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:46 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , Jessica Zhang , Jiasheng Jiang , Doug Anderson , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 6/6] drm/msm/dsi: fix DSC for the bonded DSI case Date: Tue, 14 Nov 2023 17:58:34 -0500 Message-Id: <20231114225857.19702-7-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the bonded DSI case, DSC pic_width and timing calculations should use the width of a single panel instead of the total combined width. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi.h | 3 ++- drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +++++++++++--------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 28379b1af63f..3a641e69447c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -93,7 +93,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + bool is_bonded_dsi); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 892a463a7e03..cf06736e5a60 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -940,8 +940,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_h= ost, bool is_bonded_dsi) mode->hdisplay, mode->vdisplay); return; } - - dsc->pic_width =3D mode->hdisplay; + dsc->pic_width =3D hdisplay; dsc->pic_height =3D mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); =20 @@ -952,6 +951,11 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_= host, bool is_bonded_dsi) if (ret) return; =20 + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) + dsi_update_dsc_timing(msm_host, false, hdisplay); + else + dsi_update_dsc_timing(msm_host, true, hdisplay); + /* Divide the display by 3 but keep back/font porch and * pulse width same */ @@ -968,9 +972,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_h= ost, bool is_bonded_dsi) } =20 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); - dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -989,9 +990,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_h= ost, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); - /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) wc =3D hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; @@ -2479,7 +2477,8 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_hos= t *host, } =20 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + bool is_bonded_dsi) { struct msm_dsi_host *msm_host =3D to_msm_dsi_host(host); struct drm_dsc_config *dsc =3D msm_host->dsc; @@ -2489,6 +2488,9 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mi= pi_dsi_host *host, if (!msm_host->dsc) return MODE_OK; =20 + if (is_bonded_dsi) + pic_width =3D mode->hdisplay / 2; + if (pic_width % dsc->slice_width) { pr_err("DSI: pic_width %d has to be multiple of slice %d\n", pic_width, dsc->slice_width); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/ds= i/dsi_manager.c index 896f369fdd53..2ca1a7ca3659 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -455,7 +455,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(s= truct drm_bridge *bridge, return MODE_ERROR; } =20 - return msm_dsi_host_check_dsc(host, mode); + return msm_dsi_host_check_dsc(host, mode, IS_BONDED_DSI()); } =20 static const struct drm_bridge_funcs dsi_mgr_bridge_funcs =3D { --=20 2.26.1