From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB2AC4332F for ; Tue, 14 Nov 2023 14:13:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233372AbjKNONi (ORCPT ); Tue, 14 Nov 2023 09:13:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231903AbjKNONg (ORCPT ); Tue, 14 Nov 2023 09:13:36 -0500 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4EE21B6 for ; Tue, 14 Nov 2023 06:13:32 -0800 (PST) Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-779d57a3343so4573385a.1 for ; Tue, 14 Nov 2023 06:13:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971212; x=1700576012; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XMkgyvuzGYJaW56Gm45FtsJL6qswpkealapQbWKCBRw=; b=uIBDpDTIMu9VGA3u8M1nldKSmpn97SZfT6P0b+VQMlGAkkAqbaxeg3hiCjpXCSUVvF b05jV2ToGjDaIh84IQ23PDZKUTdsu7wgWvWTIS0RmrCCJ8/olwSHk4vtoTeYm7SyTG7L 75FU41ZjDUBF2FPZ2lkNRlGBwqAWO/+HiTsSQ/N6ta8upyc/NAC3ecNdpt42giYYabDF TYhUSwAmYHuIDV700z9LIg83/akQ32ZfupFnn7XF1wDkIuURKbqJmQR3xus57ZngSAu1 ds4jhXXJ6JrNXMBB3p1o9X54sjrIt3aIkn7cyGn9NxI/qnSsTcvndwUH/V35LfXWTMdW U+lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971212; x=1700576012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XMkgyvuzGYJaW56Gm45FtsJL6qswpkealapQbWKCBRw=; b=sNi68GnovPKOT3IWyOhvYvlp2xtGiTZBMOnwzeXs0MliW6kMGcCbTeZ2aH2GcxPuib vhKqutOoLh7t2AnVtNjcq77xHU/gF1fgL1L4dvhlpj1svYyttj0VUOxS8gS52YEjgXx8 ZUmYX8gqYAqQIyKAgoQiphd4edtPvOaa32OKKzzlU+lyXTuSeZG2Luxeoaq4mHTUfxYk DgR2N69jUFI8nW4P+06TGELeNJJM+2U5AQGd0t/2MXxWpEtOMmUQH4AJEI+qpouOYg1I U5kUrhFQ59YgnHoDdtZAN1nb8eCPk2LyfKumj5HzkiJT9kU7KtefhItsC2bsl8I1lzxT 3MBw== X-Gm-Message-State: AOJu0YzGVmzN4TBORzh6Jil1pdclobMxZUufDYmVfRElANWlEag+iKlF b+Hrfh4A8cOEVFbJMqDtYT1qkw== X-Google-Smtp-Source: AGHT+IHnMHw8F3ryLSB+7vrra0BH+tHsLT5qn9YR2ZuZzRjWRR16+wgDWF4cMlcUDZPdu8ADN5zYkA== X-Received: by 2002:a05:620a:1aa2:b0:77b:c622:e7fc with SMTP id bl34-20020a05620a1aa200b0077bc622e7fcmr2526334qkb.2.1699971212064; Tue, 14 Nov 2023 06:13:32 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:31 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 01/20] riscv: add ISA extension parsing for Zbc Date: Tue, 14 Nov 2023 09:12:37 -0500 Message-ID: <20231114141256.126749-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Zbc was documented in the dt-bindings but actually not supported in ISA string parsing. Add it. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 06d30526ef3b..afa9abc1a0b0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -57,6 +57,7 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 +#define RISCV_ISA_EXT_ZBC 45 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3785ffc1570..eae14daa5a75 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -176,6 +176,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), --=20 2.42.0 From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C07FCC4332F for ; Tue, 14 Nov 2023 14:13:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233422AbjKNONs (ORCPT ); Tue, 14 Nov 2023 09:13:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233373AbjKNONj (ORCPT ); Tue, 14 Nov 2023 09:13:39 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 177091B9 for ; Tue, 14 Nov 2023 06:13:34 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id af79cd13be357-778a25cad6dso14498085a.0 for ; Tue, 14 Nov 2023 06:13:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971213; x=1700576013; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PrGNrJ4Mz4+id5eBYM8EQz0/YakC3IvStBxc6baL/D0=; b=AUR4TuLvfJbZR3Sib1u+kmcEBsxPLwyVRxWQY5i3BKL0Ev0WusNosIBlHEqH68qx0r KOfHBCqAxxrc5omTFCBVC7yF7rb5inDRTwn4hmoEBWqO4u0YvZmBT2H0TxJaAMn38y6m BzdntVnbsi9wHXILj4WZyXyZH71/23GWoJRuebXX2fztDpstJq49gd7wKnnShEUFDyf4 Z48KH4j++X0VaWC3E2c1j6Nj+96432bQ5qOAPGGTrYlmVlwZf3C+eizECbT/zuTLWl9w wMwAjdnKYDtatFGeGDfSvsdpvmKnRI+dIXQZ6Xm5/nEfL35DaepkwaNhiJXoCu8g2ADy aW7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971213; x=1700576013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PrGNrJ4Mz4+id5eBYM8EQz0/YakC3IvStBxc6baL/D0=; b=XrmVHj2BKK9xOvXdGuKuqS4eW5/qySx2wry3M1htsxTS1CN5foR6uWoFHswBZleKF9 VjErBSl//+QtCcoCtOZVl6MA/Qt9QDlC4wMzTrCnbmrZNRstfRSmRvV+grZX9IDSnM0T 5AgHNoD+EUetKvmOS0gqm9eguWUVXrq/18878zRlOs676p3GRlnyfEwEA2B3w9ge+Ot6 BTayP5StxsosjnXXoB1TKTb780kG2F80snaru6Hiz96StytSdzq4Y75DtBTPT1UCQxas U53QHLC9VD1ysvmWu4unHKSKqV4aduDtZadISNEXrd9kMHAQn13P/RUXpfvTMHbaQj1z m78w== X-Gm-Message-State: AOJu0Ywvgdy9l0tY9BkpOY3H4urN/AhOBvs0l68PBmtRzQgSaUcM0pmG Z8eh/ZYRdwYeDn+zTXBqQ2cXdQ== X-Google-Smtp-Source: AGHT+IFZD2b/EdJCKXaxNJw+Q4jC4YD3sm2mqseVgTheJfANyM9xUv2Lh4hYASCwt6RNtJiG1DYtgw== X-Received: by 2002:a05:620a:28d4:b0:773:a789:cd15 with SMTP id l20-20020a05620a28d400b00773a789cd15mr2089252qkp.6.1699971213032; Tue, 14 Nov 2023 06:13:33 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:32 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 02/20] riscv: hwprobe: export missing Zbc ISA extension Date: Tue, 14 Nov 2023 09:12:38 -0500 Message-ID: <20231114141256.126749-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org While Zba and Zbb were exported through hwprobe, Zbc was not. Export it. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 7b2384de471f..3f71da935a65 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -80,6 +80,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported= , as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as de= fined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index b659ffcfcdb4..aca5abc7ebee 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -30,6 +30,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) +#define RISCV_HWPROBE_EXT_ZBC (1 << 7) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index c712037dbe10..7a40145e9628 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZBB); EXT_KEY(ZBS); EXT_KEY(ZICBOZ); + EXT_KEY(ZBC); #undef EXT_KEY } =20 --=20 2.42.0 From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E4EBC4332F for ; Tue, 14 Nov 2023 14:13:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233384AbjKNONn (ORCPT ); Tue, 14 Nov 2023 09:13:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231903AbjKNONj (ORCPT ); Tue, 14 Nov 2023 09:13:39 -0500 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3765F1B6 for ; Tue, 14 Nov 2023 06:13:35 -0800 (PST) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-77bbe4702a1so4532385a.0 for ; Tue, 14 Nov 2023 06:13:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971214; x=1700576014; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SU/g700ZLyLiX8R4aH7M4U3AIKizV9KTngI03z4llSI=; b=NF+UzazRrsyvg27tEbhXJRGKfsndER4vz71rl8AcPbYpjXzQ7CgV7DzVMtY92/F1Ir qQMgfqHGiyEDl81y4g1OrTVIulMmv4B8Sz+z+5MK4hcgcRlzQm27GBxZmFwLun03Vii1 uk/dFsyMqthoypbiwB7clgYhodVLVU3JuS7mK/3V3twGxyTxaytySYKDmNQxlX1+VO8W gmPn8QqltCkjiuhzbuU87MpFNh23CuZhZ81yrigr5xGJ/AUuKY8x1AJeBYazAHINRxma fE6kNQxOiSEFPzECXInqgHIKJVya50L7z8uc0M9AY2+yEwLd4V6HY+fTte703xRtrMe3 TfdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971214; x=1700576014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SU/g700ZLyLiX8R4aH7M4U3AIKizV9KTngI03z4llSI=; b=e6shP7x63Hc3foyGPHFa0L+qQ4eiJ57hidd7tLs1+2N7jMOkF8vTIxctoDsW+/+1C0 aZ8DKmLCNmstO7Yj0doqAADSL9ioba6pWU0NUQimBjP7H3jgjaIXoqer3Lcx5OZYN4Hl H5OZ8lA2qkrtyop+10vLRIvSBk54hpO9vCRM6h9iMIVBBzV7rlvMzA2nn0fCpmQqzAgE pz3O0iYJDkQVs+B6XfCblsMimgQLQjGGv7kIwSutw5O3FsousotOqOtCWOC9cH+utwTI bNylEViizZ+nJKpztXkPMEpFYP6WGS7HSkfhZsXZIqrjVao7wqJVPt9TTqv4NsCliR0t Icpw== X-Gm-Message-State: AOJu0Yy+da5Q0+dGEvk25V6RhUK4uPrzub6QY3QKgaE83zJnQbyborOO toRPplDRzwh9jQVep/JYV8/t+Q== X-Google-Smtp-Source: AGHT+IEsx2T25BKdVYtuC6/nOhv4dKk0otBx5lnACq1YF4ozL1VqFHzj8lfYhBmRkEJIwgc5CSdyeg== X-Received: by 2002:a05:620a:458b:b0:76e:f686:cad5 with SMTP id bp11-20020a05620a458b00b0076ef686cad5mr2470951qkb.5.1699971214316; Tue, 14 Nov 2023 06:13:34 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:33 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 03/20] riscv: add ISA extension parsing for scalar crypto Date: Tue, 14 Nov 2023 09:12:39 -0500 Message-ID: <20231114141256.126749-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Evan Green The Scalar Crypto specification defines Zk as a shorthand for the Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk, which are all shorthands for various other extensions. The detailed breakdown can be found in their dt-binding entries. Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing "zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk" should generate the following cpuinfo output: "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_z= kt" riscv_isa_ext_data grows a pair of new members, to permit setting the relevant bits for "bundled" extensions, both while parsing the ISA string and the new dedicated extension properties. Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Signed-off-by: Evan Green Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 4 +- arch/riscv/include/asm/hwcap.h | 11 +++ arch/riscv/kernel/cpufeature.c | 118 ++++++++++++++++++++++------ 3 files changed, 109 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index a418c3112cd6..fbdde8b8a47e 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -59,6 +59,8 @@ struct riscv_isa_ext_data { const unsigned int id; const char *name; const char *property; + const unsigned int *subset_ext_ids; + const unsigned int subset_ext_size; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; @@ -67,7 +69,7 @@ extern bool riscv_isa_fallback; =20 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit); +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsi= gned int bit); #define riscv_isa_extension_available(isa_bitmap, ext) \ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) =20 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index afa9abc1a0b0..b0857c64bf6e 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,8 +58,19 @@ #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 #define RISCV_ISA_EXT_ZBC 45 +#define RISCV_ISA_EXT_ZBKB 46 +#define RISCV_ISA_EXT_ZBKC 47 +#define RISCV_ISA_EXT_ZBKX 48 +#define RISCV_ISA_EXT_ZKND 49 +#define RISCV_ISA_EXT_ZKNE 50 +#define RISCV_ISA_EXT_ZKNH 51 +#define RISCV_ISA_EXT_ZKR 52 +#define RISCV_ISA_EXT_ZKSED 53 +#define RISCV_ISA_EXT_ZKSH 54 +#define RISCV_ISA_EXT_ZKT 55 =20 #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_INVALID U32_MAX =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index eae14daa5a75..a2871bceaad9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(riscv_isa_extension_base); * * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. */ -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit) +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsi= gned int bit) { const unsigned long *bmap =3D (isa_bitmap) ? isa_bitmap : riscv_isa; =20 @@ -102,17 +102,53 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_INVALID: + return false; } =20 return true; } =20 -#define __RISCV_ISA_EXT_DATA(_name, _id) { \ - .name =3D #_name, \ - .property =3D #_name, \ - .id =3D _id, \ +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {= \ + .name =3D #_name, \ + .property =3D #_name, \ + .id =3D _id, \ + .subset_ext_ids =3D _subset_exts, \ + .subset_ext_size =3D _subset_exts_size \ } =20 +#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, N= ULL, 0) + +/* Used to declare pure "lasso" extension (Zk for instance) */ +#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SI= ZE(_bundled_exts)) + +static const unsigned int riscv_zk_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKT, +}; + +static const unsigned int riscv_zkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, +}; + +static const unsigned int riscv_zks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -177,7 +213,20 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), @@ -190,6 +239,31 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); =20 +static void __init match_isa_ext(const struct riscv_isa_ext_data *ext, con= st char *name, + const char *name_end, struct riscv_isainfo *isainfo) +{ + if ((name_end - name =3D=3D strlen(ext->name)) && + !strncasecmp(name, ext->name, name_end - name)) { + /* + * If this is a bundle, enable all the ISA extensions that + * comprise the bundle. + */ + if (ext->subset_ext_size) { + for (int i =3D 0; i < ext->subset_ext_size; i++) { + if (riscv_isa_extension_check(ext->subset_ext_ids[i])) + set_bit(ext->subset_ext_ids[i], isainfo->isa); + } + } + + /* + * This is valid even for bundle extensions which uses the RISCV_ISA_EXT= _INVALID id + * (rejected by riscv_isa_extension_check()). + */ + if (riscv_isa_extension_check(ext->id)) + set_bit(ext->id, isainfo->isa); + } +} + static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struc= t riscv_isainfo *isainfo, unsigned long *isa2hwcap, const char *isa) { @@ -322,14 +396,6 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc if (*isa =3D=3D '_') ++isa; =20 -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext =3D=3D strlen(name)) && \ - !strncasecmp(ext, name, strlen(name)) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - if (unlikely(ext_err)) continue; if (!ext_long) { @@ -341,10 +407,8 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc } } else { for (int i =3D 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } -#undef SET_ISA_EXT_MAP } } =20 @@ -443,18 +507,26 @@ static int __init riscv_fill_hwcap_from_ext_list(unsi= gned long *isa2hwcap) } =20 for (int i =3D 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data *ext =3D &riscv_isa_ext[i]; + if (of_property_match_string(cpu_node, "riscv,isa-extensions", - riscv_isa_ext[i].property) < 0) + ext->property) < 0) continue; =20 - if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) - continue; + if (ext->subset_ext_size) { + for (int j =3D 0; j < ext->subset_ext_size; j++) { + if (riscv_isa_extension_check(ext->subset_ext_ids[i])) + set_bit(ext->subset_ext_ids[j], isainfo->isa); + } + } =20 - /* Only single letter extensions get set in hwcap */ - if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) - this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + if (riscv_isa_extension_check(ext->id)) { + set_bit(ext->id, isainfo->isa); =20 - set_bit(riscv_isa_ext[i].id, isainfo->isa); + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) + this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + } } =20 of_node_put(cpu_node); --=20 2.42.0 From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D41BC4167B for ; Tue, 14 Nov 2023 14:13:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231903AbjKNONp (ORCPT ); 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:34 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Date: Tue, 14 Nov 2023 09:12:40 -0500 Message-ID: <20231114141256.126749-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the following scalar crypto extensions through hwprobe: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 27 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 9 +++++++++ arch/riscv/kernel/sys_riscv.c | 10 ++++++++++ 3 files changed, 46 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 3f71da935a65..3a18a31e32c3 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -83,6 +83,33 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as de= fined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined + in version 1.0 of the Scalar Crypto ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index aca5abc7ebee..624abd5cde29 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -31,6 +31,15 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) #define RISCV_HWPROBE_EXT_ZBC (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 9) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 10) +#define RISCV_HWPROBE_EXT_ZKND (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 12) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) +#define RISCV_HWPROBE_EXT_ZKT (1 << 16) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 7a40145e9628..43aa66e71418 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -163,6 +163,16 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, EXT_KEY(ZBS); EXT_KEY(ZICBOZ); EXT_KEY(ZBC); + + EXT_KEY(ZBKB); + EXT_KEY(ZBKC); + EXT_KEY(ZBKX); + EXT_KEY(ZKND); + EXT_KEY(ZKNE); + EXT_KEY(ZKNH); + EXT_KEY(ZKSED); + EXT_KEY(ZKSH); + EXT_KEY(ZKT); #undef EXT_KEY } =20 --=20 2.42.0 From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B806C4167B for ; Tue, 14 Nov 2023 14:13:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233392AbjKNONt (ORCPT ); Tue, 14 Nov 2023 09:13:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233379AbjKNONl (ORCPT ); Tue, 14 Nov 2023 09:13:41 -0500 Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D09C10D for ; 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:36 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Date: Tue, 14 Nov 2023 09:12:41 -0500 Message-ID: <20231114141256.126749-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for scalar crypto ISA extensions: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c91ab0e46648..a3803b22cf4f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -190,12 +190,92 @@ properties: multiplication as ratified at commit 6d33919 ("Merge pull requ= est #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitm= anip. =20 + - const: zbkb + description: + The standard Zbkb bitmanip instructions for cryptography as ra= tified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkc + description: + The standard Zbkc carry-less multiply instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkx + description: + The standard Zbkx crossbar permutation instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zbs description: | The standard Zbs bit-manipulation extension for single-bit instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zk + description: + The standard Zk Standard Scalar cryptography extension as rati= fied + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkn + description: + The standard Zkn NIST algorithm suite extensions as ratified in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zknd + description: | + The standard Zknd for NIST suite: AES decryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkne + description: | + The standard Zkne for NIST suite: AES encryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zknh + description: | + The standard Zknh for NIST suite: hash function instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkr + description: + The standard Zkr entropy source extension as ratified in versi= on + 1.0 of RISC-V Cryptography Extensions Volume I specification. + This string being present means that the CSR associated to this + extension is accessible at the privilege level to which that + device-tree has been provided. + + - const: zks + description: + The standard Zks ShangMi algorithm suite extensions as ratifie= d in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zksed + description: | + The standard Zksed for ShangMi suite: SM4 block cipher instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zksh + description: | + The standard Zksh for ShangMi suite: SM3 hash function instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zkt + description: + The standard Zkt for data independent execution latency as rat= ified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zicbom description: The standard Zicbom extension for base cache management operat= ions as --=20 2.42.0 From nobody Tue Dec 30 14:49:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E20CC4332F for ; Tue, 14 Nov 2023 14:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233468AbjKNONz (ORCPT ); Tue, 14 Nov 2023 09:13:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233391AbjKNONp (ORCPT ); Tue, 14 Nov 2023 09:13:45 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2640D43 for ; Tue, 14 Nov 2023 06:13:40 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id af79cd13be357-779d0c05959so55567185a.1 for ; Tue, 14 Nov 2023 06:13:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971220; x=1700576020; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+g4r4bjsySLwk77l9XIM5/wH2ybzV4V3VQlpQWbskRU=; b=K53flC5fBqqG+5jhqhEWH4JsAdSVYGIMx8oEfpdz0EddE5AB43a1OkbAMUfig20mPE 02xi73vNlYddWGJ20mkCK8/5F9gZU6eLWSSxwDt5CaXc5slzshAUu7XvKB42D8okBrKP HZPAPWs1v2wq8+ZzMJ4x3mO67PxWeWgyQJCRoG92NdiphYairvgBxDPs3T1lsgDixNLu NXZG8DZRD/uuq+lN1zeaG/fIvdlYoAeCHf6dFwkP+h8o6lLs3cBv4dkO/VrJOvJvjGUp Kh8O7mOBAnnbRcNyAxze/9ml1L1OC5Wj4m6c41Ex4Xo9PK1ZbZqRfr75n4Gt6OTlrzo1 XyYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971220; x=1700576020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+g4r4bjsySLwk77l9XIM5/wH2ybzV4V3VQlpQWbskRU=; b=nWghlxdorep8cUEncS0rMntlEwpYfwLsBwKPyj12ZbwcDTtXQ+e/yzy9NjDky44x65 15cmFBnlZzUfdVzWTVgn0yHp7So22fbf6M+aiIvJsD59VFa1l0TWPQNsrjXmm+Nc9hHZ /fRRO/54waNbJpXsvU7gWPj1kXIjr+gPAaki+nDMk0dVh86UgeDAdokQ8Se/dupMbUvj mx5qHC1of9AJ91vyPlIwnuu9DOF/ZHtEy8SEs48VwY2mqWJaUcdbIiv+xcE5SNtvsF9N ThFWPi/CqNemvei5aWCxUzo9U2NUF1xJXT6dCt4+OMRwEk4saWpXwSqggWMTnjCAH6If UNrA== X-Gm-Message-State: AOJu0YxYt5j5iexyvLgxUwjBulSpcw6KL/XKK26fxRrcofWqStpiZVTr AB4br9GC8kuC/mJM2Q5FzaXlIg== X-Google-Smtp-Source: AGHT+IH7kpjtCOGgFTVn0VXhNLv2IfiHOGHCQO3TA/WLBqK62He/u3Tqp6my3moeV85XJ3AUbedh2w== X-Received: by 2002:a05:620a:3945:b0:776:f188:eee6 with SMTP id qs5-20020a05620a394500b00776f188eee6mr2482783qkn.2.1699971218961; Tue, 14 Nov 2023 06:13:38 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:37 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 06/20] riscv: add ISA extension parsing for vector crypto Date: Tue, 14 Nov 2023 09:12:42 -0500 Message-ID: <20231114141256.126749-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing of some Zv* vector crypto ISA extensions that are mentioned in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions are the following: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 12 ++++++- arch/riscv/kernel/cpufeature.c | 64 ++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b0857c64bf6e..477254668d82 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -68,8 +68,18 @@ #define RISCV_ISA_EXT_ZKSED 53 #define RISCV_ISA_EXT_ZKSH 54 #define RISCV_ISA_EXT_ZKT 55 +#define RISCV_ISA_EXT_ZVBB 56 +#define RISCV_ISA_EXT_ZVBC 57 +#define RISCV_ISA_EXT_ZVKB 58 +#define RISCV_ISA_EXT_ZVKG 59 +#define RISCV_ISA_EXT_ZVKNED 60 +#define RISCV_ISA_EXT_ZVKNHA 61 +#define RISCV_ISA_EXT_ZVKNHB 62 +#define RISCV_ISA_EXT_ZVKSED 63 +#define RISCV_ISA_EXT_ZVKSH 64 +#define RISCV_ISA_EXT_ZVKT 65 =20 -#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX =20 #ifdef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a2871bceaad9..c4d0f16c29b9 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -123,6 +123,10 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SI= ZE(_bundled_exts)) =20 +/* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ +#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + static const unsigned int riscv_zk_bundled_exts[] =3D { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -149,6 +153,50 @@ static const unsigned int riscv_zks_bundled_exts[] =3D= { RISCV_ISA_EXT_ZKSH }; =20 +#define RISCV_ISA_EXT_ZVKN \ + RISCV_ISA_EXT_ZVKNED, \ + RISCV_ISA_EXT_ZVKNHB, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN +}; + +static const unsigned int riscv_zvknc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvkng_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVKG +}; + +#define RISCV_ISA_EXT_ZVKS \ + RISCV_ISA_EXT_ZVKSED, \ + RISCV_ISA_EXT_ZVKSH, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS +}; + +static const unsigned int riscv_zvksc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvksg_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVKG +}; + +static const unsigned int riscv_zvbb_exts[] =3D { + RISCV_ISA_EXT_ZVKB +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -227,6 +275,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), + __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), + __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), + __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), + __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E085EC4167D for ; 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:39 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 07/20] riscv: hwprobe: export vector crypto ISA extensions Date: Tue, 14 Nov 2023 09:12:43 -0500 Message-ID: <20231114141256.126749-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zv* vector crypto ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Zvkn and Zvks are ommited since they are a superset of other extensions. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++ arch/riscv/kernel/sys_riscv.c | 13 ++++++++++++ 3 files changed, 53 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 3a18a31e32c3..a08fcd899b6d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -110,6 +110,36 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined in version 1.0 of the Scalar Crypto ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 624abd5cde29..89628a76ca04 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -40,6 +40,16 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZKSED (1 << 14) #define RISCV_HWPROBE_EXT_ZKSH (1 << 15) #define RISCV_HWPROBE_EXT_ZKT (1 << 16) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 17) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 26) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 43aa66e71418..9bbcd7334d96 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -173,6 +173,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, EXT_KEY(ZKSED); EXT_KEY(ZKSH); EXT_KEY(ZKT); + + if (has_vector()) { + EXT_KEY(ZVBB); + EXT_KEY(ZVBC); + EXT_KEY(ZVKB); + EXT_KEY(ZVKG); + EXT_KEY(ZVKNED); + EXT_KEY(ZVKNHA); + EXT_KEY(ZVKNHB); + EXT_KEY(ZVKSED); + EXT_KEY(ZVKSH); + EXT_KEY(ZVKT); + } #undef EXT_KEY } =20 --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC9BC4167B for ; Tue, 14 Nov 2023 14:13:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233418AbjKNOOA (ORCPT ); Tue, 14 Nov 2023 09:14:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233437AbjKNONx (ORCPT ); Tue, 14 Nov 2023 09:13:53 -0500 Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 752CAD52 for ; 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:41 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Date: Tue, 14 Nov 2023 09:12:44 -0500 Message-ID: <20231114141256.126749-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a3803b22cf4f..e845e461b6e1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -338,5 +338,101 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: zvbb + description: + The standard Zvbb extension for vectored basic bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvbc + description: + The standard Zvbc extension for vectored carryless multiplicat= ion + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkb + description: + The standard Zvkb extension for vector cryptography bit-manipu= lation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkg + description: + The standard Zvkg extension for vector GCM/GMAC instructions, = as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvkn + description: + The standard Zvkn extension for NIST algorithm suite instructi= ons, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvknc + description: + The standard Zvknc extension for NIST algorithm suite with car= ryless + multiply instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkned + description: + The standard Zvkned extension for Vector AES block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkng + description: + The standard Zvkng extension for NIST algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknha + description: | + The standard Zvknha extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 only) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvknhb + description: | + The standard Zvknhb extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 and SHA-512) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvks + description: + The standard Zvks extension for ShangMi algorithm suite + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksc + description: + The standard Zvksc extension for ShangMi algorithm suite with + carryless multiplication instructions, as ratified in commit 5= 6ed795 + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksed + description: | + The standard Zvksed extension for ShangMi suite: SM4 block cip= her + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksg + description: + The standard Zvksg extension for ShangMi algorithm suite with = GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkt + description: + The standard Zvkt extension for vector data-independent execut= ion + latency, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + additionalProperties: true ... --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40881C4332F for ; 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:43 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Date: Tue, 14 Nov 2023 09:12:45 -0500 Message-ID: <20231114141256.126749-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zfh[min] ISA extensions[1]. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 477254668d82..6a6ee93a3c9a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -78,6 +78,8 @@ #define RISCV_ISA_EXT_ZVKSED 63 #define RISCV_ISA_EXT_ZVKSH 64 #define RISCV_ISA_EXT_ZVKT 65 +#define RISCV_ISA_EXT_ZFH 66 +#define RISCV_ISA_EXT_ZFHMIN 67 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c4d0f16c29b9..7182cf278b1c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -258,6 +258,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), + __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 734CCC4167D for ; Tue, 14 Nov 2023 14:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233391AbjKNOOK (ORCPT ); Tue, 14 Nov 2023 09:14:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233469AbjKNONz (ORCPT ); Tue, 14 Nov 2023 09:13:55 -0500 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 642801706 for ; Tue, 14 Nov 2023 06:13:46 -0800 (PST) Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3b40bf434a3so639868b6e.1 for ; Tue, 14 Nov 2023 06:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971225; x=1700576025; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iEYEszCfp8f2sFaBAy4eKryQQU+hp7kZpXxy9sdi/dQ=; b=EjOWHAfp2Aag2afsEE/uNUpIVu7TqXlONdoGrToLFxc9zjKOx3D3aE88OnEZ2fFpjx B2dgdMiJq1aqAg6RXWsQJVJjXByzmHDNM1ulWT6+3PPnfnbUuBgVZFyQAuFfMdERBRpH WY6rJxm2v5Cji12S7jjw9ny4v592FHg+94PR667cc2YJVJoX6AM1VrEdlR+r1L1sNbDF NsP6rVu+CmKjws2QyUOFxkldQ09L+6qLrWmt2Dw1eQhvxkXQqSzF6N3RaSu617sph3kN FtcIiI/LzdplztCq/cTdZYo4jDoG696ifD1MQiY2PQ162VfgRQYuYytjbJlMUdbRHey+ riqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971225; x=1700576025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iEYEszCfp8f2sFaBAy4eKryQQU+hp7kZpXxy9sdi/dQ=; b=HkzrNI3TuH8PW+R8vLKDRu9h9bCbTnjsMJjpzpbCKAJgpN81Cx6b3xtgYYxiACJOr6 qlQAKWMkjntkaNdz/vNEyXMPMiLBfWVz2JioqcNRp+0P7S5e6/E3lYsOazeE7fDnfihu GmgOW4ykw6U0qc8UWNP9vuXwLCH81Fqw5z6nJNzg6nQRYYO2eM3vXGvQe2HhuZ83K6Dw Bl6SiytebrD7IZLXkGgTTiRKcy/m+QyUf/Gm8yPwS+m2nO1YcWQFFw/2k8GjL4XYhVYy +3kiqtr8vcKqVcGNKT6eRuo9KW8qDl9JN1etz0eZfJyrg0FAXtaIGiAfH7hYBn04a7Ay 89Cw== X-Gm-Message-State: AOJu0YyPKLRa3zoAUuAKYZuEjz11MRGQU7D7E6Y5GMsUHGD7fntWWDHz 3EHRpxFDtt02aWw1DLcvcHXpjGr3o4Giok8JmzJjyg== X-Google-Smtp-Source: AGHT+IGZDXgDf7Oyda/sT4+/a1oolhnnDFVdqByG3o5P/z09X4SwtY07cxiO09aQ9LMMrzbgtkqFGw== X-Received: by 2002:a54:4688:0:b0:3b2:ef4e:23e1 with SMTP id k8-20020a544688000000b003b2ef4e23e1mr2189020oic.1.1699971225384; Tue, 14 Nov 2023 06:13:45 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:44 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 10/20] riscv: hwprobe: export Zfh[min] ISA extensions Date: Tue, 14 Nov 2023 09:12:46 -0500 Message-ID: <20231114141256.126749-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfh[min] ISA extensions[1] through hwprobe only if FPU support is available. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index a08fcd899b6d..397d53195f49 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -140,6 +140,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is sup= ported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 89628a76ca04..2d960777ea43 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -50,6 +50,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSED (1 << 24) #define RISCV_HWPROBE_EXT_ZVKSH (1 << 25) #define RISCV_HWPROBE_EXT_ZVKT (1 << 26) +#define RISCV_HWPROBE_EXT_ZFH (1 << 27) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 9bbcd7334d96..d776c6c39fcd 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -186,6 +186,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, EXT_KEY(ZVKSH); EXT_KEY(ZVKT); } + + if (has_fpu()) { + EXT_KEY(ZFH); + EXT_KEY(ZFHMIN); + } #undef EXT_KEY } =20 --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F10FFC072A2 for ; Tue, 14 Nov 2023 14:14:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233568AbjKNOOU (ORCPT ); Tue, 14 Nov 2023 09:14:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233493AbjKNON7 (ORCPT ); Tue, 14 Nov 2023 09:13:59 -0500 Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39DAC172C for ; Tue, 14 Nov 2023 06:13:48 -0800 (PST) Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-779d0c05959so55569185a.1 for ; Tue, 14 Nov 2023 06:13:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971227; x=1700576027; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ak2BDRIk2vDqh5U51tE5B/vdW3wNdZF+MHtrJJi5jsA=; b=0hFu8LzJy4hfD8J0+/tBOtIJWT5aqMsYZcKW/3+b6BQITqhDlT5jNNlp6tzHZTdNy2 z7yomNmeGGQ/zquiK3QP0anWgCfJk/j1h6Ph4VDWgY/LqP7c1eJC3lTsRYLEAA/7e12t CibcLX8kBkTwtlwm4PMTzFPHDn2MxoxgGH+NFD8pF7zaicLbFF8q+wQwBXUv6j8H/+7C gA9Zibe2/72IkwYgqdAfNY2+5B/Ul9AAuubDus+xAF8+oPVWfUquuR7QRCZSX97A+iNB gRlPLKqPLp5DQEY3BTzCqngqs9GXWCvYVpanJGZQHTTUF5GBoSRM6bcBo3iZy3ufYAcI 62LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971227; x=1700576027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ak2BDRIk2vDqh5U51tE5B/vdW3wNdZF+MHtrJJi5jsA=; b=JuWd/o4bl3Sps+Wdl3HVIr1C4G3GCEqzR6OqMnbKFNC/wiRtcrbYJXo3XfzwnYoAiX iuKbFpg7dQHtj78IKRI6e7QlcamYqd8BT3cm3lTQaViW7yPLbX6Fyh6BtyFru/pMygCS MdlBCSh5rWwdphPfuyntZbwe4hzywIRrB2LsVALQJ2bMnhd3Fo8UBZ6Aq7q7ZfiyIDdJ xMYniIYXcZgGLAYe+AjGS6AEmq2BHJMH14oLZVnw7JxCjy+FjvaDOvAO1VH+j0XqUHlR QabpkdfJ7h/0cwK5I88A7+2ZRW8zcaEEpZbp4jo3R9vnE3uIJU3fojPbDAjoHbjTZOv3 Qdgg== X-Gm-Message-State: AOJu0YzSSTBPJvFOjngbpw6/V9KXrnL15dEXEiEIu6DvZqmIabQmeKKR /9BUdgd0WSGsezGgHEJBgzEhhg== X-Google-Smtp-Source: AGHT+IF2D+KBDRTw0WcUH3F5f9hiu2zqM89jEEHbneHS+TDtFN6UAjynE2yo55wJNn9K3IiKYTPHXQ== X-Received: by 2002:a05:620a:31a8:b0:77a:69a1:b6a3 with SMTP id bi40-20020a05620a31a800b0077a69a1b6a3mr3097295qkb.1.1699971226657; Tue, 14 Nov 2023 06:13:46 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:46 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Date: Tue, 14 Nov 2023 09:12:47 -0500 Message-ID: <20231114141256.126749-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description of Zfh[min] ISA extensions[1]. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index e845e461b6e1..f3c99e69619b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -214,6 +214,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("U= pdate + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support f= or + 16-bit half-precision binary floating-point instructions, as r= atified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as rati= fied --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D329EC4167D for ; Tue, 14 Nov 2023 14:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233436AbjKNOOY (ORCPT ); Tue, 14 Nov 2023 09:14:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233509AbjKNOOE (ORCPT ); Tue, 14 Nov 2023 09:14:04 -0500 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6035F173D for ; Tue, 14 Nov 2023 06:13:49 -0800 (PST) Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-77891670417so55611885a.0 for ; Tue, 14 Nov 2023 06:13:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971228; x=1700576028; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CepaQtX/sdwhUbmZetc41QOoUE9LfFVWHL973vxJ7UQ=; b=r4MsV3pUqHlMtM0U0eUSS3RLRXCYYDZHJuKDGcFHaMw6qb5hkSX+dJIGYacyH1qhAh Lhg7kY7fmo2pXm0T5kuc+p5Nxy3ncX8VwjG/UvNOBQ44lNkFhMfEjZis345yXfojY5zC eUDDdqtxnfQruhys9TYHAikQs8daWK7PeU5lNEVjFlg8bu6ZzyDlu6PSwYgA1D/fJ9Dj Fn7GFezFPsTYE6UPDwzBUUw4XNnF2MHpYMpJLxkJPy2bXEpZvEvu2TgA/2eaSGOaRoH7 E/rWYgYy4e9Yru13n67l7byzQaopoX2AJUO0jRSYhtw4cAKkNCo8Wk/Og09Kh6pEh9AC pk/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971228; x=1700576028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CepaQtX/sdwhUbmZetc41QOoUE9LfFVWHL973vxJ7UQ=; b=c6RnmOgzSAcdrJx5LWsjeaoObPd0W4siN9cKBWFPCTd6MybMscBn087O6HUXITvI4P MyIFWfzHW8hJ6NKEJTiaIFMqLyaFYJBn1qDgNxwNGrhJmFlWFLdqZHzlw8CGzyc1blbQ FWtVAFWtmne0f96ARwCyU5wJCPtoA+ydGkvScEyENgpxqRVOB7RUGydq5KYCu8xn0QpE gLKujv0DsMefaDHiO1R8ISPzDs+9/6WJx+LwtYRK9Vj7SfphxGYpEKqKHbDsvhOs1sfW vhLQDnLXigOhedYeo0RkHCeON/1RV6yR3bujEjhJ9Tf8+LV+KMQvQN7iFHZU4FvIkhoW oR6A== X-Gm-Message-State: AOJu0YzUPj4XBofAL7gnRUWcLcMPfP651MvVM+K+XcDiSexC7xyClCDA cNBJpaECWPLBB1YuUlKi9Fts4g== X-Google-Smtp-Source: AGHT+IF7WevyrXd//n4lH0ZEXB0TDnFlHM3i203ryiy76OKa7Bcf589Sc/lKHJHt3RYWXfpjbdBHtw== X-Received: by 2002:a05:620a:31a8:b0:77a:69a1:b6a3 with SMTP id bi40-20020a05620a31a800b0077a69a1b6a3mr3097387qkb.1.1699971228077; Tue, 14 Nov 2023 06:13:48 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:47 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 12/20] riscv: add ISA extension parsing for Zihintntl Date: Tue, 14 Nov 2023 09:12:48 -0500 Message-ID: <20231114141256.126749-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zihintntl ISA extension[1] that was ratified in commit 0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6a6ee93a3c9a..97d106fa0f54 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,7 @@ #define RISCV_ISA_EXT_ZVKT 65 #define RISCV_ISA_EXT_ZFH 66 #define RISCV_ISA_EXT_ZFHMIN 67 +#define RISCV_ISA_EXT_ZIHINTNTL 68 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7182cf278b1c..e73ee4cfd84a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -256,6 +256,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 391ADC4167D for ; Tue, 14 Nov 2023 14:14:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233500AbjKNOOp (ORCPT ); Tue, 14 Nov 2023 09:14:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233430AbjKNOOS (ORCPT ); Tue, 14 Nov 2023 09:14:18 -0500 Received: from mail-oi1-x233.google.com (mail-oi1-x233.google.com [IPv6:2607:f8b0:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD08719B3 for ; Tue, 14 Nov 2023 06:13:54 -0800 (PST) Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3b2d9a9c824so804155b6e.0 for ; Tue, 14 Nov 2023 06:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971234; x=1700576034; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mh7tTRDZwkplFE7US+z6W8VzyVO8RyK0Ie0Y8NEIF5E=; b=PEZcIcbGBEo0y6V1wpVuwE5qZ//Zpnf17+QQWQXOKXcMgcplY7Kjgy3qPrQjcRoyYd T0VTgtpfcdB4sortegvMrdXTWeCJn26Boaf92ufEHtigFmu0RPdmEMZdDwp+0J25IAxQ w05qf/8a7wIgilGEkQNqd5TPU/E720kcCIjLKOfY6eSDRdtE2f2kGI4sgBhkyf6KORB1 NR5zzPObND2Cq4hc/UpxTCQqdWiHdQLvFNeXinpiLUVo+uR5KQzkcE6xqsh6hObzVHgE bJR5zZQXWU49fxe2Coa7uo9SZFwd54YkP/LZ+wQugBMkdIssWRK/GrD6NogoxMyrtl8a idUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971234; x=1700576034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mh7tTRDZwkplFE7US+z6W8VzyVO8RyK0Ie0Y8NEIF5E=; b=Gl6kqD9vsluIirJ0atPlp4sCwu4S+LnzFX824RpJDKPXG4sK1IB4+o8z0BVkVRY3Lp 11cW2qw5mru58a6W/iWVKETRHMJU0TOJsxsKDL3CfkRXhaa+pJwioFAZyYxolLos1vZQ ECxadWYMss+xRx0IUc/6mnd86e9gpqdW/3oIGkoVnn6o80J5/yaVwHrKLr61ZgVNDCTE 53ErT8XBAOMoDw723qqcOIFtTIIIKWKTPCsl6W0+oWAhSOvnviw44xsmSBf36/ZLj2uH h1PC22MynyeIIxDzIGWj6uXdBT95UanUl6N8dAKluzj5N8Z7No+C5LjCO050OJNTqS/g BHNQ== X-Gm-Message-State: AOJu0YxDbdW6akV4aXY12IDTRswWp+LiO1oCpQ+rU4KnTbKc6+cIfmHf InZssIgiKvXlugTD527nCZWiaA== X-Google-Smtp-Source: AGHT+IGkxt/nZ/twmuaXiKz9xS1+QSbiEolPjI0eAyguNp2BxYnPRpCdPEUVfljS4ZnrA7PBhdlykg== X-Received: by 2002:a05:6808:1a2a:b0:3b5:65c2:fef4 with SMTP id bk42-20020a0568081a2a00b003b565c2fef4mr2571171oib.5.1699971229027; Tue, 14 Nov 2023 06:13:49 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:48 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 13/20] riscv: hwprobe: export Zhintntl ISA extension Date: Tue, 14 Nov 2023 09:12:49 -0500 Message-ID: <20231114141256.126749-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zihintntl extension[1] through hwprobe. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 397d53195f49..aa8ebeeddfe6 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -146,6 +146,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 2d960777ea43..d72c69ea0740 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -52,6 +52,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKT (1 << 26) #define RISCV_HWPROBE_EXT_ZFH (1 << 27) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) +#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index d776c6c39fcd..a46e4f6821dd 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -173,6 +173,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSED); EXT_KEY(ZKSH); EXT_KEY(ZKT); + EXT_KEY(ZIHINTNTL); =20 if (has_vector()) { EXT_KEY(ZVBB); --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D1DC4332F for ; Tue, 14 Nov 2023 14:14:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233528AbjKNOOa (ORCPT ); Tue, 14 Nov 2023 09:14:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233463AbjKNOOI (ORCPT ); Tue, 14 Nov 2023 09:14:08 -0500 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 733191702 for ; Tue, 14 Nov 2023 06:13:51 -0800 (PST) Received: by mail-qk1-x72c.google.com with SMTP id af79cd13be357-779f81223ebso9062685a.1 for ; Tue, 14 Nov 2023 06:13:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971230; x=1700576030; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B5yYxDd+9V9reUvZ2DQpNcNkqEc4BDOdQVkeYdlaxbs=; b=MY51Ax27YlLXH6RdZ9FPltzrsU4CjToYoLGJjczl4zoY/6moxzyB2DhkuP9AeAy3tp b1o8+5toiyB6L2eS0HOBANnRsIl+zMEXS0gs/+PAdv1nBdMIQdMjQeLS4pFqCqMf+DGp l5bkevWMQ9Q50K91C2z9O4KInkCP8O3FwnLufOsaqGoLSAsMsiPMHEE1jJssRBW1D7j2 eQuNtwCM6C1FaJiabShZ6jQw6i1kUvLmt/oLZZyBqCv0I/OWy2P2Wfz1ZFrf9LfK8EH+ oQ+cHJvxnA0Uc2tTZfdWkqUoxaq5y3wwkuWO6JeHoTBUWSaMqQremWO+jZzOLEYiDY50 FjOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971230; x=1700576030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B5yYxDd+9V9reUvZ2DQpNcNkqEc4BDOdQVkeYdlaxbs=; b=mByFM61rvaOQcw9KsaB4OWNr0mUXIb3DmRscpmlYn53VgMP8LlE+MwLY0q+CuLDt+B Ij2/0RzgSpHnBpLs1sBrEpW0Riuhe292dqbVDAt2gedy9jmJqNrVAUinnr2i14vtIqTr nXHl2Ued4t4bAr2xJNCcSP8moX5ON9lKf/r7h5akDwynH+G+dXM5O5eSWozEpMkJyg2H 8TstUPKIuOyfbFxTOUo0w+5Rjd/73owZ3IvZxGq5OXamvUo0+ckosLtd7cigUZaqqB5e lOs4vcDNEJL0dG/V1MCj3NbCu2tLVM8duKfdNM5u8Gd4afKgpSjmb7sG9socYHT4Axkq SRXA== X-Gm-Message-State: AOJu0Yz3RsYEb2Cp78QlAjiPLO9NccrZlf+cBkdRtXIBs0Iz6R0jAnK/ Q86V6RPVcHmnQxvVdGxsu+SKtzUbBvKbj83QSLXjvQ== X-Google-Smtp-Source: AGHT+IFptxx2Guy0DQYVfc+KvtPdCaNrZCEFFfEn6l2iik1hGkFfOg6ndZjt6u/AUGRVAMsa0MAFtQ== X-Received: by 2002:a05:620a:370d:b0:774:17d6:31dc with SMTP id de13-20020a05620a370d00b0077417d631dcmr2397859qkb.4.1699971230375; Tue, 14 Nov 2023 06:13:50 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:49 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Date: Tue, 14 Nov 2023 09:12:50 -0500 Message-ID: <20231114141256.126749-15-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zihintntl ISA extension[1]. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index f3c99e69619b..f953c49be90d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -339,6 +339,12 @@ properties: The standard Zihintpause extension for pause hints, as ratifie= d in commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-ma= nual. =20 + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hin= ts, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + - const: zihpm description: The standard Zihpm extension for hardware performance counters= , as --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2129C4332F for ; Tue, 14 Nov 2023 14:14:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233414AbjKNOOm (ORCPT ); Tue, 14 Nov 2023 09:14:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233258AbjKNOOQ (ORCPT ); Tue, 14 Nov 2023 09:14:16 -0500 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C70919A3 for ; Tue, 14 Nov 2023 06:13:53 -0800 (PST) Received: by mail-qk1-x72e.google.com with SMTP id af79cd13be357-77891670417so55612985a.0 for ; Tue, 14 Nov 2023 06:13:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971232; x=1700576032; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kebr+ZAQxQeA9gxwXsENChkHynJvuQ8x6phPFJllrto=; b=VqDU5v+BES95H5PeKJaA4YrnF18y6tW7P9PqO+cRuxpKxMk9UB2ppbpX4Y683vlm3T UjyJinfL4HCs8Ifz4uICuKxNdRQPd2YR/Gky2neggpG9gAXT+sVKN7tnQ550MeA8mopH VXMePpJkCRnFg4oHrt4OeiDO3HZM+4oCWDSLBsfpQcz5cuJBHCci2RYXxe4lW679UvfW KVd9pEjGm1M0LD8H2FjGC6DUC1exfoC35HVQslmnDJx1UvIKrNpTj4XgRFHWqx2bIx9i Wg9HwPaMjEnEt7YdGsGL+z0+vF0BXszjCGQwVYWmZj6WBAH2RShD8WBGlVzWfDaFxGNG IzDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971232; x=1700576032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kebr+ZAQxQeA9gxwXsENChkHynJvuQ8x6phPFJllrto=; b=DF5lSxWQnmNBIi7DiG2UIy/tjsBB5DvWGr2mcOh1V37FaI1eK0HBTkpExEwwE7naDc nDfTSzuT1CTmWs9+H5+D6tT79qekcKNnyTYF7HKATdi92SSTL2TcvBejGdFHbUXAw+Lh 7fsmP0dY5VkeVXFQPoByHV7/IVy+o44nMDl8M1EOuc/Z4nWtuEewRuNNXPBDRLI9iRhf 7aZvR8Ipc0ce1LF/QtatIHjRbomosy63uldijM68N1d/vqC5WBQTqohJWU7faclXOsyt bSjDx70SfY86lXAXt0JAM0Pw97/XLo7qevX3pe9rlfiN0TP918TX4CmXmLD3HgB1aR95 bfAg== X-Gm-Message-State: AOJu0YwjdxrO3crPSx5wwHezHLo0kVKwU+wDQCPB1cpiLUbBb8287PD2 41/s38w5ABuI0uUanQkZvBP64w== X-Google-Smtp-Source: AGHT+IGUNDzsVyRn1cI8Qi+AL4zww1R/UAkdwGtV1FRdekOhhWQiL5gaf+3isCeURHwpf2kxBnYCXw== X-Received: by 2002:a05:620a:461f:b0:774:17d6:31f1 with SMTP id br31-20020a05620a461f00b0077417d631f1mr2492322qkb.4.1699971232036; Tue, 14 Nov 2023 06:13:52 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:50 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 15/20] riscv: add ISA extension parsing for Zvfh[min] Date: Tue, 14 Nov 2023 09:12:51 -0500 Message-ID: <20231114141256.126749-16-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zvfh[min] ISA extension[1] which were ratified in june 2023 around commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]") in riscv-v-spec[2]. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 97d106fa0f54..103d4f0aaf15 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZFH 66 #define RISCV_ISA_EXT_ZFHMIN 67 #define RISCV_ISA_EXT_ZIHINTNTL 68 +#define RISCV_ISA_EXT_ZVFH 69 +#define RISCV_ISA_EXT_ZVFHMIN 70 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e73ee4cfd84a..623a5fa48cf4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -280,6 +280,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), + __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69CD4C4332F for ; Tue, 14 Nov 2023 14:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233606AbjKNOOs (ORCPT ); Tue, 14 Nov 2023 09:14:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233490AbjKNOOS (ORCPT ); Tue, 14 Nov 2023 09:14:18 -0500 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D748C19AE for ; Tue, 14 Nov 2023 06:13:54 -0800 (PST) Received: by mail-qk1-x731.google.com with SMTP id af79cd13be357-778a25cad6dso14503685a.0 for ; Tue, 14 Nov 2023 06:13:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971233; x=1700576033; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mTkSM9bAUTwt3Wciw9Vfs7ckFoeuejbzVqs+azlN9Lg=; b=PRNAoTpuJ0hj9DjaSfnckoXrSem82++xC1+wfZJXtd3oWVQlPOgCp6VYjcCq/TALUP OyHOdOvqB2Wf+yjKRCbBuFDIhebSnDgtwJEG/ZvmIh8tVGB6T809Fby8bc871rY2HsP1 QXYlGB7h3GZX/ooZcYUAbkvn3BfU1768Y+SSbQEuvIlq0TOINkqdy1xRABzRgxYxY/9s 5lA9BBUE/ME+bmF9AR4aagARsUqYpH1nFM0lUNobt8Hd2F+/tSSAOs5wkn3LnbK1OF9d wS8GtwNKbcvKNn8UwkInUCzI8pYjugXp6kF+mheBlGFpDW+ow/6wh+buLNaRl6Exi35x n6rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971233; x=1700576033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mTkSM9bAUTwt3Wciw9Vfs7ckFoeuejbzVqs+azlN9Lg=; b=iLgrKpR+lJSySyZ9NPv0uQ6lUiPigogFk5acdBY3p3Rm8JTAwxR1hx/+F7xil3CP1x X0Pra9ntOLNMrhk6937qZhNhM0ecPiGdHhmxNxHNWzmhSUmQ+ZGjp55aYydq+DIEtBql YgrAkU1OX29elTdahM3QWc6n50EfCUxMLrJPjoXYJ1WmmWFI2hAXPaj0jH8OwK6zcJD7 GUUNI9duM20f5Q0zNKaGNcV4mMSlvOKwTOOk2afcAQfGPEaul1p7A+QOiZ9D5edj4N0f i6D98m9KdL7DnF3JDWm0H3dr01gkxdRQD8nIJGCeDbjNLfn8M+tsW2uzJnsUB9S0ZLuM PVhw== X-Gm-Message-State: AOJu0YwZzqINWNwVpYlTjJwGKDJwnYZ3s1bOv7xf317VcnqkqCN+SDd+ a4dCbQFMUd1MN4zU2xHsPtBXyA== X-Google-Smtp-Source: AGHT+IH10FrNz5wJfdEN4PWoaaLBM1zx/8nZEqjt+rAkZMedk134cZsiD1LAwi+cZemn3bnj/q1syg== X-Received: by 2002:a05:620a:d94:b0:775:82e2:dc19 with SMTP id q20-20020a05620a0d9400b0077582e2dc19mr2498746qkl.2.1699971233218; Tue, 14 Nov 2023 06:13:53 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:52 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Date: Tue, 14 Nov 2023 09:12:52 -0500 Message-ID: <20231114141256.126749-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zvfh[min] ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index aa8ebeeddfe6..896ecfbbe5f4 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -149,6 +149,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is support= ed as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index d72c69ea0740..fffc69d9f6ba 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -53,6 +53,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFH (1 << 27) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 30) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index a46e4f6821dd..e90537593f5f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -186,6 +186,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZVKSED); EXT_KEY(ZVKSH); EXT_KEY(ZVKT); + EXT_KEY(ZVFH); + EXT_KEY(ZVFHMIN); } =20 if (has_fpu()) { --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55687C4167B for ; Tue, 14 Nov 2023 14:14:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233614AbjKNOOu (ORCPT ); Tue, 14 Nov 2023 09:14:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233554AbjKNOOS (ORCPT ); Tue, 14 Nov 2023 09:14:18 -0500 Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3559B19BA for ; Tue, 14 Nov 2023 06:13:56 -0800 (PST) Received: by mail-qk1-x72f.google.com with SMTP id af79cd13be357-779f81223ebso9063485a.1 for ; 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([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:53 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Date: Tue, 14 Nov 2023 09:12:53 -0500 Message-ID: <20231114141256.126749-18-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zvfh[min] ISA extension[1]. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index f953c49be90d..b91d49b7c3a0 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -369,6 +369,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + - const: zvfh + description: + The standard Zvfh extension for vectored half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + + - const: zvfhmin + description: + The standard Zvfhmin extension for vectored minimal half-preci= sion + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + - const: zvkb description: The standard Zvkb extension for vector cryptography bit-manipu= lation --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 881FCC4332F for ; Tue, 14 Nov 2023 14:14:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233516AbjKNOO5 (ORCPT ); Tue, 14 Nov 2023 09:14:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233565AbjKNOOU (ORCPT ); Tue, 14 Nov 2023 09:14:20 -0500 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90A4D68 for ; Tue, 14 Nov 2023 06:13:57 -0800 (PST) Received: by mail-qk1-x72e.google.com with SMTP id af79cd13be357-77773d3246aso14496785a.1 for ; Tue, 14 Nov 2023 06:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971235; x=1700576035; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FhcCtOR2GZrdrPK8F2RJJNrJMtAQGPXOJeJBoGOeT7I=; b=HBsLFE+r07aglPpovHuOYS6UcCt5hTIo6KX0SVkBk8PYFWMxogNbsTW4tPzn/qUzbG hA7+ORL7dCyye1oqpkJcQLYGjfdUD0uxV4lv5Vizt1HkDqYH/rUJCb4yacwOcdpumFYW AHtjFEsruLOphHJSQRf2Nw1vBBt75SgkwfMUrX/a6hU7RtLWT4wIPGzbXFAoX4iR2Wee dxHTFx9mp6Mnr2EYsc8Vbg3frqWKaJ9Y7GC1Ad9bs+RpjwT30nu7K4RCxzcaUk8q7yVY g0QRb4/Eo8LrG71+o6B6Erk5hIWeYVAGkrzE0974YDTCIi8/Peg5HvXXl5c8akADe9X1 uUVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971235; x=1700576035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FhcCtOR2GZrdrPK8F2RJJNrJMtAQGPXOJeJBoGOeT7I=; b=sVrnI8vxHx1CmI0GqFDjbjZld+N3CsrEsQa9J0OF+AfZFG3wHaguDB0NPk5YUxgs+a m31sftJ8zWActxNL9F/C1jhILb/8QclGH3w259kYWEzsqgyb1DfC/53+8eDeSCgMYjNJ WYAE7M1SocS46a5WpXNy2MxxGcziuLeDcDDSf907p5YD8yqV/807jBv8NASBu8QB0Jny OYB+1PyaIMSGJ8l7IscTwXL8LJzHXN0KUh17hXBEaXXozboea2PefcZMz9K8UUGerBl+ o0JiGLrjqhVVbd4HwCtoesyjJfrbETzIOqKLMjhFap8Ch595pxzNvj+1xaoX0RVthCrB Y78A== X-Gm-Message-State: AOJu0YxUxI8AFdBejqjlx3n4aAgv2cMSyBB+ZmUFjlpQ7wChLgXGu6Ew IW5vAC5yf2u/tFfinsXTYWdQvw== X-Google-Smtp-Source: AGHT+IHw6SoyZ+QahmzQ/8JDfKi56le+NNxYvZ8O/S2hYgiLZdXnFM9RxTYP4C4LF3pIviuj3zDP+A== X-Received: by 2002:a05:620a:f12:b0:77b:d8aa:6755 with SMTP id v18-20020a05620a0f1200b0077bd8aa6755mr2516814qkl.3.1699971235353; Tue, 14 Nov 2023 06:13:55 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:54 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 18/20] riscv: add ISA extension parsing for Zfa Date: Tue, 14 Nov 2023 09:12:54 -0500 Message-ID: <20231114141256.126749-19-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zfa ISA extension [1] which were ratified in commit 056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 103d4f0aaf15..2438d4685da6 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -83,6 +83,7 @@ #define RISCV_ISA_EXT_ZIHINTNTL 68 #define RISCV_ISA_EXT_ZVFH 69 #define RISCV_ISA_EXT_ZVFHMIN 70 +#define RISCV_ISA_EXT_ZFA 71 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 623a5fa48cf4..dc0ab3e97cd2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FEB7C4332F for ; Tue, 14 Nov 2023 14:15:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233627AbjKNOPC (ORCPT ); Tue, 14 Nov 2023 09:15:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233526AbjKNOOZ (ORCPT ); Tue, 14 Nov 2023 09:14:25 -0500 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D8971BEF for ; Tue, 14 Nov 2023 06:13:58 -0800 (PST) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-77773d3246aso14497385a.1 for ; Tue, 14 Nov 2023 06:13:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971237; x=1700576037; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8oJqbvRhcnLQ4NxthWPQmg85qomzW1aIjvQdZvqQ+P8=; b=dnx4y6VFVZXXxHxrPOZEMg+iwKsctF0YCegxpcgZ/bb45IGDJdKj4Y8+McR3vD6lI5 y2T4cb1YbVszVikjWD42lwmNcxbHGVd6w9MD/TqmJvjdWRPwfGpWRniaRgFPXgXtpw0r CekBGC17nhNv8+evmB3Ke3NNJSyC2p1l7UO/tchmEyHmU1LTpo+GTvH2cKwnGsfW6N9I WK50pJpK80jGRpPiSQHMsNACQxFI5dgz76zrgd9AcA1AurxepWt6XLTl376nS4yju3Ti RWrDD7Ng5Y4Le361FOJ7lj3e0zdTnfSIfP8ilouMgdtmsUEvINxXqo6mDB+1iorQy/0F +szg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971237; x=1700576037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8oJqbvRhcnLQ4NxthWPQmg85qomzW1aIjvQdZvqQ+P8=; b=rFXqiNyGcZM+bZiqZWO/U8EIWMhrYwi1x+avh6BgCEFNNyvrwFgKO7UK7dP2B29Gr2 WYJA/ylBLjZwmHlDvxmSOGbwPjbsaEAgLsXeWRqDjLj2ZOdJbSwLz3J4f+d8qsvObzMZ xgbSHFcQv9js6iUG+vVSXfZIvWpN82zIMnKbbaTogNcXVZga6f9TpvGkc+ZIlzuWxN22 RT3NsAVSEA//lwjUQM+xQIRcK2OxA/wUqeAmatkCZ2nveT6CDIwgJQTaVvRJFLf5fNay XyCdG13DmgaJZKw6kD1WWMq8dLsvH+RNT8GBlzQfwCRuJ+GgTaBjr4dZ98SBUeK/fBT0 S95g== X-Gm-Message-State: AOJu0Yy7EokWv/Al6/kvCj2XZYXxqWu9h0opFxVrstTYmhuuVGyIQnlv WxvCO3CIkJ25ooHG4YkYBp7ing== X-Google-Smtp-Source: AGHT+IF9EjIfzzCxNwPyM1ga1yNOhI5yYokOjuEfqsXGtogg+vNsqW/HCxpZN6Ez5oZMRSmIbkGJGw== X-Received: by 2002:a05:620a:28d4:b0:773:a789:cd15 with SMTP id l20-20020a05620a28d400b00773a789cd15mr2090356qkp.6.1699971236775; Tue, 14 Nov 2023 06:13:56 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:56 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih Subject: [PATCH v4 19/20] riscv: hwprobe: export Zfa ISA extension Date: Tue, 14 Nov 2023 09:12:55 -0500 Message-ID: <20231114141256.126749-20-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfa ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 896ecfbbe5f4..41463b932268 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -157,6 +157,10 @@ The following keys are defined: defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c ("Remove draft warnings from Zvfh[min]"). =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as + defined in the RISC-V ISA manual starting from commit 056b6ff467c7 + ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index fffc69d9f6ba..91fbe1a7f2e2 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -55,6 +55,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) +#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index e90537593f5f..f0bd7b480b7f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -193,6 +193,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) { EXT_KEY(ZFH); EXT_KEY(ZFHMIN); + EXT_KEY(ZFA); } #undef EXT_KEY } --=20 2.42.0 From nobody Tue Dec 30 14:49:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FBDCC4332F for ; Tue, 14 Nov 2023 14:15:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233483AbjKNOPN (ORCPT ); Tue, 14 Nov 2023 09:15:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233444AbjKNOOj (ORCPT ); Tue, 14 Nov 2023 09:14:39 -0500 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12E831FD0 for ; Tue, 14 Nov 2023 06:14:00 -0800 (PST) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-77891670417so55614285a.0 for ; Tue, 14 Nov 2023 06:14:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699971238; x=1700576038; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rR6IoEmFXflq9Qi2M8/M8/Q1NwDbTzc9ULqQpExnZtc=; b=N/thXekKUOrWo0W1g0hZeBjK984McFlvDKnUJ93Fg8G3BU7BA6AIUwkYGUAmFm1W/c pZw+T6EVvJIIZiB8u9myTSLXJBGSJw+lsGbyCeIlFbeDS/vbeoEReROE9AWog3Tyo2TO NET3HmTC0cHI44r4kyrrPEQaSEhR5ldV2pKeY/KuPtg8THRluZTLIQHwpjRgufMxL442 e89inI/nfS+OuSmybuAEElEkpOTcX3xCECORk97WbBS3fzMI+Ck7opbLbKtL0Ga4iXZR vvLwhfOAQIndX5luSPMJ5xGPWEXoEs+k6F6P/E55EuZIopDNCJoYnNuZ6HfBadt0/S+2 Hblw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699971238; x=1700576038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rR6IoEmFXflq9Qi2M8/M8/Q1NwDbTzc9ULqQpExnZtc=; b=HWYzzEYiC4IBJuejaQGpZJFVmCnuZVZOHIzabZjQWJ5Irc9d6BKAK6fOrbDEZeDwgG FGUxXIlPHT2qbwFU6BFj1WNo9xkfoMNRLGsh5Dd1CpRFbmTajB3RW2ZFpPXS/awvk/Q8 x9t+BA7bI+gS8L0ST2WVzUAYg3Rlqk+daqsvJ69+InT31EivZNZcSRhNXjbiv5b9YBaz gYMiQwrUv5tWIdoosYrK6d1tuRgWHziLO3iBzCw43pw6J4YPLbq43y1GkGPsp9bYfj0X H+CSy43k4voWLHZlh+XfgL9/3401VDv1FUNjiBTjqdUd1+T4vobK7IfNrUxctuuQSU56 6MEw== X-Gm-Message-State: AOJu0YxflsbHrHfHeAmjP3Nfy9SMpIZD16rNmlBMnEciVI/WlfaCf10t 1Np/e9snZeWy/vOPB7wm6KY/1w== X-Google-Smtp-Source: AGHT+IGC6MfMYTQMl9dKfVeKwBQV9tnSgNOr1rIW41NsUM7O4nwiZO4ELAHWdrBbYXRRG7zqxSN9cw== X-Received: by 2002:a05:620a:461f:b0:774:17d6:31f1 with SMTP id br31-20020a05620a461f00b0077417d631f1mr2492695qkb.4.1699971238436; Tue, 14 Nov 2023 06:13:58 -0800 (PST) Received: from carbon-x1.. ([12.186.190.2]) by smtp.gmail.com with ESMTPSA id m2-20020a05620a220200b00777611164c5sm2701263qkh.106.2023.11.14.06.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 06:13:57 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Jerry Shih , Conor Dooley Subject: [PATCH v4 20/20] dt-bindings: riscv: add Zfa ISA extension description Date: Tue, 14 Nov 2023 09:12:56 -0500 Message-ID: <20231114141256.126749-21-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231114141256.126749-1-cleger@rivosinc.com> References: <20231114141256.126749-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for the Zfa ISA extension[1]. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index b91d49b7c3a0..3574a0b70be4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -214,6 +214,12 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfa + description: + The standard Zfa extension for additional floating point + instructions, as ratified in commit 056b6ff ("Zfa is ratified"= ) of + riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary --=20 2.42.0