From nobody Tue Dec 16 09:01:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00EE1C4167B for ; Tue, 14 Nov 2023 06:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232100AbjKNGRN (ORCPT ); Tue, 14 Nov 2023 01:17:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230140AbjKNGRL (ORCPT ); Tue, 14 Nov 2023 01:17:11 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 15440D43 for ; Mon, 13 Nov 2023 22:17:04 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2C36DA7; Mon, 13 Nov 2023 22:17:49 -0800 (PST) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5EB043F7B4; Mon, 13 Nov 2023 22:17:02 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Will Deacon , Mark Rutland , linux-kernel@vger.kernel.org, James Clark Subject: [PATCH V2 RESEND] drivers: perf: arm_pmuv3: Add new macro PMUV3_INIT_MAP_EVENT() Date: Tue, 14 Nov 2023 11:46:56 +0530 Message-Id: <20231114061656.337231-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This further compacts all remaining PMU init procedures requiring specific map_event functions via a new macro PMUV3_INIT_MAP_EVENT(). While here, it also changes generated init function names to match to those generated via the other macro PMUV3_INIT_SIMPLE(). This does not cause functional change. Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: James Clark Signed-off-by: Anshuman Khandual --- This applies on v6.7-rc1 Changes in V2: https://lore.kernel.org/all/20231020051543.2818951-1-anshuman.khandual@arm.= com/ - Updated the commit message - Rebased the patch after the following change https://lore.kernel.org/all/20231016025436.1368945-1-anshuman.khandual@ar= m.com/ Changes in V1: https://lore.kernel.org/all/20231009064714.186770-1-anshuman.khandual@arm.c= om/ drivers/perf/arm_pmuv3.c | 61 +++++++++++++--------------------------- 1 file changed, 20 insertions(+), 41 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 6ca7be05229c..c136a6529014 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1221,6 +1221,12 @@ static int name##_pmu_init(struct arm_pmu *cpu_pmu) = \ return armv8_pmu_init(cpu_pmu, #name, armv8_pmuv3_map_event); \ } =20 +#define PMUV3_INIT_MAP_EVENT(name, map_event) \ +static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ +{ \ + return armv8_pmu_init(cpu_pmu, #name, map_event); \ +} + PMUV3_INIT_SIMPLE(armv8_pmuv3) =20 PMUV3_INIT_SIMPLE(armv8_cortex_a34) @@ -1247,51 +1253,24 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) =20 -static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35", armv8_a53_map_event); -} - -static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53", armv8_a53_map_event); -} - -static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57", armv8_a57_map_event); -} - -static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72", armv8_a57_map_event); -} - -static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73", armv8_a73_map_event); -} - -static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder", armv8_thunder_map_= event); -} - -static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) -{ - return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan", armv8_vulcan_map_even= t); -} +PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event) +PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event) +PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event) +PMUV3_INIT_MAP_EVENT(armv8_cortex_a72, armv8_a57_map_event) +PMUV3_INIT_MAP_EVENT(armv8_cortex_a73, armv8_a73_map_event) +PMUV3_INIT_MAP_EVENT(armv8_cavium_thunder, armv8_thunder_map_event) +PMUV3_INIT_MAP_EVENT(armv8_brcm_vulcan, armv8_vulcan_map_event) =20 static const struct of_device_id armv8_pmu_of_device_ids[] =3D { {.compatible =3D "arm,armv8-pmuv3", .data =3D armv8_pmuv3_pmu_init}, {.compatible =3D "arm,cortex-a34-pmu", .data =3D armv8_cortex_a34_pmu_ini= t}, - {.compatible =3D "arm,cortex-a35-pmu", .data =3D armv8_a35_pmu_init}, - {.compatible =3D "arm,cortex-a53-pmu", .data =3D armv8_a53_pmu_init}, + {.compatible =3D "arm,cortex-a35-pmu", .data =3D armv8_cortex_a35_pmu_ini= t}, + {.compatible =3D "arm,cortex-a53-pmu", .data =3D armv8_cortex_a53_pmu_ini= t}, {.compatible =3D "arm,cortex-a55-pmu", .data =3D armv8_cortex_a55_pmu_ini= t}, - {.compatible =3D "arm,cortex-a57-pmu", .data =3D armv8_a57_pmu_init}, + {.compatible =3D "arm,cortex-a57-pmu", .data =3D armv8_cortex_a57_pmu_ini= t}, {.compatible =3D "arm,cortex-a65-pmu", .data =3D armv8_cortex_a65_pmu_ini= t}, - {.compatible =3D "arm,cortex-a72-pmu", .data =3D armv8_a72_pmu_init}, - {.compatible =3D "arm,cortex-a73-pmu", .data =3D armv8_a73_pmu_init}, + {.compatible =3D "arm,cortex-a72-pmu", .data =3D armv8_cortex_a72_pmu_ini= t}, + {.compatible =3D "arm,cortex-a73-pmu", .data =3D armv8_cortex_a73_pmu_ini= t}, {.compatible =3D "arm,cortex-a75-pmu", .data =3D armv8_cortex_a75_pmu_ini= t}, {.compatible =3D "arm,cortex-a76-pmu", .data =3D armv8_cortex_a76_pmu_ini= t}, {.compatible =3D "arm,cortex-a77-pmu", .data =3D armv8_cortex_a77_pmu_ini= t}, @@ -1309,8 +1288,8 @@ static const struct of_device_id armv8_pmu_of_device_= ids[] =3D { {.compatible =3D "arm,neoverse-n1-pmu", .data =3D armv8_neoverse_n1_pmu_i= nit}, {.compatible =3D "arm,neoverse-n2-pmu", .data =3D armv9_neoverse_n2_pmu_i= nit}, {.compatible =3D "arm,neoverse-v1-pmu", .data =3D armv8_neoverse_v1_pmu_i= nit}, - {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_thunder_pmu_init}, - {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_vulcan_pmu_init}, + {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_cavium_thunder_pmu= _init}, + {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_brcm_vulcan_pmu_init}, {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_nvidia_carmel_pmu_i= nit}, {.compatible =3D "nvidia,denver-pmu", .data =3D armv8_nvidia_denver_pmu_i= nit}, {}, --=20 2.25.1