From nobody Wed Dec 31 00:58:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B62F9C4332F for ; Tue, 14 Nov 2023 04:04:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231971AbjKNEEp (ORCPT ); Mon, 13 Nov 2023 23:04:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbjKNEEb (ORCPT ); Mon, 13 Nov 2023 23:04:31 -0500 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C590D45 for ; Mon, 13 Nov 2023 20:04:26 -0800 (PST) Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4STt2x0HVNzvQh4; Tue, 14 Nov 2023 12:04:09 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 14 Nov 2023 12:04:24 +0800 From: Yicong Yang To: , , , CC: , , , , , , , Subject: [PATCH v3 3/4] arm64: topology: Support SMT control on ACPI based system Date: Tue, 14 Nov 2023 12:01:09 +0800 Message-ID: <20231114040110.54590-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231114040110.54590-1-yangyicong@huawei.com> References: <20231114040110.54590-1-yangyicong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yicong Yang For ACPI we'll build the topology from PPTT and we cannot directly get the SMT number of each core. Instead using a temporary xarray to record the SMT number of each core when building the topology and we can know the largest SMT number in the system. Then we can notify the arch_topology for supporting SMT control. Signed-off-by: Yicong Yang --- arch/arm64/kernel/topology.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 817d788cd866..0dc360c32ec8 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -43,11 +44,16 @@ static bool __init acpi_cpu_is_threaded(int cpu) */ int __init parse_acpi_topology(void) { + int thread_num, max_smt_thread_num =3D 1; + struct xarray core_threads; int cpu, topology_id; + void *entry; =20 if (acpi_disabled) return 0; =20 + xa_init(&core_threads); + for_each_possible_cpu(cpu) { topology_id =3D find_acpi_cpu_topology(cpu, 0); if (topology_id < 0) @@ -57,6 +63,20 @@ int __init parse_acpi_topology(void) cpu_topology[cpu].thread_id =3D topology_id; topology_id =3D find_acpi_cpu_topology(cpu, 1); cpu_topology[cpu].core_id =3D topology_id; + + entry =3D xa_load(&core_threads, topology_id); + if (!entry) { + xa_store(&core_threads, topology_id, + xa_mk_value(1), GFP_KERNEL); + } else { + thread_num =3D xa_to_value(entry); + thread_num++; + xa_store(&core_threads, topology_id, + xa_mk_value(thread_num), GFP_KERNEL); + + if (thread_num > max_smt_thread_num) + max_smt_thread_num =3D thread_num; + } } else { cpu_topology[cpu].thread_id =3D -1; cpu_topology[cpu].core_id =3D topology_id; @@ -67,6 +87,9 @@ int __init parse_acpi_topology(void) cpu_topology[cpu].package_id =3D topology_id; } =20 + topology_smt_set_num_threads(max_smt_thread_num); + + xa_destroy(&core_threads); return 0; } #endif --=20 2.24.0