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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add MIPI ISP & CSI PHY clock ids to G12A clock bindings header Signed-off-by: Neil Armstrong Acked-by: Conor Dooley Reviewed-by: Daniel Scally Tested-by: Daniel Scally --- include/dt-bindings/clock/g12a-clkc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/cl= ock/g12a-clkc.h index 636d713f95ff..fd09819da2ec 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -281,5 +281,11 @@ #define CLKID_MIPI_DSI_PXCLK 270 #define CLKID_CTS_ENCL 271 #define CLKID_CTS_ENCL_SEL 272 +#define CLKID_MIPI_ISP_DIV 273 +#define CLKID_MIPI_ISP_SEL 274 +#define CLKID_MIPI_ISP 275 +#define CLKID_MIPI_ISP_GATE 276 +#define CLKID_MIPI_ISP_CSI_PHY0 277 +#define CLKID_MIPI_ISP_CSI_PHY1 278 =20 #endif /* __G12A_CLKC_H */ --=20 2.34.1 From nobody Tue Dec 30 15:15:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 392B8C4332F for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the MIPI ISP gate, divider and mux used to feed the MIPI CSI ISP (Image Signal Processor) IP on the Amlogic G12B SoC. Signed-off-by: Neil Armstrong Reviewed-by: Daniel Scally Tested-by: Daniel Scally --- drivers/clk/meson/g12a.c | 66 ++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/meson/g12a.h | 1 + 2 files changed, 67 insertions(+) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index f373a8d48b1d..a8312f29d1cc 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3722,6 +3722,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk =3D { }, }; =20 +/* MIPI ISP Clocks */ + +static const struct clk_parent_data g12b_mipi_isp_parent_data[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &g12a_gp0_pll.hw }, + { .hw =3D &g12a_hifi_pll.hw }, + { .hw =3D &g12a_fclk_div2p5.hw }, + { .hw =3D &g12a_fclk_div3.hw }, + { .hw =3D &g12a_fclk_div4.hw }, + { .hw =3D &g12a_fclk_div5.hw }, + { .hw =3D &g12a_fclk_div7.hw }, +}; + +static struct clk_regmap g12b_mipi_isp_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_ISP_CLK_CNTL, + .mask =3D 7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mipi_isp_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D g12b_mipi_isp_parent_data, + .num_parents =3D ARRAY_SIZE(g12b_mipi_isp_parent_data), + }, +}; + +static struct clk_regmap g12b_mipi_isp_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D HHI_ISP_CLK_CNTL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "mipi_isp_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_mipi_isp_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12b_mipi_isp =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_ISP_CLK_CNTL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mipi_isp", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12b_mipi_isp_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + /* HDMI Clocks */ =20 static const struct clk_parent_data g12a_hdmi_parent_data[] =3D { @@ -4729,6 +4789,9 @@ static struct clk_hw *g12b_hw_clks[] =3D { [CLKID_MIPI_DSI_PXCLK_SEL] =3D &g12a_mipi_dsi_pxclk_sel.hw, [CLKID_MIPI_DSI_PXCLK_DIV] =3D &g12a_mipi_dsi_pxclk_div.hw, [CLKID_MIPI_DSI_PXCLK] =3D &g12a_mipi_dsi_pxclk.hw, + [CLKID_MIPI_ISP_SEL] =3D &g12b_mipi_isp_sel.hw, + [CLKID_MIPI_ISP_DIV] =3D &g12b_mipi_isp_div.hw, + [CLKID_MIPI_ISP] =3D &g12b_mipi_isp.hw, }; =20 static struct clk_hw *sm1_hw_clks[] =3D { @@ -5221,6 +5284,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = =3D { &g12a_mipi_dsi_pxclk_sel, &g12a_mipi_dsi_pxclk_div, &g12a_mipi_dsi_pxclk, + &g12b_mipi_isp_sel, + &g12b_mipi_isp_div, + &g12b_mipi_isp, }; =20 static const struct reg_sequence g12a_init_regs[] =3D { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index f11ee3c59849..27df99c4565a 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -70,6 +70,7 @@ #define HHI_MALI_CLK_CNTL 0x1b0 #define HHI_VPU_CLKC_CNTL 0x1b4 #define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_ISP_CLK_CNTL 0x1C0 #define HHI_NNA_CLK_CNTL 0x1C8 #define HHI_HDMI_CLK_CNTL 0x1CC #define HHI_VDEC_CLK_CNTL 0x1E0 --=20 2.34.1 From nobody Tue Dec 30 15:15:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4E4AC4167B for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the gates entires for the CSI ISP domain and CSI PHYs. Signed-off-by: Neil Armstrong Reviewed-by: Daniel Scally Tested-by: Daniel Scally --- drivers/clk/meson/g12a.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index a8312f29d1cc..b0bd37ae1a81 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4274,9 +4274,12 @@ static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, = 3); static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6); static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); +static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17); static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); +static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28); +static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29); static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); =20 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); @@ -4792,6 +4795,9 @@ static struct clk_hw *g12b_hw_clks[] =3D { [CLKID_MIPI_ISP_SEL] =3D &g12b_mipi_isp_sel.hw, [CLKID_MIPI_ISP_DIV] =3D &g12b_mipi_isp_div.hw, [CLKID_MIPI_ISP] =3D &g12b_mipi_isp.hw, + [CLKID_MIPI_ISP_GATE] =3D &g12b_mipi_isp_gate.hw, + [CLKID_MIPI_ISP_CSI_PHY0] =3D &g12b_csi_phy0.hw, + [CLKID_MIPI_ISP_CSI_PHY1] =3D &g12b_csi_phy1.hw, }; =20 static struct clk_hw *sm1_hw_clks[] =3D { @@ -5287,6 +5293,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = =3D { &g12b_mipi_isp_sel, &g12b_mipi_isp_div, &g12b_mipi_isp, + &g12b_mipi_isp_gate, + &g12b_csi_phy1, + &g12b_csi_phy0, }; =20 static const struct reg_sequence g12a_init_regs[] =3D { --=20 2.34.1