From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6ADEC4332F for ; Thu, 9 Nov 2023 10:25:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232829AbjKIKZ5 (ORCPT ); Thu, 9 Nov 2023 05:25:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231849AbjKIKZx (ORCPT ); Thu, 9 Nov 2023 05:25:53 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08D16D50 for ; Thu, 9 Nov 2023 02:25:51 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D92C7660748C; Thu, 9 Nov 2023 10:25:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525549; bh=VutiVek57G2+kwr524Jb2GlK/BYf3oFU6xsK3CmnGxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEf1VhxQm+/YrzXxu0eX2Vp/pHu8nyLBdUXrysuB7D05srtm483iHG5cBEXi9m0+W V9wKVd8g+jqhRoD2CfHjL9KEj712PUwqFtErrTOAccAbMdu5f1LHmb77ITJ5XGR1s4 w4qWhV/U02mblV0mYYqcgD+Q36FPULk5Eg4hVrcu1Ud4E9KUteIIn2O0Qd7+P4HiBm coHD52Egca4uqzE3cWey20IoxF6lXEgRrrHJ68zbVdLIpoAryvjy8oLVH4OiIey0pR cT7fSm/3xGfY+jWPv6bFAI0MLLZn+DhukSn7ytK9dWvpkNGR7Doz56bkQRcmdo0PZV Ft0tAZO5F8p9w== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 1/6] drm/panfrost: Perform hard reset to recover GPU if soft reset fails Date: Thu, 9 Nov 2023 11:25:38 +0100 Message-ID: <20231109102543.42971-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Even though soft reset should ideally never fail, during development of some power management features I managed to get some bits wrong: this resulted in GPU soft reset failures, where the GPU was never able to recover, not even after suspend/resume cycles, meaning that the only way to get functionality back was to reboot the machine. Perform a hard reset after a soft reset failure to be able to recover the GPU during runtime (so, without any machine reboot). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 13 ++++++++++--- drivers/gpu/drm/panfrost/panfrost_regs.h | 1 + 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panf= rost/panfrost_gpu.c index f0be7e19b13e..ae3f7d97bb47 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -60,14 +60,21 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfd= ev) =20 gpu_write(pfdev, GPU_INT_MASK, 0); gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); - gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); =20 + gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); =20 if (ret) { - dev_err(pfdev->dev, "gpu soft reset timed out\n"); - return ret; + dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); + + gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); + ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, + val & GPU_IRQ_RESET_COMPLETED, 100, 10000); + if (ret) { + dev_err(pfdev->dev, "gpu hard reset timed out\n"); + return ret; + } } =20 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/pan= frost/panfrost_regs.h index 55ec807550b3..c25743b05c55 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -44,6 +44,7 @@ GPU_IRQ_MULTIPLE_FAULT) #define GPU_CMD 0x30 #define GPU_CMD_SOFT_RESET 0x01 +#define GPU_CMD_HARD_RESET 0x02 #define GPU_CMD_PERFCNT_CLEAR 0x03 #define GPU_CMD_PERFCNT_SAMPLE 0x04 #define GPU_CMD_CYCLE_COUNT_START 0x05 --=20 2.42.0 From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 631C4C4332F for ; Thu, 9 Nov 2023 10:26:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233557AbjKIK0D (ORCPT ); Thu, 9 Nov 2023 05:26:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233110AbjKIKZy (ORCPT ); Thu, 9 Nov 2023 05:25:54 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23D6E211B for ; Thu, 9 Nov 2023 02:25:52 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 06ED86607498; Thu, 9 Nov 2023 10:25:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525550; bh=jhmRrLJp8PH/G9FAfR90YAI0hEC9baxhyFV4GjT06UY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TC3Ee+3kBEGYswGdMICLfNwD55LYTBEzx3QrQ79ZJac8J0ZTY9+wynVAUNrptV6fI mRXK7sRtgFV4Or1ReQGtXOJs7bdtF95l/t0ZgXsrxGQ2/IB35YqaPGUJZq9p+KJGUi T9Rbz3uP+3DwzOhMcusBlthxvnoLymyAwrO2dDAAAae8KA+bOq455C5uu7YBshWmFw TEy9bm2gyeGUUYmk8uQydmub5+epdiJsed0wUZe10QFoxSgmP0Cw+6aA8N4m9U+cfH 2rR6EOJYj8JCzFUv7NYw7fpypkC69gIxlGeZRzUOinAoNaR04QI2yPRRcizC+69Stw TbTs4YjpmBmVQ== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 2/6] drm/panfrost: Tighten polling for soft reset and power on Date: Thu, 9 Nov 2023 11:25:39 +0100 Message-ID: <20231109102543.42971-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In many cases, soft reset takes more than 1 microsecond, but definitely less than 10; moreover in the poweron flow, tilers, shaders and l2 will become ready (each) in less than 10 microseconds as well. Even in the cases (at least on my platforms, rarely) in which those take more than 10 microseconds, it's very unlikely to see both soft reset and poweron to take more than 70 microseconds. Shorten the polling delay to 10 microseconds to consistently reduce the runtime resume time of the GPU. As an indicative example, measurements taken on a MediaTek MT8195 SoC Average runtime resume time in nanoseconds before this commit: GDM, user selection up/down: 88435ns GDM, Text Entry (typing user/password): 91489ns GNOME Desktop, idling, GKRELLM running: 73200ns After this commit: GDM: user selection up/down: 26690ns GDM: Text Entry (typing user/password): 27917ns GNOME Desktop, idling, GKRELLM running: 25304ns Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panf= rost/panfrost_gpu.c index ae3f7d97bb47..69179bc9677d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -63,7 +63,7 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) =20 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, - val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); + val, val & GPU_IRQ_RESET_COMPLETED, 10, 10000); =20 if (ret) { dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); @@ -394,7 +394,7 @@ void panfrost_gpu_power_on(struct panfrost_device *pfde= v) gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, val, val =3D=3D (pfdev->features.l2_present & core_mask), - 100, 20000); + 10, 20000); if (ret) dev_err(pfdev->dev, "error powering up gpu L2"); =20 @@ -402,13 +402,13 @@ void panfrost_gpu_power_on(struct panfrost_device *pf= dev) pfdev->features.shader_present & core_mask); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, val, val =3D=3D (pfdev->features.shader_present & core_mask), - 100, 20000); + 10, 20000); if (ret) dev_err(pfdev->dev, "error powering up gpu shader"); =20 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO, - val, val =3D=3D pfdev->features.tiler_present, 100, 1000); + val, val =3D=3D pfdev->features.tiler_present, 10, 1000); if (ret) dev_err(pfdev->dev, "error powering up gpu tiler"); } --=20 2.42.0 From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9D3DC4167B for ; Thu, 9 Nov 2023 10:26:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233638AbjKIK0G (ORCPT ); Thu, 9 Nov 2023 05:26:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233286AbjKIKZz (ORCPT ); Thu, 9 Nov 2023 05:25:55 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33BE4258D for ; Thu, 9 Nov 2023 02:25:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 289C766074B0; Thu, 9 Nov 2023 10:25:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525552; bh=2GPFBJNW5GRbawHFbqCBL3Rkx8B9UBWyRsGfJmve0+U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UUd9lFROc6P2jd9yR9cBXg5Qok/3p+glg+eiU6FCVEERqbPtX9FhTSbS+U1tT0LB7 VaoUBkyDKRFo3IV3jCBe24hPg+geJ/rLWK6ZtS9nYSkirtiS1iHH1sMT3lYnIIsKRH pFocHO3HRi8vQUwGSo2dZ60g/CwVTs/2nPLB3Hzx2874rlg1TPwLwGJ7npYXqlSw3Z y8J8Dy7X+oZoMrFOso34RpmFAM9cmRxM4UmIaRcsSUCVXw/moA60N40hwbgaiQsDCX cYuFPX1wHUUyCtXTZIamvsmViWKlHjFD2T5WglwsT/hitW3Htd/ztJJmX4bR6j4EQQ KkdnmQQOcQ86g== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 3/6] drm/panfrost: Implement ability to turn on/off GPU clocks in suspend Date: Thu, 9 Nov 2023 11:25:40 +0100 Message-ID: <20231109102543.42971-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the GPU is being internally powered off for runtime suspend and turned back on for runtime resume through commands sent to it, but note that the GPU doesn't need to be clocked during the poweroff state, hence it is possible to save some power on selected platforms. Add suspend and resume handlers for full system sleep and then add a new panfrost_gpu_pm enumeration and a pm_features variable in the panfrost_compatible structure: BIT(GPU_PM_CLK_DIS) will be used to enable this power saving technique only on SoCs that are able to safely use it. Note that this was implemented only for the system sleep case and not for runtime PM because testing on one of my MediaTek platforms showed issues when turning on and off clocks aggressively (in PM runtime) resulting in a full system lockup. Doing this only for full system sleep never showed issues during my testing by suspending and resuming the system continuously for more than 100 cycles. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_device.c | 61 ++++++++++++++++++++-- drivers/gpu/drm/panfrost/panfrost_device.h | 11 ++++ 2 files changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index 28f7046e1b1a..b4ddbc3b8069 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -403,7 +403,7 @@ void panfrost_device_reset(struct panfrost_device *pfde= v) panfrost_job_enable_interrupts(pfdev); } =20 -static int panfrost_device_resume(struct device *dev) +static int panfrost_device_runtime_resume(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); =20 @@ -413,7 +413,7 @@ static int panfrost_device_resume(struct device *dev) return 0; } =20 -static int panfrost_device_suspend(struct device *dev) +static int panfrost_device_runtime_suspend(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); =20 @@ -426,5 +426,58 @@ static int panfrost_device_suspend(struct device *dev) return 0; } =20 -EXPORT_GPL_RUNTIME_DEV_PM_OPS(panfrost_pm_ops, panfrost_device_suspend, - panfrost_device_resume, NULL); +static int panfrost_device_resume(struct device *dev) +{ + struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { + ret =3D clk_enable(pfdev->clock); + if (ret) + return ret; + + if (pfdev->bus_clock) { + ret =3D clk_enable(pfdev->bus_clock); + if (ret) + goto err_bus_clk; + } + } + + ret =3D pm_runtime_force_resume(dev); + if (ret) + goto err_resume; + + return 0; + +err_resume: + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS) && pfdev->bus_clock) + clk_disable(pfdev->bus_clock); +err_bus_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) + clk_disable(pfdev->clock); + return ret; +} + +static int panfrost_device_suspend(struct device *dev) +{ + struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_suspend(dev); + if (ret) + return ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { + if (pfdev->bus_clock) + clk_disable(pfdev->bus_clock); + + clk_disable(pfdev->clock); + } + + return 0; +} + +EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) =3D { + RUNTIME_PM_OPS(panfrost_device_runtime_suspend, panfrost_device_runtime_r= esume, NULL) + SYSTEM_SLEEP_PM_OPS(panfrost_device_suspend, panfrost_device_resume) +}; diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index 1ef38f60d5dc..d7f179eb8ea3 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -25,6 +25,14 @@ struct panfrost_perfcnt; #define NUM_JOB_SLOTS 3 #define MAX_PM_DOMAINS 5 =20 +/** + * enum panfrost_gpu_pm - Supported kernel power management features + * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend + */ +enum panfrost_gpu_pm { + GPU_PM_CLK_DIS, +}; + struct panfrost_features { u16 id; u16 revision; @@ -75,6 +83,9 @@ struct panfrost_compatible { =20 /* Vendor implementation quirks callback */ void (*vendor_quirk)(struct panfrost_device *pfdev); + + /* Allowed PM features */ + u8 pm_features; }; =20 struct panfrost_device { --=20 2.42.0 From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FD31C4332F for ; Thu, 9 Nov 2023 10:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233707AbjKIK0K (ORCPT ); Thu, 9 Nov 2023 05:26:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233210AbjKIKZ4 (ORCPT ); Thu, 9 Nov 2023 05:25:56 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9642584 for ; Thu, 9 Nov 2023 02:25:54 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4B54066074EC; Thu, 9 Nov 2023 10:25:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525553; bh=+OvqC6w/3PiRYdnTouSPUEJ19DjJes4x/Q2ujq7R7iE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JaiIz2gRqt8ainxfYGjGEtOQE0pVPgwpbjv6MsV2anAxI5Rt4Zu0N6cGfbHchcSVc h8+z7R89Qbjm/ZL1Kyw5Y/lzrabF6l6HsTUlKBGMvI3GyNnPmhuHVmADCCiuN+XD5/ /kxIyv7qZp5lgKu+nukXWdDCPvN9cxNLFVqsCfJIA9GtudGSBu16mFrmnPjB8wCoA6 NJWoROMNUXGnAME2QUWUVqrgtnBDyUlDQkfke6ncNylc832ZdiXe2sgfLzB/pnz9fA 98VXlGmvs6yhR6jT/toDac+N2QRLXcUrbYzgichJvy+QvdBSmpUlCyyMi1mXCHE/41 F9cNV4gzhapXQ== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 4/6] drm/panfrost: Set clocks on/off during system sleep on MediaTek SoCs Date: Thu, 9 Nov 2023 11:25:41 +0100 Message-ID: <20231109102543.42971-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the MediaTek SoCs supported by Panfrost can switch the clocks off and on during system sleep to save some power without any user experience penalty. Measurements taken on multiple MediaTek SoCs (MT8183/8186/8192/8195) show that adding this will not prolong the time that is required to resume the system in any meaningful way. As an example, for MT8195 - a "before" with only runtime PM operations (so, without turning on/off GPU clocks), and an "after" executing both the system sleep .resume() handler and .runtime_resume() (so the time refers to T_Resume + T_Runtime_Resume): Average Panfrost-only system sleep resume time, before: ~28000ns Average Panfrost-only system sleep resume time, after: ~33500ns Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 7cabf4e3d1f2..82f3c5fe9c58 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -734,6 +734,7 @@ static const struct panfrost_compatible mediatek_mt8183= _b_data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; @@ -742,6 +743,7 @@ static const struct panfrost_compatible mediatek_mt8186= _data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names =3D mediatek_mt8186_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; @@ -752,6 +754,7 @@ static const struct panfrost_compatible mediatek_mt8192= _data =3D { .supply_names =3D mediatek_mt8192_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names =3D mediatek_mt8192_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.42.0 From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27397C4332F for ; Thu, 9 Nov 2023 10:26:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233210AbjKIK0O (ORCPT ); Thu, 9 Nov 2023 05:26:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233395AbjKIKZ6 (ORCPT ); Thu, 9 Nov 2023 05:25:58 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860BE2D6A for ; Thu, 9 Nov 2023 02:25:55 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6B60E6607691; Thu, 9 Nov 2023 10:25:53 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525554; bh=mDPKNF83uvk33KrukPYl2Hf3G8HMp0A70irMrDutJLM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kqsJ6nVoRmEFtUhcnVFDAjprHsWTYSDkz4ZXgM6GLZv3eMK70VxWuCQshbrnZYB2X bFPG+HuoXHQJraSZV26yrDXBHO+J3ANGvYawbFDqEwKxW/wAkOPZEbBx4vNs5vHLfu Pq9IgeN89QL9Vow0QkgqF5rMZOnIIfJmclvlVSvGJLJfLtOoZdWVzaYEyzOGXFjEQ/ nk0BhqGKD7dux/fTnvhHOFSHBcVMpquJ9OUHFFix/MhGk2zkNKP6GnEapX1lG3lHu0 iJPrQDzGtCh9MHPTU6RQxbpoNI6GFbWmdlR+rhwzbpOs+rLjnTTMx4JtxPi95mnLW8 +9ZzLvLKCVXLQ== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 5/6] drm/panfrost: Implement ability to turn on/off regulators in suspend Date: Thu, 9 Nov 2023 11:25:42 +0100 Message-ID: <20231109102543.42971-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some platforms/SoCs can power off the GPU entirely by completely cutting off power, greatly enhancing battery time during system suspend: add a new pm_feature GPU_PM_VREG_OFF to allow turning off the GPU regulators during full suspend only on selected platforms. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_device.c | 19 ++++++++++++++++++- drivers/gpu/drm/panfrost/panfrost_device.h | 2 ++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index b4ddbc3b8069..c90ad5ee34e7 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -431,10 +431,21 @@ static int panfrost_device_resume(struct device *dev) struct panfrost_device *pfdev =3D dev_get_drvdata(dev); int ret; =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) { + unsigned long freq =3D pfdev->pfdevfreq.fast_rate; + struct dev_pm_opp *opp; + + opp =3D dev_pm_opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + dev_pm_opp_set_opp(dev, opp); + dev_pm_opp_put(opp); + } + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { ret =3D clk_enable(pfdev->clock); if (ret) - return ret; + goto err_clk; =20 if (pfdev->bus_clock) { ret =3D clk_enable(pfdev->bus_clock); @@ -455,6 +466,9 @@ static int panfrost_device_resume(struct device *dev) err_bus_clk: if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) clk_disable(pfdev->clock); +err_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) + dev_pm_opp_set_opp(dev, NULL); return ret; } =20 @@ -474,6 +488,9 @@ static int panfrost_device_suspend(struct device *dev) clk_disable(pfdev->clock); } =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) + dev_pm_opp_set_opp(dev, NULL); + return 0; } =20 diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index d7f179eb8ea3..0fc558db6bfd 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -28,9 +28,11 @@ struct panfrost_perfcnt; /** * enum panfrost_gpu_pm - Supported kernel power management features * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend + * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend */ enum panfrost_gpu_pm { GPU_PM_CLK_DIS, + GPU_PM_VREG_OFF, }; =20 struct panfrost_features { --=20 2.42.0 From nobody Wed Dec 17 03:47:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2694C4332F for ; Thu, 9 Nov 2023 10:26:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233717AbjKIK0R (ORCPT ); Thu, 9 Nov 2023 05:26:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233428AbjKIKZ7 (ORCPT ); Thu, 9 Nov 2023 05:25:59 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A603E2D74 for ; Thu, 9 Nov 2023 02:25:56 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8EB7C66074E4; Thu, 9 Nov 2023 10:25:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699525555; bh=d3zTQouwLyyEFIHsf9/xe8EYttNAC0DeHeu3XBTyvRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aUivKZHLULvsoef0DZLygMttrY4nsxgo8J7XjuMylkjtqxw5YnXSUE8Xng6rKVIUb cxRZIQLXgK67Q/k3POFNVzA76JKqpGRHW7AOFY260xkWlD545MtobUcYlVv5It6hQf n0Rs0Pyf7QoBuN0V5REeHNcornoT4Cu9Om3lKS83PnMDfDqWUPH+iLwh1d6fIZnK+9 W44vmN3jKNUjm5tW2ZNgi59J8bAhG8OCLEG8zX0KqCnlJk+qBawVYuGZnsB8pp8HuV nDLOFSni7YSGhM/hGBNSvl4IJ7JklNSfKCG45npSRZLI5wB6nQ5NDpsC7eYJkUoWa6 qCkq3nHqvrAwA== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v3 6/6] drm/panfrost: Set regulators on/off during system sleep on MediaTek SoCs Date: Thu, 9 Nov 2023 11:25:43 +0100 Message-ID: <20231109102543.42971-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> References: <20231109102543.42971-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the MediaTek SoCs supported by Panfrost can completely cut power to the GPU during full system sleep without any user-noticeable delay in the resume operation, as shown by measurements taken on multiple MediaTek SoCs (MT8183/86/92/95). As an example, for MT8195 - a "before" with only runtime PM operations (so, without turning on/off regulators), and an "after" executing both the system sleep .resume() handler and .runtime_resume() (so the time refers to T_Resume + T_Runtime_Resume): Average Panfrost-only system sleep resume time, before: ~33500ns Average Panfrost-only system sleep resume time, after: ~336200ns Keep in mind that this additional ~308200 nanoseconds delay happens only in resume from a full system suspend, and not in runtime PM operations, hence it is acceptable. Measurements were also taken on MT8186, showing a delay of ~312000 ns. Testing of this happened on all of the aforementioned MediaTek SoCs, but: MT8183 got tested only by KernelCI with <=3D10 suspend/resume cycles MT8186, MT8192, MT8195 were tested manually with over 100 suspend/resume cycles with GNOME DE (Mutter + Wayland). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_drv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 82f3c5fe9c58..f63382d9ab04 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -734,7 +734,7 @@ static const struct panfrost_compatible mediatek_mt8183= _b_data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; @@ -743,7 +743,7 @@ static const struct panfrost_compatible mediatek_mt8186= _data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names =3D mediatek_mt8186_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; @@ -754,7 +754,7 @@ static const struct panfrost_compatible mediatek_mt8192= _data =3D { .supply_names =3D mediatek_mt8192_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names =3D mediatek_mt8192_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.42.0