From nobody Wed Dec 31 01:11:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14666C4167B for ; Thu, 9 Nov 2023 05:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbjKIFuf (ORCPT ); Thu, 9 Nov 2023 00:50:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbjKIFub (ORCPT ); Thu, 9 Nov 2023 00:50:31 -0500 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F171195 for ; Wed, 8 Nov 2023 21:50:28 -0800 (PST) Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A95Aln4013504; Thu, 9 Nov 2023 05:50:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=pQhQg4apXhsXXZZDAj4vFHJNWV4fH6SB8zFy8oQ+Hm4=; b=M2l8iWosE9NHHvK8p5Ns4EdLhwd0cjILt7UFMpAJ//hhvF51ZmL8zGCTyWvAwqg5/EOg 3zJv34qtkPp10f4rpB+c4WabZZn/wng2tYBLAcTsqsv89uq2qxoE2Abz/mbtlgkBA7AK Az7VRd2D0/26vBznm5orjWLoKlb7mA6mjkdkQlECJSlM0oxijjCXya4KdpXEqtFl8otR J0PqGub62L0nmeHSih+PVjrJP/VqhHbv/KNkWovzAJ7hFUB6XcOpbL3Nr2veLTHUPIfr hAxG+1KVdDlo9TXA2KUKWSIUvSkuTnmf/XyQR1FeadmR2Qau9K6zgL2GRJTuJ1WgM+YX XA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8s201f0v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:02 +0000 Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3A95mgLx020288; Thu, 9 Nov 2023 05:50:02 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8s201f00-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:02 +0000 Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3A94rlc2000726; Thu, 9 Nov 2023 05:50:01 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3u7w231ttv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:01 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3A95nxcm45810180 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Nov 2023 05:49:59 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C86620043; Thu, 9 Nov 2023 05:49:59 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 161A920040; Thu, 9 Nov 2023 05:49:57 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.109.198.19]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Nov 2023 05:49:56 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linuxppc-dev , Srikar Dronamraju , Josh Poimboeuf , linux-kernel@vger.kernel.org, Mark Rutland , "Paul E. McKenney" , Peter Zijlstra , Rohan McLure , Valentin Schneider , Vincent Guittot , "ndesaulniers@google.com" Subject: [PATCH v4 1/5] powerpc/smp: Enable Asym packing for cores on shared processor Date: Thu, 9 Nov 2023 11:19:29 +0530 Message-ID: <20231109054938.26589-2-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> References: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: vtM3-coGDw4fG6ceF_CwiN4LweawGrYV X-Proofpoint-ORIG-GUID: b-SMEp_SUD0NIqtTBUv4XDdOsy5d8c6T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_04,2023-11-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If there are shared processor LPARs, underlying Hypervisor can have more virtual cores to handle than actual physical cores. Starting with Power 9, a big core (aka SMT8 core) has 2 nearly independent thread groups. On a shared processors LPARs, it helps to pack threads to lesser number of cores so that the overall system performance and utilization improves. PowerVM schedules at a big core level. Hence packing to fewer cores helps. For example: Lets says there are two 8-core Shared LPARs that are actually sharing a 8 Core shared physical pool, each running 8 threads each. Then Consolidating 8 threads to 4 cores on each LPAR would help them to perform better. This is because each of the LPAR will get 100% time to run applications and there will no switching required by the Hypervisor. To achieve this, enable SD_ASYM_PACKING flag at CACHE, MC and DIE level when the system is running in shared processor mode and has big cores. Signed-off-by: Srikar Dronamraju --- Changelog: v3 -> v4: - Dont use splpar_asym_pack with SMT - Conflict resolution due to rebase (DIE changed to PKG) v2 -> v3: - Handle comments from Michael Ellerman. - Rework using existing cpu_has_features static key v1->v2: Using Jump label instead of a variable. arch/powerpc/kernel/smp.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index ab691c89d787..69a3262024f1 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -993,16 +993,20 @@ static bool shared_caches; /* cpumask of CPUs with asymmetric SMT dependency */ static int powerpc_smt_flags(void) { - int flags =3D SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; + if (!cpu_has_feature(CPU_FTR_ASYM_SMT)) + return SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; =20 - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { - printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); - flags |=3D SD_ASYM_PACKING; - } - return flags; + return SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES | SD_ASYM_PACKING; } #endif =20 +/* + * On shared processor LPARs scheduled on a big core (which has two or more + * independent thread groups per core), prefer lower numbered CPUs, so + * that workload consolidates to lesser number of cores. + */ +static __ro_after_init DEFINE_STATIC_KEY_FALSE(splpar_asym_pack); + /* * P9 has a slightly odd architecture where pairs of cores share an L2 cac= he. * This topology makes it *much* cheaper to migrate tasks between adjacent= cores @@ -1011,9 +1015,20 @@ static int powerpc_smt_flags(void) */ static int powerpc_shared_cache_flags(void) { + if (static_branch_unlikely(&splpar_asym_pack)) + return SD_SHARE_PKG_RESOURCES | SD_ASYM_PACKING; + return SD_SHARE_PKG_RESOURCES; } =20 +static int powerpc_shared_proc_flags(void) +{ + if (static_branch_unlikely(&splpar_asym_pack)) + return SD_ASYM_PACKING; + + return 0; +} + /* * We can't just pass cpu_l2_cache_mask() directly because * returns a non-const pointer and the compiler barfs on that. @@ -1050,8 +1065,8 @@ static struct sched_domain_topology_level powerpc_top= ology[] =3D { { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, #endif { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, - { cpu_mc_mask, SD_INIT_NAME(MC) }, - { cpu_cpu_mask, SD_INIT_NAME(PKG) }, + { cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC) }, + { cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(PKG) }, { NULL, }, }; =20 @@ -1686,7 +1701,13 @@ static void __init fixup_topology(void) { int i; =20 + if (is_shared_processor() && has_big_cores) + static_branch_enable(&splpar_asym_pack); + #ifdef CONFIG_SCHED_SMT + if (cpu_has_feature(CPU_FTR_ASYM_SMT)) + pr_info_once("Enabling Asymmetric SMT scheduling\n"); + if (has_big_cores) { pr_info("Big cores detected but using small core scheduling\n"); powerpc_topology[smt_idx].mask =3D smallcore_smt_mask; --=20 2.31.1 From nobody Wed Dec 31 01:11:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EF3BC4332F for ; Thu, 9 Nov 2023 05:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230451AbjKIFud (ORCPT ); Thu, 9 Nov 2023 00:50:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229697AbjKIFub (ORCPT ); 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Thu, 9 Nov 2023 05:50:03 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1E8F22004B; Thu, 9 Nov 2023 05:50:03 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B25BB20040; Thu, 9 Nov 2023 05:50:00 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.109.198.19]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Nov 2023 05:50:00 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linuxppc-dev , Srikar Dronamraju , Josh Poimboeuf , linux-kernel@vger.kernel.org, Mark Rutland , "Paul E. McKenney" , Peter Zijlstra , Rohan McLure , Valentin Schneider , Vincent Guittot , "ndesaulniers@google.com" Subject: [PATCH v4 2/5] powerpc/smp: Disable MC domain for shared processor Date: Thu, 9 Nov 2023 11:19:30 +0530 Message-ID: <20231109054938.26589-3-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> References: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: d__swH62mFofZ5W_nx6tsbQ9U4diNO5m X-Proofpoint-ORIG-GUID: IAxiS1Dffz73V5XPc8YLGawJW0p5s6vC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_04,2023-11-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like L2-cache info, coregroup information which is used to determine MC sched domains is only present on dedicated LPARs. i.e PowerVM doesn't export coregroup information for shared processor LPARs. Hence disable creating MC domains on shared LPAR Systems. Signed-off-by: Srikar Dronamraju --- arch/powerpc/kernel/smp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 69a3262024f1..1dae4e9ba42d 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -1052,6 +1052,10 @@ static struct cpumask *cpu_coregroup_mask(int cpu) =20 static bool has_coregroup_support(void) { + /* Coregroup identification not available on shared systems */ + if (is_shared_processor()) + return 0; + return coregroup_enabled; } =20 --=20 2.31.1 From nobody Wed Dec 31 01:11:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27D58C4332F for ; Thu, 9 Nov 2023 05:50:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232676AbjKIFun (ORCPT ); Thu, 9 Nov 2023 00:50:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232498AbjKIFud (ORCPT ); Thu, 9 Nov 2023 00:50:33 -0500 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1C91BD7 for ; Wed, 8 Nov 2023 21:50:31 -0800 (PST) Received: from pps.filterd (m0360072.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A95lce2015558; Thu, 9 Nov 2023 05:50:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=N7am5QLVzzx8O8JCxpQgP7g2QAN9Pmg/pFTC6I0PJF0=; b=G0lnM0cibPWcIIeJEyNB3HIBk4cZ1pSqqa0yRy+mD/ajPSKGT7aoVZUmgMbKIjg3r5MZ UU8BRIazKDjBYBos3+rD1UgC/n8s2yTymInUeN8MIC2su8aGtI5ef0PKym4S7mjF31lQ Fado+/gsoH/m6eyDQFTMrZTrZQhQ+EKggkz/XK3SkVtSnitnoywkal9qfbaUdlWDBa2L NvBryncYGu5AvLAMc4IUYRhtXdf11QdfS+lprexpMej5Zu3PDGCDIV8Ty67ne1eNXfx9 jIMSQOGfxO4m+YiCUyf6r1/T+Y1g81VTz1Eb60dDZx6yM3AIC+Q/V3LJFADiXOwmkWi+ 3w== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8s201f77-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:10 +0000 Received: from m0360072.ppops.net (m0360072.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3A95nFnt021854; Thu, 9 Nov 2023 05:50:10 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8s201f6n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:09 +0000 Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3A94rlc5000726; Thu, 9 Nov 2023 05:50:09 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3u7w231tub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:09 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3A95o6xg29229758 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Nov 2023 05:50:06 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BB8C220040; Thu, 9 Nov 2023 05:50:06 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 652DC20043; Thu, 9 Nov 2023 05:50:04 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.109.198.19]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Nov 2023 05:50:04 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linuxppc-dev , Srikar Dronamraju , Josh Poimboeuf , linux-kernel@vger.kernel.org, Mark Rutland , "Paul E. McKenney" , Peter Zijlstra , Rohan McLure , Valentin Schneider , Vincent Guittot , "ndesaulniers@google.com" Subject: [PATCH v4 3/5] powerpc/smp: Add __ro_after_init attribute Date: Thu, 9 Nov 2023 11:19:31 +0530 Message-ID: <20231109054938.26589-4-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> References: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PSDQxOS8L3g2JqApkrUVbOG1x477vcUC X-Proofpoint-ORIG-GUID: ni8jdxWrzvgFhFjKjWh9iEw0rR7Ho9aR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_04,2023-11-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are some variables that are only updated at boot time. So add __ro_after_init attribute to such variables Signed-off-by: Srikar Dronamraju --- Changelog: v2 -> v3: Use __ro_after_init instead of __read_mostly Suggested by : Peter Zijlstra and Michael Ellerman arch/powerpc/kernel/smp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 1dae4e9ba42d..65a6f988374a 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -77,10 +77,10 @@ static DEFINE_PER_CPU(int, cpu_state) =3D { 0 }; #endif =20 struct task_struct *secondary_current; -bool has_big_cores; -bool coregroup_enabled; -bool thread_group_shares_l2; -bool thread_group_shares_l3; +bool has_big_cores __ro_after_init; +bool coregroup_enabled __ro_after_init; +bool thread_group_shares_l2 __ro_after_init; +bool thread_group_shares_l3 __ro_after_init; =20 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map); @@ -987,7 +987,7 @@ static int __init init_thread_group_cache_map(int cpu, = int cache_property) return 0; } =20 -static bool shared_caches; +static bool shared_caches __ro_after_init; =20 #ifdef CONFIG_SCHED_SMT /* cpumask of CPUs with asymmetric SMT dependency */ --=20 2.31.1 From nobody Wed Dec 31 01:11:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 890F9C4332F for ; Thu, 9 Nov 2023 05:51:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232532AbjKIFvE (ORCPT ); Thu, 9 Nov 2023 00:51:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232663AbjKIFun (ORCPT ); Thu, 9 Nov 2023 00:50:43 -0500 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17C12270F for ; Wed, 8 Nov 2023 21:50:39 -0800 (PST) Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A95lEqZ008994; Thu, 9 Nov 2023 05:50:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=/trf2Da4xtquXOm8DBIOlSBbypTnsuoaPWrvAXo/nw8=; b=SDox2sA03byawHRN2j3REaFqCzMiJwAKXy5r1c7IfKSWG1W7gAlRpKhsPe9gfZdFUemw gz8/PCSBJ26jVGyu/q0l6jf1pR8XkokbXm1bwfqSlFyrY0j3x9agYcK+vWXZcnXs840e 69qc543KAeEmXnMQKzpTdMAYoCK/8HjB66NC8ua7pwf5dIIkVYW+IqccavcyMO9KIVS4 XQOJjO7vMljlGnWLuH6V3Gh4PFZlvYaB+DER1K6uA5gREIeoTn64JwUL/fxVjxvCr5Am WYg7Bagp47ks87omW2U8dgwhEyco/L8ZyTH8JO79iS4Mb1URHEJnI6mVMGLWZkMapzrx ww== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8sk6g3pm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:14 +0000 Received: from m0356517.ppops.net (m0356517.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3A95m1XB011657; Thu, 9 Nov 2023 05:50:14 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8sk6g3nu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:14 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3A9577MK004129; Thu, 9 Nov 2023 05:50:13 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3u7w211txn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:13 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3A95oAel40632996 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Nov 2023 05:50:11 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 661CF20043; Thu, 9 Nov 2023 05:50:10 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07F2A20040; Thu, 9 Nov 2023 05:50:08 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.109.198.19]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Nov 2023 05:50:07 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linuxppc-dev , Srikar Dronamraju , Josh Poimboeuf , linux-kernel@vger.kernel.org, Mark Rutland , "Paul E. McKenney" , Peter Zijlstra , Rohan McLure , Valentin Schneider , Vincent Guittot , "ndesaulniers@google.com" Subject: [PATCH v4 4/5] powerpc/smp: Avoid asym packing within thread_group of a core Date: Thu, 9 Nov 2023 11:19:32 +0530 Message-ID: <20231109054938.26589-5-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> References: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 9AEMWltEu3BCvNHZwRw30v3U0tXEgM5r X-Proofpoint-GUID: hvnR1axlJCR2VI7drAolcRWmhWo6A2CJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_04,2023-11-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 impostorscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PowerVM Hypervisor will schedule at a core granularity. However each core can have more than one thread_groups. For better utilization in case of a shared processor, its preferable for the scheduler to pack to the lowest core. However there is no benefit of moving a thread between two thread groups of the same core. Signed-off-by: Srikar Dronamraju --- arch/powerpc/kernel/smp.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 65a6f988374a..a84931c37246 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -1763,6 +1763,19 @@ void __init smp_cpus_done(unsigned int max_cpus) set_sched_topology(powerpc_topology); } =20 +/* + * For asym packing, by default lower numbered CPU has higher priority. + * On shared processors, pack to lower numbered core. However avoid moving + * between thread_groups within the same core. + */ +int arch_asym_cpu_priority(int cpu) +{ + if (static_branch_unlikely(&splpar_asym_pack)) + return -cpu / threads_per_core; + + return -cpu; +} + #ifdef CONFIG_HOTPLUG_CPU int __cpu_disable(void) { --=20 2.31.1 From nobody Wed Dec 31 01:11:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 936F2C4332F for ; Thu, 9 Nov 2023 05:50:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232803AbjKIFuy (ORCPT ); Thu, 9 Nov 2023 00:50:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232658AbjKIFum (ORCPT ); Thu, 9 Nov 2023 00:50:42 -0500 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 170542590 for ; Wed, 8 Nov 2023 21:50:39 -0800 (PST) Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A95lIfN009122; Thu, 9 Nov 2023 05:50:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=0fF3Up0tvVC7FwVj/u5EG0pFt2dXz/KpTcdk+vueGz8=; b=cY4eZ3sWu1dLgMV1W8Il4oNVbmcH7/4UIlBVCG4fNMPgkMNpF+mck+iaOfdBqKiOZtOU s6gF1hteGu/7MQZ5aIgK52DPc+JqV23Y2BpxO7E6lpgHW3Q3tvXYuvWMj5gxcZGfjb9v LJAjQWmSzHSnB6cw6k2ZTT/QK0yliBGxEQKQX8OIZ/OVD2FwRWz40aBLxmYNqkmB7zQl h/tfGRU2l5L/SwvGk7DlFW0wmTNbrwziqgyvuE0lOo5mFQHg/d6jGLRjK78ubTGvNBdl eLAlLUDVFVBCMoLvEcAia/w0IwHGVODuQ3CeU5o7NleWZo5+pam8tCAiUTblWNutTZkP bw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8sk6g3s7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:18 +0000 Received: from m0356517.ppops.net (m0356517.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3A95n63M015669; Thu, 9 Nov 2023 05:50:17 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3u8sk6g3r1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:17 +0000 Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3A951ue3000675; Thu, 9 Nov 2023 05:50:16 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3u7w231tw0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 05:50:16 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3A95oEJI51249464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Nov 2023 05:50:14 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1E8DD20043; Thu, 9 Nov 2023 05:50:14 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BDD4420040; Thu, 9 Nov 2023 05:50:11 +0000 (GMT) Received: from sapthagiri.in.ibm.com (unknown [9.109.198.19]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Nov 2023 05:50:11 +0000 (GMT) From: Srikar Dronamraju To: Michael Ellerman , Nicholas Piggin , Christophe Leroy Cc: linuxppc-dev , Srikar Dronamraju , Josh Poimboeuf , linux-kernel@vger.kernel.org, Mark Rutland , "Paul E. McKenney" , Peter Zijlstra , Rohan McLure , Valentin Schneider , Vincent Guittot , "ndesaulniers@google.com" Subject: [PATCH v4 5/5] powerpc/smp: Dynamically build Powerpc topology Date: Thu, 9 Nov 2023 11:19:33 +0530 Message-ID: <20231109054938.26589-6-srikar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> References: <20231109054938.26589-1-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: LSpB3Rpm9-YZ9TM0Ml6nODh5cjw5hnkn X-Proofpoint-GUID: irbLnf1ZnOzrwVdp3G4s0XQHNTHLcr-I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-09_04,2023-11-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 impostorscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311090045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently there are four Powerpc specific sched topologies. These are all statically defined. However not all these topologies are used by all Powerpc systems. To avoid unnecessary degenerations by the scheduler, masks and flags are compared. However if the sched topologies are build dynamically then the code is simpler and there are greater chances of avoiding degenerations. Note: Even X86 builds its sched topologies dynamically and proposed changes are very similar to the way X86 is building its topologies. Signed-off-by: Srikar Dronamraju --- Changelog: v3 -> v4: - Conflict resolution due to rebase (DIE changed to PKG) arch/powerpc/kernel/smp.c | 78 ++++++++++++++------------------------- 1 file changed, 28 insertions(+), 50 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index a84931c37246..6631659cfb38 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -93,15 +93,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); EXPORT_PER_CPU_SYMBOL(cpu_core_map); EXPORT_SYMBOL_GPL(has_big_cores); =20 -enum { -#ifdef CONFIG_SCHED_SMT - smt_idx, -#endif - cache_idx, - mc_idx, - die_idx, -}; - #define MAX_THREAD_LIST_SIZE 8 #define THREAD_GROUP_SHARE_L1 1 #define THREAD_GROUP_SHARE_L2_L3 2 @@ -1064,16 +1055,6 @@ static const struct cpumask *cpu_mc_mask(int cpu) return cpu_coregroup_mask(cpu); } =20 -static struct sched_domain_topology_level powerpc_topology[] =3D { -#ifdef CONFIG_SCHED_SMT - { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, -#endif - { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, - { cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC) }, - { cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(PKG) }, - { NULL, }, -}; - static int __init init_big_cores(void) { int cpu; @@ -1701,9 +1682,11 @@ void start_secondary(void *unused) BUG(); } =20 -static void __init fixup_topology(void) +static struct sched_domain_topology_level powerpc_topology[6]; + +static void __init build_sched_topology(void) { - int i; + int i =3D 0; =20 if (is_shared_processor() && has_big_cores) static_branch_enable(&splpar_asym_pack); @@ -1714,36 +1697,33 @@ static void __init fixup_topology(void) =20 if (has_big_cores) { pr_info("Big cores detected but using small core scheduling\n"); - powerpc_topology[smt_idx].mask =3D smallcore_smt_mask; + powerpc_topology[i++] =3D (struct sched_domain_topology_level){ + smallcore_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) + }; + } else { + powerpc_topology[i++] =3D (struct sched_domain_topology_level){ + cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) + }; } #endif + if (shared_caches) { + powerpc_topology[i++] =3D (struct sched_domain_topology_level){ + shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) + }; + } + if (has_coregroup_support()) { + powerpc_topology[i++] =3D (struct sched_domain_topology_level){ + cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC) + }; + } + powerpc_topology[i++] =3D (struct sched_domain_topology_level){ + cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(PKG) + }; =20 - if (!has_coregroup_support()) - powerpc_topology[mc_idx].mask =3D powerpc_topology[cache_idx].mask; - - /* - * Try to consolidate topology levels here instead of - * allowing scheduler to degenerate. - * - Dont consolidate if masks are different. - * - Dont consolidate if sd_flags exists and are different. - */ - for (i =3D 1; i <=3D die_idx; i++) { - if (powerpc_topology[i].mask !=3D powerpc_topology[i - 1].mask) - continue; - - if (powerpc_topology[i].sd_flags && powerpc_topology[i - 1].sd_flags && - powerpc_topology[i].sd_flags !=3D powerpc_topology[i - 1].sd_flags) - continue; - - if (!powerpc_topology[i - 1].sd_flags) - powerpc_topology[i - 1].sd_flags =3D powerpc_topology[i].sd_flags; + /* There must be one trailing NULL entry left. */ + BUG_ON(i >=3D ARRAY_SIZE(powerpc_topology) - 1); =20 - powerpc_topology[i].mask =3D powerpc_topology[i + 1].mask; - powerpc_topology[i].sd_flags =3D powerpc_topology[i + 1].sd_flags; -#ifdef CONFIG_SCHED_DEBUG - powerpc_topology[i].name =3D powerpc_topology[i + 1].name; -#endif - } + set_sched_topology(powerpc_topology); } =20 void __init smp_cpus_done(unsigned int max_cpus) @@ -1758,9 +1738,7 @@ void __init smp_cpus_done(unsigned int max_cpus) smp_ops->bringup_done(); =20 dump_numa_cpu_topology(); - - fixup_topology(); - set_sched_topology(powerpc_topology); + build_sched_topology(); } =20 /* --=20 2.31.1