From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6133CC4332F for ; Fri, 10 Nov 2023 18:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345388AbjKJSVj (ORCPT ); Fri, 10 Nov 2023 13:21:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345645AbjKJSS7 (ORCPT ); Fri, 10 Nov 2023 13:18:59 -0500 Received: from mail-qv1-xf35.google.com (mail-qv1-xf35.google.com [IPv6:2607:f8b0:4864:20::f35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5D1C619B for ; Thu, 9 Nov 2023 22:19:07 -0800 (PST) Received: by mail-qv1-xf35.google.com with SMTP id 6a1803df08f44-66d87554434so11248296d6.2 for ; Thu, 09 Nov 2023 22:19:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1699597147; x=1700201947; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=y6aHgY7dVjq1emLLBr9I0qdToBO/wwiRz9A+uR2RPk0=; b=qZ5Yhh8VnH3CeIFte2/kg7Gw8DRSdl8rOgeOb09IT+1qbqpORszp3aYAFjzrcoSbl4 lEH8qtQO4jt+HhBbCevpc/PcY60Mj3VnpTjtXKatSWdvetFTHkdIpYQYBR3J07Nzenry ZAYcpLYoS7yQFK1RI9L7ClwnAeS1SCAO1lbqYIjqRcV63YgDOaiUUdsgxSjnQmy3KAWu HehXEezehAwjW3VcEdKMT8c7PjwvbGhB3sAn3vQrsoDlb7N7utOxMIU6bJMJMdwcGeS4 mcWvB5C6CLRaOvuBdCSFShRFrbtfXhp1qg9KCSealKdONR0vZtNcl8bRIJjaEjGtnJ0A Ij6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699597147; x=1700201947; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y6aHgY7dVjq1emLLBr9I0qdToBO/wwiRz9A+uR2RPk0=; b=d/kY4KYvRT0/8psB3O9GkH+1BkhiFjWsHfrdHSFxKTAmoxIfcpNAmA62RHcZ50wxOx LpsOiI/eL/DQ8ZG2U27HxhOpHpL2RVCjfj2zVnBzHBwsTC289Fph/27LxKhhgMMB/HpU mh42+yj2bAf3H+7Sai1vVO6N68aQhRXpUqZ0erG4CrS1JuOfQQ9QxJqXjEs9IcU0guPS 74bTeOFYFGd+vWohA2NSkW0HWViAA3xs9F6qyE45CrU8ECRhwCCFMsNeEBllj+CV9iJs i2JI/AlWV3fetAlujCDtKz2qImOnClp+SHv/uhrMeT6YY0HUYY3P8kngkIEcJOuM/AHT SrYg== X-Gm-Message-State: AOJu0YySCLpe0drdcroPUhJ/5SHa5jt1bmB2G/LgQ8/nxp7ecROSuHt6 QktlaQMHca3Q/W1dtAAADVe6VXNL4aSCgMIzw+rSWQ== X-Google-Smtp-Source: AGHT+IFpFkfHNHBYhJCAUHAcswVdjopAz96NNqXsNMtnhZD1PCclguvJ4ptzgVdeIGhBXO4+11fEaA== X-Received: by 2002:a17:902:d346:b0:1ce:a0b:7314 with SMTP id l6-20020a170902d34600b001ce0a0b7314mr525866plk.61.1699594947284; Thu, 09 Nov 2023 21:42:27 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:27 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:11 -0800 Subject: [PATCH v5 1/7] dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-1-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=855; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=sdi2GBRazAXQCmzsLeFCtwwLCyPq9k+jdkf3IoMSdfo=; b=ugpumf9QoPxX+bSKCeojrp6bqXrSAnaGYhOubo1XOKWuUAe+aPIamwK96g3G9BlWXJHvQsys5 SM5IH7XCovZCPWuPcsoCJ0439BkT26SbduFWhm4sFfHz07D59YfWw5g X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible value for the T-Head TH1520 dwcmshc controller. Acked-by: Guo Ren Acked-by: Krzysztof Kozlowski Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml = b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index a43eb837f8da..42804d955293 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - thead,th1520-dwcmshc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAB67C4332F for ; Fri, 10 Nov 2023 19:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346364AbjKJTYf (ORCPT ); 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Thu, 09 Nov 2023 21:42:29 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:28 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:12 -0800 Subject: [PATCH v5 2/7] mmc: sdhci: add __sdhci_execute_tuning() to header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-2-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=2108; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vV7D9g0JyI+aykknduEYFaEeV4K8xwyLfp1qBkgVUvA=; b=wiXFL4D9Q3411BhcGKUB1ePUooVyFCo6lIXJGCjVRVhgVo/MthWkxzFvbNGGV91mDj8tIZhb9 3ad00+5H/oQC96F88xLLDDeHjyQTU7R4MEvXiEmQLL2+zlo1saaRuND X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Expose __sdhci_execute_tuning() so that it can be called from the mmc host controller drivers. In the sdhci-of-dwcmshc driver, sdhci_dwcmshc_th1520_ops sets platform_execute_tuning to th1520_execute_tuning(). That function has to manipulate phy registers before tuning can be performed. To avoid copying the code verbatim from __sdhci_execute_tuning() into th1520_execute_tuning(), make it possible for __sdhci_execute_tuning() to be called from sdhci-of-dwcmshc. Acked-by: Adrian Hunter Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ff41aa56564e..c79f73459915 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2841,7 +2841,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 o= pcode) } EXPORT_SYMBOL_GPL(sdhci_send_tuning); =20 -static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; =20 @@ -2879,6 +2879,7 @@ static int __sdhci_execute_tuning(struct sdhci_host *= host, u32 opcode) sdhci_reset_tuning(host); return -EAGAIN; } +EXPORT_SYMBOL_GPL(__sdhci_execute_tuning); =20 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f219bdea8f28..a20864fc0641 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -793,6 +793,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int w= idth); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20814C4332F for ; Fri, 10 Nov 2023 19:39:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346069AbjKJTjz (ORCPT ); Fri, 10 Nov 2023 14:39:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236276AbjKJTjl (ORCPT ); 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Thu, 09 Nov 2023 21:42:30 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:30 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:13 -0800 Subject: [PATCH v5 3/7] mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-3-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=16973; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=3gSHCBEqPQFvvGlMyZC61TTwjlTvu8a46L7x9Br6Uto=; b=+AVqNs0Fc3RWT8BDa0eU46Y/dXo3wDBjzJDxuFemHrSmX3AWlSzBsI8LzrVyFi8j7mmedXmmF oNasxdMZBPwBTfcoQBJCtPKUktRz2A5K7bCv77CKoUSjPoyTvcdfxJp X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the mmc controller in the T-Head TH1520 with the new compatible "thead,th1520-dwcmshc". Implement custom sdhci_ops for set_uhs_signaling, reset, voltage_switch, and platform_execute_tuning. Acked-by: Adrian Hunter Signed-off-by: Drew Fustini --- drivers/mmc/host/sdhci-of-dwcmshc.c | 349 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 349 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-o= f-dwcmshc.c index 3a3bae6948a8..0eb72544c09e 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -35,6 +36,21 @@ #define DWCMSHC_CARD_IS_EMMC BIT(0) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DWCMSHC_EMMC_ATCTRL 0x40 +/* Tuning and auto-tuning fields in AT_CTRL_R control register */ +#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ +#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ +#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ +#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ +#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ +#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ +#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase co= de change */ +#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ +#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ +#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ +#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ +#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ +#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ =20 /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 @@ -72,6 +88,82 @@ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) =3D=3D 0)) #define RK35xx_MAX_CLKS 3 =20 +/* PHY register area pointer */ +#define DWC_MSHC_PTR_PHY_R 0x300 + +/* PHY general configuration */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ + +/* PHY command/response pad settings */ +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) + +/* PHY data pad settings */ +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) + +/* PHY clock pad settings */ +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) + +/* PHY strobe pad settings */ +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) + +/* PHY reset pad settings */ +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) + +/* Bitfields are common for all pad settings */ +#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ +#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ + +#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ +#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ +#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ + +#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ +#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ +#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ + +/* PHY CLK delay line settings */ +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC= */ + +/* PHY CLK delay line delay code */ +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ +#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ +#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ + +/* PHY drift_cclk_rx delay line configuration setting */ +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ +#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ + +/* PHY DLL control settings */ +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ +#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ + +/* PHY DLL configuration register 1 */ +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ +#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ +#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ + +/* PHY DLL configuration register 2 */ +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ + +/* PHY DLL master and slave delay line configuration settings */ +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ +#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL = */ + +#define FLAG_IO_FIXED_1V8 BIT(0) + #define BOUNDARY_OK(addr, len) \ ((addr | (SZ_128M - 1)) =3D=3D ((addr + len - 1) | (SZ_128M - 1))) =20 @@ -92,6 +184,8 @@ struct dwcmshc_priv { struct clk *bus_clk; int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ void *priv; /* pointer to SoC private stuff */ + u16 delay_line; + u16 flags; }; =20 /* @@ -157,6 +251,127 @@ static void dwcmshc_request(struct mmc_host *mmc, str= uct mmc_request *mrq) sdhci_request(mmc, mrq); } =20 +static void dwcmshc_phy_1_8v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val; + + /* deassert phy reset & set tx drive strength */ + val =3D PHY_CNFG_RSTN_DEASSERT; + val |=3D FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |=3D FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val =3D sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &=3D ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val =3D PHY_PAD_RXSEL_1V8; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val =3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val =3D PHY_PAD_RXSEL_1V8; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_C= NFG_SLV_INPSEL), + PHY_DLLDL_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void dwcmshc_phy_3_3v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val; + + /* deassert phy reset & set tx drive strength */ + val =3D PHY_CNFG_RSTN_DEASSERT; + val |=3D FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |=3D FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val =3D sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &=3D ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val =3D PHY_PAD_RXSEL_3V3; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val =3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val =3D PHY_PAD_RXSEL_3V3; + val |=3D FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |=3D FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void th1520_sdhci_set_phy(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 emmc_caps =3D MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; + u16 emmc_ctrl; + + /* Before power on, set PHY configs */ + if (priv->flags & FLAG_IO_FIXED_1V8) + dwcmshc_phy_1_8v_init(host); + else + dwcmshc_phy_3_3v_init(host); + + if ((host->mmc->caps2 & emmc_caps) =3D=3D emmc_caps) { + emmc_ctrl =3D sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EM= MC_CONTROL); + emmc_ctrl |=3D DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC= _CONTROL); + } + + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SL= VDLY) | + PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); +} + static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { @@ -189,9 +404,25 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_hos= t *host, ctrl_2 |=3D DWCMSHC_CTRL_HS400; } =20 + if (priv->flags & FLAG_IO_FIXED_1V8) + ctrl_2 |=3D SDHCI_CTRL_VDD_180; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } =20 +static void th1520_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + + dwcmshc_set_uhs_signaling(host, timing); + if (timing =3D=3D MMC_TIMING_MMC_HS400) + priv->delay_line =3D PHY_SDCLKDL_DC_HS400; + else + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + th1520_sdhci_set_phy(host); +} + static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -338,6 +569,79 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host= , u8 mask) sdhci_reset(host, mask); } =20 +static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 val =3D 0; + + if (host->flags & SDHCI_HS400_TUNING) + return 0; + + sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_IN= PSEL), + PHY_ATDL_CNFG_R); + val =3D sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCT= RL); + + /* + * configure tuning settings: + * - center phase select code driven in block gap interval + * - disable reporting of framing errors + * - disable software managed tuning + * - disable user selection of sampling window edges, + * instead tuning calculated edges are used + */ + val &=3D ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | + FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); + + /* + * configure tuning settings: + * - enable auto-tuning + * - enable sampling window threshold + * - stop clocks during phase code change + * - set max latency in cycles between tx and rx clocks + * - set max latency in cycles to switch output phase + * - set max sampling window threshold value + */ + val |=3D AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; + val |=3D FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); + val |=3D FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY= ); + val |=3D FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); + + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL= ); + val =3D sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCT= RL); + + /* perform tuning */ + sdhci_start_tuning(host); + host->tuning_err =3D __sdhci_execute_tuning(host, opcode); + if (host->tuning_err) { + /* disable auto-tuning upon tuning error */ + val &=3D ~AT_CTRL_AT_EN; + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTR= L); + dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); + return -EIO; + } + sdhci_end_tuning(host); + + return 0; +} + +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u16 ctrl_2; + + sdhci_reset(host, mask); + + if (priv->flags & FLAG_IO_FIXED_1V8) { + ctrl_2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { + ctrl_2 |=3D SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } + } +} + static const struct sdhci_ops sdhci_dwcmshc_ops =3D { .set_clock =3D sdhci_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -356,6 +660,17 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops= =3D { .adma_write_desc =3D dwcmshc_adma_write_desc, }; =20 +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops =3D { + .set_clock =3D sdhci_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D th1520_set_uhs_signaling, + .get_max_clock =3D dwcmshc_get_max_clock, + .reset =3D th1520_sdhci_reset, + .adma_write_desc =3D dwcmshc_adma_write_desc, + .voltage_switch =3D dwcmshc_phy_1_8v_init, + .platform_execute_tuning =3D &th1520_execute_tuning, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata =3D { .ops =3D &sdhci_dwcmshc_ops, .quirks =3D SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, @@ -379,6 +694,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3= 5xx_pdata =3D { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; =20 +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata =3D { + .ops =3D &sdhci_dwcmshc_th1520_ops, + .quirks =3D SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_pri= v *dwc_priv) { int err; @@ -447,6 +768,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[= ] =3D { .compatible =3D "snps,dwcmshc-sdhci", .data =3D &sdhci_dwcmshc_pdata, }, + { + .compatible =3D "thead,th1520-dwcmshc", + .data =3D &sdhci_dwcmshc_th1520_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); @@ -542,6 +867,30 @@ static int dwcmshc_probe(struct platform_device *pdev) goto err_clk; } =20 + if (pltfm_data =3D=3D &sdhci_dwcmshc_th1520_pdata) { + priv->delay_line =3D PHY_SDCLKDL_DC_DEFAULT; + + if ((device_property_read_bool(dev, "mmc-ddr-1_8v")) | + (device_property_read_bool(dev, "mmc-hs200-1_8v")) | + (device_property_read_bool(dev, "mmc-hs400-1_8v"))) + priv->flags |=3D FLAG_IO_FIXED_1V8; + else + priv->flags &=3D ~FLAG_IO_FIXED_1V8; + + /* + * start_signal_voltage_switch() will try 3.3V first + * then 1.8V. Use SDHCI_SIGNALING_180 rather than + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V + * in sdhci_start_signal_voltage_switch(). + */ + if (priv->flags & FLAG_IO_FIXED_1V8) { + host->flags &=3D ~SDHCI_SIGNALING_330; + host->flags |=3D SDHCI_SIGNALING_180; + } + + sdhci_enable_v4_mode(host); + } + #ifdef CONFIG_ACPI if (pltfm_data =3D=3D &sdhci_dwcmshc_bf3_pdata) sdhci_enable_v4_mode(host); --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87156C04A95 for ; Fri, 10 Nov 2023 18:32:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344534AbjKJScd (ORCPT ); Fri, 10 Nov 2023 13:32:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346603AbjKJSbX (ORCPT ); Fri, 10 Nov 2023 13:31:23 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E88E2184 for ; Thu, 9 Nov 2023 22:11:38 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id af79cd13be357-77bcbc14899so3594585a.1 for ; Thu, 09 Nov 2023 22:11:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1699596659; x=1700201459; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xY9e61NSBd34WKgwLiextVdIl1pEHWCBao7kYEHaYbc=; b=SqNnB1jH6mb/MYWSqSifl/rgG8CG0cf01AYTjzN14rrtT0kITUUDzE8EQXVDSpUVfA VqQReYFdKzG4zxz6OcGQLEwMQY61Ws5uxWkDaYMB6tbS3HET10vtGZqrnFZxqxfA+tyG +5XQtFVthtKB0hMK75z7X5loOGQyBhKnOsxiJ5LZcm0V1bQFC+IsWpnxZca0h3WKpUIu yr5ybMyZK4uuoFEuxL0aQGrUmGqSNwnWC9kxX2TR/Sds6yXZb4Luhe647I1OsH/uUCIP htPfcMFq1yGIPcH1drvWWxlbR4jBf3PqGYrwYRRkWaFhlhVLhk2KISl2ShV3jCH0D1dR N9NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699596659; x=1700201459; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xY9e61NSBd34WKgwLiextVdIl1pEHWCBao7kYEHaYbc=; b=oMOWCNdbgY414P+w2ey3Z9nSpgKBR0tSUi/KZ2dQjuHmfoS3cIQOZ525pI/j0bb3Xe r0eneZP3rMtD0cG7hNRfWjn1fRSBv9ZhoFYhryUbxRblKZc3HPsL3In+0RpizfrZTBDR Y/v+cSWhaW0uFJr/TGXMs/AsMPWp2wFUjK37l+yd14LnktImqWD/Ge6XBckx7iowRT8K VzzmhCLiTmNAkWHB06Ytx/uUst+pW7//ybs2kbGaptUG909O1anCgvtcHXsvdlKP9eC9 AraDMD1xa3vH+GDs57fwaZ/JThH+rCnx/sR3hKMYQY31vjGyqsNo7+304sOWkJpEY7D2 JmHA== X-Gm-Message-State: AOJu0Ywomlqt3ryJVeP02N9k3QYeV2uCOKB5eao9K1IBbDcoWeN/eDaJ MgvQ69Cm8rE78ZX+MR+3FwIwmumOEHeT2XGz/YRAWw== X-Google-Smtp-Source: AGHT+IGXmrfa4qbmD8PufQBo8ECvg8/RA13eLrik89guDJz1lWQRgT5GoM06ddfpEcVwZ1Qo931DgQ== X-Received: by 2002:a17:902:8c92:b0:1ca:8b90:1cbd with SMTP id t18-20020a1709028c9200b001ca8b901cbdmr6854012plo.0.1699594952706; Thu, 09 Nov 2023 21:42:32 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:32 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:14 -0800 Subject: [PATCH v5 4/7] riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-4-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=915; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=ht5Rt9iMCRM1t5yThjxoCTbuOVz3OXmRTAYLzzfd3/s=; b=81YrMX/6Pup0Mk4t9Mpny542tULxqVs1k+13xNQqBbmGqkaQgZCsQjsJdqcuxcUGHQdm9Sdy0 DormnbG2KwrClt9J1tjQHZ3FwqQMqAeqmWYK1a5r2HceKW/UQkdU9DC X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the mmc controller driver and dma controller driver needed for T-Head TH1520 based boards, like the LicheePi 4A and BeagleV-Ahead, to boot from eMMC storage. Reviewed-by: Guo Ren Signed-off-by: Drew Fustini --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..c5a8583236d0 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -168,12 +168,14 @@ CONFIG_MMC=3Dy CONFIG_MMC_SDHCI=3Dy CONFIG_MMC_SDHCI_PLTFM=3Dy CONFIG_MMC_SDHCI_CADENCE=3Dy +CONFIG_MMC_SDHCI_OF_DWCMSHC=3Dy CONFIG_MMC_SPI=3Dy CONFIG_MMC_SUNXI=3Dy CONFIG_RTC_CLASS=3Dy CONFIG_RTC_DRV_SUN6I=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm +CONFIG_DW_AXI_DMAC=3Dy CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E38C8C4167D for ; Fri, 10 Nov 2023 19:20:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346185AbjKJTUp (ORCPT ); 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Thu, 09 Nov 2023 21:42:34 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:34 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:15 -0800 Subject: [PATCH v5 5/7] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-5-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=1608; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=118IOeI3EDHQnRGvuv5ewuNsGEAnYvxtIZdzQTMEyXk=; b=yeOrLz+tWTsGAfXBiTlsUCM457E2vnWs1IdM64XT3ndoS1ZsuBso99iSFBRWZAC6Hpujod2vK xZA5w+PGj/PAXAJNWux4UMW0MTSz3dqYn8V63Datq2uZLRYpXMPuJ8B X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add node for the SDHCI fixed clock. Add mmc0 node for the first mmc controller instance which is typically connected to the eMMC device. Add mmc1 node for the second mmc controller instance which is typically connected to microSD slot. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index ff364709a6df..f5ec9326c4b8 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells =3D <0>; }; =20 + sdhci_clk: sdhci-clock { + compatible =3D "fixed-clock"; + clock-frequency =3D <198000000>; + clock-output-names =3D "sdhci_clk"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -292,6 +299,22 @@ dmac0: dma-controller@ffefc00000 { status =3D "disabled"; }; =20 + mmc0: mmc@ffe7080000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe7080000 0x0 0x10000>; + interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + }; + + mmc1: mmc@ffe7090000 { + compatible =3D "thead,th1520-dwcmshc"; + reg =3D <0xff 0xe7090000 0x0 0x10000>; + interrupts =3D <64 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&sdhci_clk>; + clock-names =3D "core"; + }; + timer0: timer@ffefc32000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xefc32000 0x0 0x14>; --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0118BC4332F for ; Fri, 10 Nov 2023 20:37:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346371AbjKJUhJ (ORCPT ); Fri, 10 Nov 2023 15:37:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346070AbjKJUgo (ORCPT ); Fri, 10 Nov 2023 15:36:44 -0500 Received: from mail-oi1-x22d.google.com (mail-oi1-x22d.google.com [IPv6:2607:f8b0:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 938C57D9E for ; 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Thu, 09 Nov 2023 21:42:36 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:16 -0800 Subject: [PATCH v5 6/7] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-6-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=1108; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=4bgo3aK3cuR26cRWBbMVA6MrvhUqOJ8As8gzvmDCzhs=; b=lALKEKj8Qm8uCPZT94ZeDZCapEMna2PJb7qYfmxdtsiIiPu5ZBsq1ZTsCjmwM7LQeHswhFuMT bUj9CkooLlrCm59R+vpdz5OfJa2nhKLJZ6dvleve4V8ZDgXFGGMNDkz X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mmc0 properties for the eMMC device and add mmc1 properties for the microSD slot. Set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 ++++++++++++++++++= ++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index 70e8042c8304..f91d94f95510 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -48,6 +48,10 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 +&sdhci_clk { + clock-frequency =3D <198000000>; +}; + &uart_sclk { clock-frequency =3D <100000000>; }; @@ -56,6 +60,22 @@ &dmac0 { status =3D "okay"; }; =20 +&mmc0 { + bus-width =3D <8>; + max-frequency =3D <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&mmc1 { + max-frequency =3D <198000000>; + bus-width =3D <4>; + status =3D "okay"; +}; + &uart0 { status =3D "okay"; }; --=20 2.34.1 From nobody Tue Dec 16 11:45:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D4CC4167B for ; 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Thu, 09 Nov 2023 21:42:38 -0800 (PST) Received: from [127.0.1.1] ([2601:1c2:1800:f680:2071:4479:98b8:cc69]) by smtp.gmail.com with ESMTPSA id ix22-20020a170902f81600b001b8a00d4f7asm4498845plb.9.2023.11.09.21.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 21:42:37 -0800 (PST) From: Drew Fustini Date: Thu, 09 Nov 2023 21:41:17 -0800 Subject: [PATCH v5 7/7] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-th1520-mmc-v5-7-018bd039cf17@baylibre.com> References: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> In-Reply-To: <20231109-th1520-mmc-v5-0-018bd039cf17@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Fu Wei , Conor Dooley Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1699594943; l=1102; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vZkA/Rp2zWEJvsAGA/badfpHmHgx6/3DqqLzYe2IxQc=; b=fJaLj8Us7PpYhDPHDt2gAJV0CgQsotNJKZ73gVndaddpreipV21Pv9bXilRM3ODn6eiDa/Ubk h7kJ2SCtnDZD8g4t2P9LyI/wn5hmo7COmgWYmsLyqjWJR3zX5ICneL5 X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mmc0 properties for the eMMC device and add mmc1 properties for the microSD slot. Set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..94f1741435a5 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,6 +29,10 @@ &apb_clk { clock-frequency =3D <62500000>; }; =20 +&sdhci_clk { + clock-frequency =3D <198000000>; +}; + &uart_sclk { clock-frequency =3D <100000000>; }; @@ -36,3 +40,19 @@ &uart_sclk { &dmac0 { status =3D "okay"; }; + +&mmc0 { + bus-width =3D <8>; + max-frequency =3D <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&mmc1 { + max-frequency =3D <198000000>; + bus-width =3D <4>; + status =3D "okay"; +}; --=20 2.34.1