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Thu, 09 Nov 2023 03:30:29 -0800 (PST) Received: from [127.0.0.1] ([37.228.218.3]) by smtp.gmail.com with ESMTPSA id a11-20020adfed0b000000b0032d9337e7d1sm7185790wro.11.2023.11.09.03.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 03:30:28 -0800 (PST) From: Bryan O'Donoghue Date: Thu, 09 Nov 2023 11:30:24 +0000 Subject: [PATCH v4 4/6] media: qcom: camss: Add sc8280xp resource details MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231109-b4-camss-sc8280xp-v4-4-58a58bc200f9@linaro.org> References: <20231109-b4-camss-sc8280xp-v4-0-58a58bc200f9@linaro.org> In-Reply-To: <20231109-b4-camss-sc8280xp-v4-0-58a58bc200f9@linaro.org> To: hverkuil-cisco@xs4all.nl, laurent.pinchart@ideasonboard.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , vincent.knecht@mailoo.org, matti.lehtimaki@gmail.com, quic_grosikop@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.13-dev-26615 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit describes the hardware layout for the sc8280xp for the following hardware blocks: - 4 x VFE, 4 RDI per VFE - 4 x VFE Lite, 4 RDI per VFE - 4 x CSID - 4 x CSID Lite - 4 x CSI PHY Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 307 ++++++++++++++++++++++++++= ++++ 1 file changed, 307 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 8778fdc1ee342..fff891a72c850 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -941,6 +941,298 @@ static const struct resources_icc icc_res_sm8250[] = =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_sc8280xp[] =3D { + /* CSIPHY0 */ + { + .regulators =3D {}, + .clock =3D { "csiphy0", "csiphy0_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY1 */ + { + .regulators =3D {}, + .clock =3D { "csiphy1", "csiphy1_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY2 */ + { + .regulators =3D {}, + .clock =3D { "csiphy2", "csiphy2_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, + /* CSIPHY3 */ + { + .regulators =3D {}, + .clock =3D { "csiphy3", "csiphy3_timer" }, + .clock_rate =3D { { 400000000 }, + { 300000000 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .ops =3D &csiphy_ops_3ph_1_0 + }, +}; + +static const struct camss_subdev_resources csid_res_sc8280xp[] =3D { + /* CSID0 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID1 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID2 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID3 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe3_csid", "vfe3_cphy_rx", "vfe3", "vfe3_axi" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, + { 0 } }, + .reg =3D { "csid3" }, + .interrupt =3D { "csid3" }, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE0 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid0_lite" }, + .interrupt =3D { "csid0_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE1 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid1_lite" }, + .interrupt =3D { "csid1_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE2 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite2_csid", "vfe_lite2_cphy_rx", "vfe_lite2" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid2_lite" }, + .interrupt =3D { "csid2_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + }, + /* CSID_LITE3 */ + { + .regulators =3D { "vdda-phy", "vdda-pll" }, + .clock =3D { "vfe_lite3_csid", "vfe_lite3_cphy_rx", "vfe_lite3" }, + .clock_rate =3D { { 400000000, 400000000, 480000000, 600000000, 60000000= 0, 600000000 }, + { 0 }, + { 0 }, }, + .reg =3D { "csid3_lite" }, + .interrupt =3D { "csid3_lite" }, + .is_lite =3D true, + .ops =3D &csid_ops_gen2 + } +}; + +static const struct camss_subdev_resources vfe_res_sc8280xp[] =3D { + /* IFE0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0= ", "vfe0_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .pd_name =3D "ife0", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* IFE1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe1= ", "vfe1_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .pd_name =3D "ife1", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* IFE2 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe2= ", "vfe2_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .pd_name =3D "ife2", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE3 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe3= ", "vfe3_axi" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 400000000, 558000000, 637000000, 760000000 }, + { 0 }, }, + .reg =3D { "vfe3" }, + .interrupt =3D { "vfe3" }, + .pd_name =3D "ife3", + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* IFE_LITE_0 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite0" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* IFE_LITE_1 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite1" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* IFE_LITE_2 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite2" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000, }, }, + .reg =3D { "vfe_lite2" }, + .interrupt =3D { "vfe_lite2" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, + /* VFE_LITE_3 */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe_= lite3" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 19200000, 80000000, 80000000, 80000000, 80000000}, + { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 }, + { 320000000, 400000000, 480000000, 600000000 }, }, + .reg =3D { "vfe_lite3" }, + .interrupt =3D { "vfe_lite3" }, + .is_lite =3D true, + .line_num =3D 4, + .ops =3D &vfe_ops_170 + }, +}; + +static const struct resources_icc icc_res_sc8280xp[] =3D { + { + .name =3D "cam_ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + { + .name =3D "cam_hf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "cam_sf_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, + { + .name =3D "cam_sf_icp_mnoc", + .icc_bw_tbl.avg =3D 2097152, + .icc_bw_tbl.peak =3D 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1824,12 +2116,27 @@ static const struct camss_resources sm8250_resource= s =3D { .vfe_num =3D ARRAY_SIZE(vfe_res_8250), }; =20 +static const struct camss_resources sc8280xp_resources =3D { + .version =3D CAMSS_8280XP, + .pd_name =3D "top", + .csiphy_res =3D csiphy_res_sc8280xp, + .csid_res =3D csid_res_sc8280xp, + .ispif_res =3D NULL, + .vfe_res =3D vfe_res_sc8280xp, + .icc_res =3D icc_res_sc8280xp, + .icc_path_num =3D ARRAY_SIZE(icc_res_sc8280xp), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_sc8280xp), + .csid_num =3D ARRAY_SIZE(csid_res_sc8280xp), + .vfe_num =3D ARRAY_SIZE(vfe_res_sc8280xp), +}; + static const struct of_device_id camss_dt_match[] =3D { { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8996-camss", .data =3D &msm8996_resources }, { .compatible =3D "qcom,sdm660-camss", .data =3D &sdm660_resources }, { .compatible =3D "qcom,sdm845-camss", .data =3D &sdm845_resources }, { .compatible =3D "qcom,sm8250-camss", .data =3D &sm8250_resources }, + { .compatible =3D "qcom,sc8280xp-camss", .data =3D &sc8280xp_resources }, { } }; =20 --=20 2.42.0