From nobody Wed Dec 31 05:06:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA6EEC4332F for ; Wed, 8 Nov 2023 00:32:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344341AbjKHAc6 (ORCPT ); Tue, 7 Nov 2023 19:32:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344242AbjKHAcV (ORCPT ); Tue, 7 Nov 2023 19:32:21 -0500 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 405B6171B for ; Tue, 7 Nov 2023 16:32:08 -0800 (PST) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1cc29f3afe0so42784095ad.2 for ; Tue, 07 Nov 2023 16:32:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699403527; x=1700008327; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=wf+zlCo108XjvE8MPLJv7QMxtCkSi3xWeOr1iRY+q5s=; b=IiEyOS4++t0n0zdyc2LUBn/oMOqmwrNdLeRwB6moKHobZhTaUSoTAo/XZ2rdsj86Fu Exm7j+JYXirpA2BQ2EhoJkdZM4jRBmZy4+rUn/gH3v3ym/UM77LW78E+Z3lFXoRXEU7i dBruiI9ygZBOTYbXbXfw/pQn2qKUmtYgGxKcKeIdLAPADyPn0AHd6koBqu1wsUHbNmkJ uHIic4oEygCifzmt6OwfmHmehMmD9uuwGgdsb6SbdWt53LRUBACXS7BEAb1qHO4MsloZ PbXzWybMkdCBQsIZC/MclLAxd8xF6DahNI+aON7siz2vwusW4l1ht7S+GHAVyZGniipu 8q9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699403527; x=1700008327; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=wf+zlCo108XjvE8MPLJv7QMxtCkSi3xWeOr1iRY+q5s=; b=Dap7JgrAIBKUsFYeUEwrny560HFbMgBB1g4emAiIINz3johI3LWfvyXd+z+HktOAVk 8lxz329ee9/+TVybkor8jRxkvcaBIAiWk/cXCbVxruEBdPfwKArDReMbt5HlOKIjLSXw p+8PYXuO5vueYNEeX2mXX/fKyRv/SQWrxBzkYVoKSfpmoqEIWyJdAG76NGmA8PsF/0AZ mevLnw9fSzM8s/IQGwEtUH50/fW6YRlntOSvD0tHg9iF1yF4XPfHfCRh79CSkZRLE9/3 hBdcAt24XyFfFN8KLUlPfq94noV4CpeqMzGEheO6AkQi8CQWy0/4/BYdfsNh9UfTvb+x jKVA== X-Gm-Message-State: AOJu0YyY0KBgxedY6aW0sDmzf92wgPFCRCwSHUIVKm/wrOe8up9HSFiw VQ9xmwlV11cCJDoTEUivTbkY4ABcVGE= X-Google-Smtp-Source: AGHT+IHpqXH93BuoM8nASqCZx+4iPfRz0k+281ENJSLbjLBcyetm56SJ9AMszb5E05Ot1D2NwuPeTaG/iNY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:f7d6:b0:1cc:2bff:fe61 with SMTP id h22-20020a170902f7d600b001cc2bfffe61mr10573plw.3.1699403527679; Tue, 07 Nov 2023 16:32:07 -0800 (PST) Reply-To: Sean Christopherson Date: Tue, 7 Nov 2023 16:31:30 -0800 In-Reply-To: <20231108003135.546002-1-seanjc@google.com> Mime-Version: 1.0 References: <20231108003135.546002-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231108003135.546002-15-seanjc@google.com> Subject: [PATCH v7 14/19] KVM: selftests: Expand PMU counters test to verify LLC events From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jim Mattson , Jinrong Liang , Aaron Lewis , Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expand the PMU counters test to verify that LLC references and misses have non-zero counts when the code being executed while the LLC event(s) is active is evicted via CFLUSH{,OPT}. Note, CLFLUSH{,OPT} requires a fence of some kind to ensure the cache lines are flushed before execution continues. Use MFENCE for simplicity (performance is not a concern). Suggested-by: Jim Mattson Signed-off-by: Sean Christopherson Reviewed-by: Dapeng Mi --- .../selftests/kvm/x86_64/pmu_counters_test.c | 59 +++++++++++++------ 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index b9c073d3ade9..90381382c51f 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -14,9 +14,9 @@ /* * Number of "extra" instructions that will be counted, i.e. the number of * instructions that are needed to set up the loop and then disabled the - * counter. 2 MOV, 2 XOR, 1 WRMSR. + * counter. 1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE, 2 MOV, 2 XOR, 1 WRMSR. */ -#define NUM_EXTRA_INSNS 5 +#define NUM_EXTRA_INSNS 7 #define NUM_INSNS_RETIRED (NUM_BRANCHES + NUM_EXTRA_INSNS) =20 static uint8_t kvm_pmu_version; @@ -107,6 +107,12 @@ static void guest_assert_event_count(uint8_t idx, case INTEL_ARCH_BRANCHES_RETIRED_INDEX: GUEST_ASSERT_EQ(count, NUM_BRANCHES); break; + case INTEL_ARCH_LLC_REFERENCES_INDEX: + case INTEL_ARCH_LLC_MISSES_INDEX: + if (!this_cpu_has(X86_FEATURE_CLFLUSHOPT) && + !this_cpu_has(X86_FEATURE_CLFLUSH)) + break; + fallthrough; case INTEL_ARCH_CPU_CYCLES_INDEX: case INTEL_ARCH_REFERENCE_CYCLES_INDEX: GUEST_ASSERT_NE(count, 0); @@ -123,29 +129,44 @@ static void guest_assert_event_count(uint8_t idx, GUEST_ASSERT_EQ(_rdpmc(pmc), 0xdead); } =20 +/* + * Enable and disable the PMC in a monolithic asm blob to ensure that the + * compiler can't insert _any_ code into the measured sequence. Note, ECX + * doesn't need to be clobbered as the input value, @pmc_msr, is restored + * before the end of the sequence. + * + * If CLFUSH{,OPT} is supported, flush the cacheline containing (at least)= the + * start of the loop to force LLC references and misses, i.e. to allow tes= ting + * that those events actually count. + */ +#define GUEST_MEASURE_EVENT(_msr, _value, clflush) \ +do { \ + __asm__ __volatile__("wrmsr\n\t" \ + clflush "\n\t" \ + "mfence\n\t" \ + "1: mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" \ + "loop .\n\t" \ + "mov %%edi, %%ecx\n\t" \ + "xor %%eax, %%eax\n\t" \ + "xor %%edx, %%edx\n\t" \ + "wrmsr\n\t" \ + :: "a"((uint32_t)_value), "d"(_value >> 32), \ + "c"(_msr), "D"(_msr) \ + ); \ +} while (0) + static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_featur= e event, uint32_t pmc, uint32_t pmc_msr, uint32_t ctrl_msr, uint64_t ctrl_msr_value) { wrmsr(pmc_msr, 0); =20 - /* - * Enable and disable the PMC in a monolithic asm blob to ensure that - * the compiler can't insert _any_ code into the measured sequence. - * Note, ECX doesn't need to be clobbered as the input value, @pmc_msr, - * is restored before the end of the sequence. - */ - __asm__ __volatile__("wrmsr\n\t" - "mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" - "loop .\n\t" - "mov %%edi, %%ecx\n\t" - "xor %%eax, %%eax\n\t" - "xor %%edx, %%edx\n\t" - "wrmsr\n\t" - :: "a"((uint32_t)ctrl_msr_value), - "d"(ctrl_msr_value >> 32), - "c"(ctrl_msr), "D"(ctrl_msr) - ); + if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflushopt 1f"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflush 1f"); + else + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "nop"); =20 guest_assert_event_count(idx, event, pmc, pmc_msr); } --=20 2.42.0.869.gea05f2083d-goog