From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B1FAC4167D for ; Tue, 7 Nov 2023 10:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234261AbjKGK4X (ORCPT ); Tue, 7 Nov 2023 05:56:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233986AbjKGK4K (ORCPT ); Tue, 7 Nov 2023 05:56:10 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB34E122 for ; Tue, 7 Nov 2023 02:56:02 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-32f831087c6so1250673f8f.0 for ; Tue, 07 Nov 2023 02:56:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354561; x=1699959361; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yWXszjrW0mqtPT5ge0XuiGQJ6aaCxrPofMKEXjPvYnQ=; b=c4wX3fG5F8aKGGSfMvLi2Y10+n1g6YLC+lOXGQAKQwVD0nXggrkTKAPvnjXEHsPpLi Tv4HM0vAaLODqcka4Ei5ysUBLc1Yv9aFeOGTq9LxzeXy98reED89s/UFBrluLK6VpMHo Y7eJNQhTTPwtkWSQy482lR8DOlQkpvD6uSqKqnSH6t37wdnzgWpAMBTXewPWMX1k75TQ J3yG0alz4pmsuQ3f5xZK7wdfCUOfEttBddRUyrnKDuHqAarzm6ZHy9RHovNXQiOQ5bTK mvC6s5xAnAaRHmqcbIxLkhLl2Z1wRY4yx9TD2unBfEC0Lx+i+avJ7H6cqhWSZMM+kN8c dECw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354561; x=1699959361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWXszjrW0mqtPT5ge0XuiGQJ6aaCxrPofMKEXjPvYnQ=; b=PHfczgiKzSW14Dhe8ZIeicdcVEhGh0vqdrKVr/Yrp2/9zZvuar+d6dA2SqYvWEtPMQ eFaAPae/y6in35FLYf05M5F2MPI+Ye4AonA3u2F2IeP/1yTZZL/q6eiwmTh+KFwHJolP oHU8QxjpR3pNmEiZMSLmcR8rTOTr2YJNm4irgdrYqACvxuLwhVFZMru99TCimXvqinBn y5pqudzOTZ38H+KXrOTh8U0l374gGuTX2We4f3LgpkBktf9aw+0R8xwSuT/d2rCH89Jv objaLVc2UlmuA66DDSIgY4d+tKwv0CicW99WeSLpXqPC/FhMCskb54JInIK5wuIec1Rn yV4g== X-Gm-Message-State: AOJu0YymQ2ATm41fqpelZYMXrYyJ4CROEE43n0qJruIGgBFgwgURdDNA JK3fu7i+DIjiSkXswpG2a1AqyQ== X-Google-Smtp-Source: AGHT+IGuavTtsmwxI8/q0+XaTOH3JqZmAYfCgV3LA6iUJWNnV+0tLfzziM9Sx1y+OIsrf624uUG+Gg== X-Received: by 2002:a05:600c:418a:b0:3fe:d637:7b25 with SMTP id p10-20020a05600c418a00b003fed6377b25mr25010147wmh.0.1699354561462; Tue, 07 Nov 2023 02:56:01 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:00 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 01/20] riscv: hwprobe: factorize hwprobe ISA extension reporting Date: Tue, 7 Nov 2023 11:55:37 +0100 Message-ID: <20231107105556.517187-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Factorize ISA extension reporting by using a macro rather than copy/pasting extension names. This will allow adding new extensions more easily. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/kernel/sys_riscv.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index b651ec698a91..49aa4e82797c 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,24 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pa= ir, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; =20 - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBA; - else - missing |=3D RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBB; - else - missing |=3D RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBS; - else - missing |=3D RISCV_HWPROBE_EXT_ZBS; +#define CHECK_ISA_EXT(__ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ + pair->value |=3D RISCV_HWPROBE_EXT_##__ext; \ + else \ + missing |=3D RISCV_HWPROBE_EXT_##__ext; \ + } while (false) + + /* + * Only use CHECK_ISA_EXT() for extensions which are usable by + * userspace with respect to the kernel current configuration. + * For instance, ISA extensions that use float operations + * should not be exposed when CONFIG_FPU is not enabled. + */ + CHECK_ISA_EXT(ZBA); + CHECK_ISA_EXT(ZBB); + CHECK_ISA_EXT(ZBS); +#undef CHECK_ISA_EXT } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B56A7C0018C for ; Tue, 7 Nov 2023 10:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234214AbjKGK4S (ORCPT ); Tue, 7 Nov 2023 05:56:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233987AbjKGK4K (ORCPT ); Tue, 7 Nov 2023 05:56:10 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84F3EB6 for ; Tue, 7 Nov 2023 02:56:04 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40a279663a2so3105605e9.1 for ; Tue, 07 Nov 2023 02:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354563; x=1699959363; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UA6TaO+YV3P6uG5ehiL6SbNfsZ4OUqVSTDbxUXfxm5E=; b=mslxwdHQuWaxcrulAW+VEopaf9tk0MPHPvLPkbFz93m2isk4gU8wKtuq33s71LZeXy iLQBVSbA68L00sFT70I10E8nKpr6Ym4+xXu8cT6mag8ZIGzFadGA6Ox27b9SKQOSEyXX XKBxsssx+VTa4F5ZtojQcOEgbuxp9C8fFVli46UxfNtyBbhylGlKH7EWUZUX0YJFQ044 ZF4k5iAhcFfkSDZFIxaIovcTBOQOE2hO02iXlipf99Qq7ZmZ+/DGKCPnSa/z8xyUEfQh +D1DAnpHe8BrBblLxxOCnDAhjt9FeaCzeqWgz0EKJlULfZjply/xm9N9Y4N0qNsaeY+Q S6Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354563; x=1699959363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UA6TaO+YV3P6uG5ehiL6SbNfsZ4OUqVSTDbxUXfxm5E=; b=Vi4MEdVT1MTsrnsfQYbHg+q7Poh/x8rkhNJGYS9P9TB+Z7onHJcBFt73gS47DzvR27 ORikUt8rBhmAby7rzgHCFzgKQfbIG2mfXMJJFC8iMTPBbmm9QDvyQa/eBwHslswRcm0U kSq5pivhyZ9IXt25k51S5lHMYLHwUwgLYSnD66snI+V7GrYK6vjSLC71QoG+iYErDMLl SrfBV73V+hBFtXoUtqFVGaKUzALlFab2XF/BjldAw1RZOoeFsoNkeeEFOc8P1LDVdFYa XLs/m/k7+9JVlPl/NJejzcMDuyEZIbW91tNxFIpN3IBH4Fg6A5VWxMraRabR+wXz2Ayu REmQ== X-Gm-Message-State: AOJu0YyGn9f1eaj2K2LS67fP7qq6cTjPfpj+/LS2vFlcrBo4Y5j5gMSz MxlNkzkZmTJNaQB+MxuBWaL53Q== X-Google-Smtp-Source: AGHT+IEDB5qlOk6FgrKsa3qj9SE6v/Kfu6peNUysoGxbasqez5sPqF/BIOxq9sfcbgB58kS3oj4koA== X-Received: by 2002:a05:600c:3b93:b0:405:3cc1:e115 with SMTP id n19-20020a05600c3b9300b004053cc1e115mr25948840wms.3.1699354562728; Tue, 07 Nov 2023 02:56:02 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:01 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 02/20] riscv: hwprobe: export missing Zbc ISA extension Date: Tue, 7 Nov 2023 11:55:38 +0100 Message-ID: <20231107105556.517187-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org While ISA string parsing has been added, Zbc was not export through hwprobe interface. Export and document this extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index a52996b22f75..ecc0307c107e 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -77,6 +77,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as d= efined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as de= fined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index d43e306ce2f9..dcef5c33c009 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZBC (1 << 6) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 49aa4e82797c..382cd71129c6 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZBA); CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); + CHECK_ISA_EXT(ZBC); #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB543C4167B for ; Tue, 7 Nov 2023 10:56:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234263AbjKGK40 (ORCPT ); Tue, 7 Nov 2023 05:56:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233980AbjKGK4N (ORCPT ); Tue, 7 Nov 2023 05:56:13 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41C78D71 for ; Tue, 7 Nov 2023 02:56:06 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2c519eab81fso10207631fa.1 for ; Tue, 07 Nov 2023 02:56:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354564; x=1699959364; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=884mjVBUf/B5xVe7Mn+vWmHn9PLqi2rVnCfcoQ9sUfs=; b=bYdOzr/EuQEJquBgHwf/rkMrDMUQn3h7l9IT/ZRd7I64tY0Mx/NJ2APmFIUPrkn7ex Os4cQdideQ8X1DBU+TpAE2ibVM4rdkCd+6L8e9MSlCuy2+wD7GiOk7qUi9ZsCgtFyVKD XGr+KhOyl3L1w9V57hhoCu8wik35kM7kXuCIPK6G99rEIe/+7mF5IbxVZDC2dys4IPAN IdfNZ3V23Fr7B8anAtzKuzgB3ROxYCg8LXI4xRYMjAZleKKd7t9OJhU8cV9Kr5mtwYeS dsVip9L3AomT9Ue9T2TXOId0TEaIHjQi6ngKabCb880jLLNPkISD8j0Vd1yMNb7fBmxp hAQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354564; x=1699959364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=884mjVBUf/B5xVe7Mn+vWmHn9PLqi2rVnCfcoQ9sUfs=; b=f8hEufqxpO1jVDkegeMMdF/LDo7zhnLqUvuP8z+Wo15NvMQBEyXyMmBrmeCnAkeFVl bt471sfNDjjjxB+Co46bx/3fPn5Slju6LZLMv611dw4fZzwbodQrmoDr+rtanftZNGWt tgt84ymOsv7D5TUNa65beaGx3G/17rPU1xVaW9Rfe5+IxSrXfB2IUVB9I5m/rfc32s5i I60e+4OmldgdjKUIdMyfBTsro3okUuj79LAXVqw0uGnRau1xEkKR62kRYliDmAkvZGJj Ip3rJG1ija/eUoG0l0QSSRegZtLr4/UsQlqN88lZPi1FmXwk4WzKMbV3I6DdJ5gFStl7 KrWw== X-Gm-Message-State: AOJu0Ywv0IC0kjeYaQJYgEJoZZ9+WgZNuTK21KiHEckSBLWgM1JfTaP5 /alBErC8H3bmVEVofqr7/KfRVQ== X-Google-Smtp-Source: AGHT+IHXvy/dIISU7g85YMpjpEsVNYZwgjK7rpkPblu9B0vYp48kVxXXr9Iu/Jk+bQRG62RXowl+sg== X-Received: by 2002:a2e:7a19:0:b0:2c0:196c:e38f with SMTP id v25-20020a2e7a19000000b002c0196ce38fmr23575551ljc.1.1699354564263; Tue, 07 Nov 2023 02:56:04 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:03 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v3 03/20] riscv: add ISA extension parsing for scalar crypto Date: Tue, 7 Nov 2023 11:55:39 +0100 Message-ID: <20231107105556.517187-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Evan Green The Scalar Crypto specification defines Zk as a shorthand for the Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk, which are all shorthands for various other extensions. The detailed breakdown can be found in their dt-binding entries. Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing "zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk" should generate the following cpuinfo output: "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_z= kt" riscv_isa_ext_data grows a pair of new members, to permit setting the relevant bits for "bundled" extensions, both while parsing the ISA string and the new dedicated extension properties. Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Signed-off-by: Evan Green Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 16 ++++- arch/riscv/kernel/cpufeature.c | 115 ++++++++++++++++++++++++++------- 2 files changed, 107 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6fc51c1b34cf..69cc659cf65e 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -60,8 +60,20 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 +#define RISCV_ISA_EXT_ZBC 45 +#define RISCV_ISA_EXT_ZBKB 46 +#define RISCV_ISA_EXT_ZBKC 47 +#define RISCV_ISA_EXT_ZBKX 48 +#define RISCV_ISA_EXT_ZKND 49 +#define RISCV_ISA_EXT_ZKNE 50 +#define RISCV_ISA_EXT_ZKNH 51 +#define RISCV_ISA_EXT_ZKR 52 +#define RISCV_ISA_EXT_ZKSED 53 +#define RISCV_ISA_EXT_ZKSH 54 +#define RISCV_ISA_EXT_ZKT 55 =20 #define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_INVALID U32_MAX =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA @@ -79,6 +91,8 @@ struct riscv_isa_ext_data { const unsigned int id; const char *name; const char *property; + const unsigned int *subset_ext_ids; + const unsigned int subset_ext_size; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; @@ -89,7 +103,7 @@ unsigned long riscv_isa_extension_base(const unsigned lo= ng *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) =20 -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit); +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsi= gned int bit); #define riscv_isa_extension_available(isa_bitmap, ext) \ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e3803822ab5a..0d78791288da 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -68,7 +68,7 @@ EXPORT_SYMBOL_GPL(riscv_isa_extension_base); * * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. */ -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int = bit) +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsi= gned int bit) { const unsigned long *bmap =3D (isa_bitmap) ? isa_bitmap : riscv_isa; =20 @@ -100,17 +100,53 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_INVALID: + return false; } =20 return true; } =20 -#define __RISCV_ISA_EXT_DATA(_name, _id) { \ - .name =3D #_name, \ - .property =3D #_name, \ - .id =3D _id, \ +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) {= \ + .name =3D #_name, \ + .property =3D #_name, \ + .id =3D _id, \ + .subset_ext_ids =3D _subset_exts, \ + .subset_ext_size =3D _subset_exts_size \ } =20 +#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, N= ULL, 0) + +/* Used to declare pure "lasso" extension (Zk for instance) */ +#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SI= ZE(_bundled_exts)) + +static const unsigned int riscv_zk_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKT, +}; + +static const unsigned int riscv_zkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKNH, +}; + +static const unsigned int riscv_zks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -174,7 +210,21 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), @@ -187,6 +237,27 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); =20 +static void __init match_isa_ext(const struct riscv_isa_ext_data *ext, con= st char *name, + const char *name_end, struct riscv_isainfo *isainfo) +{ + if ((name_end - name =3D=3D strlen(ext->name)) && + !strncasecmp(name, ext->name, name_end - name)) { + /* + * If this is a bundle, enable all the ISA extensions that + * comprise the bundle. + */ + if (ext->subset_ext_size) { + for (int i =3D 0; i < ext->subset_ext_size; i++) { + if (riscv_isa_extension_check(ext->subset_ext_ids[i])) + set_bit(ext->subset_ext_ids[i], isainfo->isa); + } + } + + if (riscv_isa_extension_check(ext->id)) + set_bit(ext->id, isainfo->isa); + } +} + static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struc= t riscv_isainfo *isainfo, unsigned long *isa2hwcap, const char *isa) { @@ -318,14 +389,6 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc if (*isa =3D=3D '_') ++isa; =20 -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext =3D=3D strlen(name)) && \ - !strncasecmp(ext, name, strlen(name)) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - if (unlikely(ext_err)) continue; if (!ext_long) { @@ -337,10 +400,8 @@ static void __init riscv_parse_isa_string(unsigned lon= g *this_hwcap, struct risc } } else { for (int i =3D 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } -#undef SET_ISA_EXT_MAP } } =20 @@ -439,18 +500,26 @@ static int __init riscv_fill_hwcap_from_ext_list(unsi= gned long *isa2hwcap) } =20 for (int i =3D 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data ext =3D riscv_isa_ext[i]; + if (of_property_match_string(cpu_node, "riscv,isa-extensions", - riscv_isa_ext[i].property) < 0) + ext.property) < 0) continue; =20 - if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) - continue; + if (ext.subset_ext_size) { + for (int j =3D 0; j < ext.subset_ext_size; j++) { + if (riscv_isa_extension_check(ext.subset_ext_ids[i])) + set_bit(ext.subset_ext_ids[j], isainfo->isa); + } + } =20 - /* Only single letter extensions get set in hwcap */ - if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) - this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + if (riscv_isa_extension_check(ext.id)) { + set_bit(ext.id, isainfo->isa); =20 - set_bit(riscv_isa_ext[i].id, isainfo->isa); + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) + this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + } } =20 of_node_put(cpu_node); --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A743EC0018C for ; Tue, 7 Nov 2023 10:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233957AbjKGK4d (ORCPT ); Tue, 7 Nov 2023 05:56:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234022AbjKGK4O (ORCPT ); Tue, 7 Nov 2023 05:56:14 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5D64114 for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:04 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 04/20] riscv: hwprobe: add support for scalar crypto ISA extensions Date: Tue, 7 Nov 2023 11:55:40 +0100 Message-ID: <20231107105556.517187-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the following scalar crypto extensions through hwprobe: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/arch/riscv/hwprobe.rst | 27 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 9 +++++++++ arch/riscv/kernel/sys_riscv.c | 9 +++++++++ 3 files changed, 45 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index ecc0307c107e..b020b2d35a99 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -80,6 +80,33 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as de= fined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as + defined in version 1.0 of the Scalar Crypto ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined + in version 1.0 of the Scalar Crypto ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index dcef5c33c009..10bf543de3ce 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -30,6 +30,15 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZBC (1 << 6) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 9) +#define RISCV_HWPROBE_EXT_ZKND (1 << 10) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 12) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 14) +#define RISCV_HWPROBE_EXT_ZKT (1 << 15) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 382cd71129c6..bb44592707a5 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -163,6 +163,15 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); CHECK_ISA_EXT(ZBC); + CHECK_ISA_EXT(ZBKB); + CHECK_ISA_EXT(ZBKC); + CHECK_ISA_EXT(ZBKX); + CHECK_ISA_EXT(ZKND); + CHECK_ISA_EXT(ZKNE); + CHECK_ISA_EXT(ZKNH); + CHECK_ISA_EXT(ZKSED); + CHECK_ISA_EXT(ZKSH); + CHECK_ISA_EXT(ZKT); #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30744C4167D for ; Tue, 7 Nov 2023 10:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234233AbjKGK4U (ORCPT ); Tue, 7 Nov 2023 05:56:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234173AbjKGK4L (ORCPT ); Tue, 7 Nov 2023 05:56:11 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 879A3D79 for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:05 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 05/20] dt-bindings: riscv: add scalar crypto ISA extensions description Date: Tue, 7 Nov 2023 11:55:41 +0100 Message-ID: <20231107105556.517187-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for scalar crypto ISA extensions which can now be reported through hwprobe for userspace usage. These extensions are the following: - Zbkb - Zbkc - Zbkx - Zknd - Zkne - Zknh - Zkr - Zksed - Zksh - Zkt Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- .../devicetree/bindings/riscv/extensions.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c91ab0e46648..a89363ad653a 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -190,12 +190,89 @@ properties: multiplication as ratified at commit 6d33919 ("Merge pull requ= est #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitm= anip. =20 + - const: zbkb + description: + The standard Zbkb bitmanip instructions for cryptography as ra= tified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkc + description: + The standard Zbkc carry-less multiply instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zbkx + description: + The standard Zbkx crossbar permutation instructions as ratified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zbs description: | The standard Zbs bit-manipulation extension for single-bit instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zk + description: + The standard Zk Standard Scalar cryptography extension as rati= fied + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zkn + description: + The standard Zkn NIST algorithm suite extensions as ratified in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zknd + description: | + The standard Zknd for NIST suite: AES decryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkne + description: | + The standard Zkne for NIST suite: AES encryption instructions = as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zknh + description: | + The standard Zknh for NIST suite: hash function instructions as + ratified in version 1.0 of RISC-V Cryptography Extensions Volu= me I + specification. + + - const: zkr + description: + The standard Zkr entropy source extension as ratified in versi= on + 1.0 of RISC-V Cryptography Extensions Volume I specification. + + - const: zks + description: + The standard Zks ShangMi algorithm suite extensions as ratifie= d in + version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + + - const: zksed + description: | + The standard Zksed for ShangMi suite: SM4 block cipher instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zksh + description: | + The standard Zksh for ShangMi suite: SM3 hash function instruc= tions + as ratified in version 1.0 of RISC-V Cryptography Extensions + Volume I specification. + + - const: zkt + description: + The standard Zkt for data independent execution latency as rat= ified + in version 1.0 of RISC-V Cryptography Extensions Volume I + specification. + - const: zicbom description: The standard Zicbom extension for base cache management operat= ions as --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFBBC4332F for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:07 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 06/20] riscv: add ISA extension parsing for vector crypto Date: Tue, 7 Nov 2023 11:55:42 +0100 Message-ID: <20231107105556.517187-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing of some Zv* vector crypto ISA extensions that are mentioned in "RISC-V Cryptography Extensions Volume II" [1]. These ISA extensions are the following: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/hwcap.h | 14 ++++++- arch/riscv/kernel/cpufeature.c | 68 ++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 69cc659cf65e..556d1da02877 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -71,8 +71,18 @@ #define RISCV_ISA_EXT_ZKSED 53 #define RISCV_ISA_EXT_ZKSH 54 #define RISCV_ISA_EXT_ZKT 55 - -#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_ZVBB 56 +#define RISCV_ISA_EXT_ZVBC 57 +#define RISCV_ISA_EXT_ZVKB 58 +#define RISCV_ISA_EXT_ZVKG 59 +#define RISCV_ISA_EXT_ZVKNED 60 +#define RISCV_ISA_EXT_ZVKNHA 61 +#define RISCV_ISA_EXT_ZVKNHB 62 +#define RISCV_ISA_EXT_ZVKSED 63 +#define RISCV_ISA_EXT_ZVKSH 64 +#define RISCV_ISA_EXT_ZVKT 65 + +#define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX =20 #ifdef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0d78791288da..56570b838910 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -121,6 +121,10 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SI= ZE(_bundled_exts)) =20 +/* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ +#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + static const unsigned int riscv_zk_bundled_exts[] =3D { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -147,6 +151,54 @@ static const unsigned int riscv_zks_bundled_exts[] =3D= { RISCV_ISA_EXT_ZKSH }; =20 +#define RISCV_ISA_EXT_ZVKN \ + RISCV_ISA_EXT_ZVKNED, \ + RISCV_ISA_EXT_ZVKNHB, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvkn_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN +}; + +static const unsigned int riscv_zvknc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvkng_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKN, + RISCV_ISA_EXT_ZVKG +}; + +#define RISCV_ISA_EXT_ZVKS \ + RISCV_ISA_EXT_ZVKSED, \ + RISCV_ISA_EXT_ZVKSH, \ + RISCV_ISA_EXT_ZVKB, \ + RISCV_ISA_EXT_ZVKT + +static const unsigned int riscv_zvks_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS +}; + +static const unsigned int riscv_zvksc_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVBC +}; + +static const unsigned int riscv_zvksg_bundled_exts[] =3D { + RISCV_ISA_EXT_ZVKS, + RISCV_ISA_EXT_ZVKG +}; + +static const unsigned int riscv_zvbb_exts[] =3D { + RISCV_ISA_EXT_ZVKB +}; + +static const unsigned int riscv_zvknhb_exts[] =3D { + RISCV_ISA_EXT_ZVKNHA +}; + /* * The canonical order of ISA extension names in the ISA string is defined= in * chapter 27 of the unprivileged specification. @@ -225,6 +277,22 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), + __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), + __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), + __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), + __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), + __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), + __RISCV_ISA_EXT_SUPERSET(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_zvknhb_exts), + __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), + __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), + __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), + __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), + __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAE78C00A5A for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:08 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 07/20] riscv: hwprobe: export vector crypto ISA extensions Date: Tue, 7 Nov 2023 11:55:43 +0100 Message-ID: <20231107105556.517187-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zv* vector crypto ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Zvkn and Zvks are ommited since they are a superset of other extensions. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++ arch/riscv/kernel/sys_riscv.c | 13 ++++++++++++ 3 files changed, 53 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index b020b2d35a99..2183fa6d2fc1 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -107,6 +107,36 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as de= fined in version 1.0 of the Scalar Crypto ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported= as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 10bf543de3ce..1b85386f276b 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -39,6 +39,16 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZKSED (1 << 13) #define RISCV_HWPROBE_EXT_ZKSH (1 << 14) #define RISCV_HWPROBE_EXT_ZKT (1 << 15) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 16) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 17) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 21) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 22) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 23) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 24) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 25) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index bb44592707a5..8e1d26659e14 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -172,6 +172,19 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZKSED); CHECK_ISA_EXT(ZKSH); CHECK_ISA_EXT(ZKT); + + if (has_vector()) { + CHECK_ISA_EXT(ZVBB); + CHECK_ISA_EXT(ZVBC); + CHECK_ISA_EXT(ZVKB); + CHECK_ISA_EXT(ZVKG); + CHECK_ISA_EXT(ZVKNED); + CHECK_ISA_EXT(ZVKNHA); + CHECK_ISA_EXT(ZVKNHB); + CHECK_ISA_EXT(ZVKSED); + CHECK_ISA_EXT(ZVKSH); + CHECK_ISA_EXT(ZVKT); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A0E8C4332F for ; Tue, 7 Nov 2023 10:56:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234294AbjKGK4l (ORCPT ); Tue, 7 Nov 2023 05:56:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234092AbjKGK4Q (ORCPT ); Tue, 7 Nov 2023 05:56:16 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5878F11A for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:09 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v3 08/20] dt-bindings: riscv: add vector crypto ISA extensions description Date: Tue, 7 Nov 2023 11:55:44 +0100 Message-ID: <20231107105556.517187-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Zv* vector crypto extensions that were added in "RISC-V Cryptography Extensions Volume II" specificationi[1]: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. Link: https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a89363ad653a..b68edfd1fb43 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -335,5 +335,101 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: zvbb + description: + The standard Zvbb extension for vectored basic bit-manipulation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvbc + description: + The standard Zvbc extension for vectored carryless multiplicat= ion + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkb + description: + The standard Zvkb extension for vector cryptography bit-manipu= lation + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkg + description: + The standard Zvkg extension for vector GCM/GMAC instructions, = as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvkn + description: + The standard Zvkn extension for NIST algorithm suite instructi= ons, as + ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.a= doc") + of riscv-crypto. + + - const: zvknc + description: + The standard Zvknc extension for NIST algorithm suite with car= ryless + multiply instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkned + description: + The standard Zvkned extension for Vector AES block cipher + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkng + description: + The standard Zvkng extension for NIST algorithm suite with GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvknha + description: | + The standard Zvknha extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 only) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvknhb + description: | + The standard Zvknhb extension for NIST suite: vector SHA-2 sec= ure, + hash (SHA-256 and SHA-512) instructions, as ratified in commit + 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-cryp= to. + + - const: zvks + description: + The standard Zvks extension for ShangMi algorithm suite + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksc + description: + The standard Zvksc extension for ShangMi algorithm suite with + carryless multiplication instructions, as ratified in commit 5= 6ed795 + ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksed + description: | + The standard Zvksed extension for ShangMi suite: SM4 block cip= her + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvksg + description: + The standard Zvksg extension for ShangMi algorithm suite with = GCM + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + + - const: zvkt + description: + The standard Zvkt extension for vector data-independent execut= ion + latency, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + additionalProperties: true ... --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2497C4167D for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:11 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 09/20] riscv: add ISA extension parsing for Zfh/Zfh[min] Date: Tue, 7 Nov 2023 11:55:45 +0100 Message-ID: <20231107105556.517187-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zfh[min] ISA extensions[1]. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 556d1da02877..10ebd36f67e0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZVKSED 63 #define RISCV_ISA_EXT_ZVKSH 64 #define RISCV_ISA_EXT_ZVKT 65 +#define RISCV_ISA_EXT_ZFH 66 +#define RISCV_ISA_EXT_ZFHMIN 67 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 56570b838910..7c04c03e435f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -260,6 +260,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), + __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92DA4C4167D for ; Tue, 7 Nov 2023 10:56:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234304AbjKGK4o (ORCPT ); Tue, 7 Nov 2023 05:56:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234212AbjKGK4R (ORCPT ); Tue, 7 Nov 2023 05:56:17 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1376512A for ; Tue, 7 Nov 2023 02:56:14 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40837396b1eso3063335e9.1 for ; Tue, 07 Nov 2023 02:56:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354572; x=1699959372; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mpUSLH3BYgf/ktV7Sl3gBxkxzBrg1sZ+k5tb8/h2R/w=; b=DlFxVsLynYKCLmHoRkxR76Rxj+QHCLQClQjgyutPkl7OQiqe3c8HafHRo0+7GJQPR3 pnO3KMpMzwJ8+p2MCVXVu/DpH7+Q7UVTlRVBIrMY+BNJNYaEbHcF1ZGpttVC/FH/3hFt VtPlvJ4PaChiyVWKRKKOX4Fc7e4ri5j+py3ZZGc2f43U5OdZmx0lSa9/6NyhzaG3Vhlw PxeG3fUtzQ9bAIYyVusLNYkGirktLX5310u4MYqWEk/sfzQXHTz4ZgbulF+vxYKwwmWA 04Y/2PaniEXy7ILGiBrL9MWhKRDW+/+eSPlQhstmDi4z879gV/sd/Q9K8joDTNVjpSfW UrHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354572; x=1699959372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mpUSLH3BYgf/ktV7Sl3gBxkxzBrg1sZ+k5tb8/h2R/w=; b=RM+B9XPNupkQw9rgU+AmVieXjlolza7VPmapEaOCycgs1lofirW+6YR02rY0U6AjGv cqyfsLwuazWzzYb7BPmbSvnxEGuxYyuzn6NX5FGxxe/bSxKD5PTjLl63PBpD21ONcDtt s480u8OCapF1YP1cUw48tcZqRkESVrWBL632wU3Vw3umRMKORMKlQfKSl5MmvLv6MBpG GMrjCVSVJRA/BwYNdGFtkF8yZToqtLleKCBk0Wkusg7+tsRF5kwr3tYlDA+0rdraEZUZ fuWZqNyC5jyYNPEF52l7Tvtze1u43J15Wis0KHyalzAorW2hSEr8+GwUbB+grpVzUjbw 7cdg== X-Gm-Message-State: AOJu0Ywa+vwtRq6XlF+C0eN+L6pbJ4X/JJmcxtBpeNup/ldXfmd/Z9Jf yYsrKuXU0qbRcPBRckwd3H3dhg== X-Google-Smtp-Source: AGHT+IGHgM8P/GBImCVbhEYbBPs1ObGpHO7TgPjk8/ukbJajiGwUzvQhgmr/xEO8DsJ21Emp1pseuw== X-Received: by 2002:a05:600c:1c17:b0:405:4280:341d with SMTP id j23-20020a05600c1c1700b004054280341dmr24929672wms.4.1699354572285; Tue, 07 Nov 2023 02:56:12 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:12 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 10/20] riscv: hwprobe: export Zfh[min] ISA extensions Date: Tue, 7 Nov 2023 11:55:46 +0100 Message-ID: <20231107105556.517187-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfh[min] ISA extensions[1] through hwprobe only if FPU support is available. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2183fa6d2fc1..ce0490e3130c 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -137,6 +137,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume= II. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is sup= ported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 1b85386f276b..12680081c602 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -49,6 +49,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSED (1 << 23) #define RISCV_HWPROBE_EXT_ZVKSH (1 << 24) #define RISCV_HWPROBE_EXT_ZVKT (1 << 25) +#define RISCV_HWPROBE_EXT_ZFH (1 << 26) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 8e1d26659e14..486e053a0797 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pai= r, CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); } + + if (has_fpu()) { + CHECK_ISA_EXT(ZFH); + CHECK_ISA_EXT(ZFHMIN); + } #undef CHECK_ISA_EXT } =20 --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C598C4332F for ; Tue, 7 Nov 2023 10:56:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234306AbjKGK4r (ORCPT ); Tue, 7 Nov 2023 05:56:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234241AbjKGK4W (ORCPT ); Tue, 7 Nov 2023 05:56:22 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2012D57 for ; Tue, 7 Nov 2023 02:56:15 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9bf60bba6f8so165967966b.0 for ; Tue, 07 Nov 2023 02:56:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354574; x=1699959374; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K+noeIiO0ZzRdCBLgjz9J+sy56GBx1867ixAgWMD4Wc=; b=1wIith9BIdnPlLltM/62yqwKTVZcSImm4+ad2Gk0VDRpQe2WzCvLgT+Hr7usm7OxSz jk41Km8ltUuWCE51dGojhIp2PnB3+3h5T48M7DxyZaBZD5m6ohFmSfE8FryJ2qORZ9ko iM8/gj6pnR5A9H6KcwrlWhMefYGY3QCfYUcl3axE2UrISp77HH0atxKDB46GS8BQTnsF QsX8bOZJV0b1RqGC6plEWYzuA/Oiod+ZjMOqTacw62vWk1BplxOj6W/lMDLpJcrfzL4k eN487W+x+n9sc5MGPqrc2BIb2ZU/jiYBfDDsiAn5vPde8l7w1T4/8m9ATxXdzRSmtZko ruIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354574; x=1699959374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K+noeIiO0ZzRdCBLgjz9J+sy56GBx1867ixAgWMD4Wc=; b=ScjHEkNDoaijlOxC7R3vCKFo2VJj86/UQ5MP4loebRIxEyrSUFBVCQBy8+oCGCTXT3 JCzrIT7KlZe9W6gIU6wYC3fO6DdqoCS5bl8XLAJSk0gy1gajF9bxexx+zAC5ZkU7thDt WAfLpnpIOtYybyuCol4gtC8TC0ZlksNUVM8E8QXjA8kRUdzCaEmuCAOzdocFs+Wk5WFv FipD7jbSITloU/Aj6hJJDdCRLvSmlrnbhkJSD+6NreAbEfuMRAyPvckrp61bska7pLFd VnqiwrbEq4UuJ2JaJ0lc6lr/KIUN4H19Jtxc4B9/P5/tF6YpdJUvPZGYSC/t7FyeL/U5 b3DQ== X-Gm-Message-State: AOJu0Yx2jK/Y1Z1N5tV5vGR2cGenwE2W9YEQn9q0f+iLLwIxahh7js3R dXp19gqAqplMn3i9MJc4r+3DmA== X-Google-Smtp-Source: AGHT+IGQ52RAx3C3PSFQKflfCCfN+v4u5QXrEdDEyMd6Gzx8ZtOWMB3t8ixpUgsMGHhCAPNhRGbMJA== X-Received: by 2002:a17:907:6d02:b0:9c9:603c:407e with SMTP id sa2-20020a1709076d0200b009c9603c407emr28520448ejc.0.1699354573974; Tue, 07 Nov 2023 02:56:13 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:12 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v3 11/20] dt-bindings: riscv: add Zfh[min] ISA extensions description Date: Tue, 7 Nov 2023 11:55:47 +0100 Message-ID: <20231107105556.517187-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description of Zfh[min] ISA extensions[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index b68edfd1fb43..62b5fe40b4a3 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -214,6 +214,19 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfh + description: + The standard Zfh extension for 16-bit half-precision binary + floating-point instructions, as ratified in commit 64074bc ("U= pdate + version numbers for Zfh/Zfinx") of riscv-isa-manual. + + - const: zfhmin + description: + The standard Zfhmin extension which provides minimal support f= or + 16-bit half-precision binary floating-point instructions, as r= atified + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as rati= fied --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8116C4332F for ; Tue, 7 Nov 2023 10:56:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234239AbjKGK4v (ORCPT ); Tue, 7 Nov 2023 05:56:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234249AbjKGK4X (ORCPT ); Tue, 7 Nov 2023 05:56:23 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3AFED73 for ; Tue, 7 Nov 2023 02:56:16 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-40837396b1eso3063415e9.1 for ; Tue, 07 Nov 2023 02:56:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354575; x=1699959375; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aJyd1YBcb+U2PBneGSdwCeFg8Fe7xoja8XAVvgGr8QM=; b=kL4dRSDmheqW1rZa9Ma3GuG+hJghK/vLfPpPAmTPnPQNkc+v+PO+QBYBteB7FCABIW 4f/qF0/vmHTJ1g6cvFQXULenWdUxp+VJzkQnWeq1n+uncWDzbigRGwknYyxCZGn+0Z2G Y3/yQdSfRdsJ8lqDBJUfNIoRs7gCb+FesUP1K1Hbo0ov53pqvU6CiD8ztEtWwb/iSSPF JCEd8vN1AwG7Zr/INM0c94gTDcri5IBnaENuCqx/yxENbZNhg+DIiKChTv1OT8W37P+k J9uJLRKVHGKrkKwxLXuSJj2g3oQ7oZv4inwm3OZzl2o3Kl6EIUP+MaVAgNoAwEvncWq9 ERKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354575; x=1699959375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aJyd1YBcb+U2PBneGSdwCeFg8Fe7xoja8XAVvgGr8QM=; b=VsYi0Mwqb7hEFhiBERupqGtIjsRWunUIw+2PT9SDlcNE63IFPsBcZZP28IktjpAPxT OMVYC8k2lK9AeGueCHhIDLE2RGxfUG8+WL7Xc17zs/Czf8OAMQ5DsZ3zZRx+RZv2K+5c wF2meGZZSHeyHnYWUlynnrBgiXow6wSa54Cx3xqMT40+7GhmlVKaFGBS/nk+2UFJx83H bPvBi35sdZ6gVYBDSTLLMYnxFVlmesln8QnQaZYcXC1GtpJNf1789VBlKOlHRtJdqqgw XYnxgxjN8lj1nLpVlApwbyoA9dS0vJyq5VeKOV10mBlPYfcF3mg8nlJPzkRucznDF/p3 HU6Q== X-Gm-Message-State: AOJu0YyEZ/GHyx5lECCxJNcgyfrvrWKqtR8KTBqjhXl8iNoZMGAdZylv 5DNP0oNB5QxGWIcmoAfBN/5hXQ== X-Google-Smtp-Source: AGHT+IFwqzEm1CRJc3Tvln28fqzLrx5PcA3gU0DPHRFsH47EQLrWlkSUXHW5cbEtNQ1KO6g6dWi35Q== X-Received: by 2002:a05:600c:35d6:b0:404:7606:a871 with SMTP id r22-20020a05600c35d600b004047606a871mr24942179wmq.2.1699354574695; Tue, 07 Nov 2023 02:56:14 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:14 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 12/20] riscv: add ISA extension parsing for Zihintntl Date: Tue, 7 Nov 2023 11:55:48 +0100 Message-ID: <20231107105556.517187-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zihintntl ISA extension[1] that was ratified in commit 0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 10ebd36f67e0..5b57b24db60c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -83,6 +83,7 @@ #define RISCV_ISA_EXT_ZVKT 65 #define RISCV_ISA_EXT_ZFH 66 #define RISCV_ISA_EXT_ZFHMIN 67 +#define RISCV_ISA_EXT_ZIHINTNTL 68 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7c04c03e435f..baa8edfb0e6a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -258,6 +258,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 267C8C4332F for ; Tue, 7 Nov 2023 10:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234323AbjKGK4z (ORCPT ); Tue, 7 Nov 2023 05:56:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234259AbjKGK4X (ORCPT ); Tue, 7 Nov 2023 05:56:23 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E6F5D79 for ; Tue, 7 Nov 2023 02:56:18 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2c52407516bso12182561fa.1 for ; Tue, 07 Nov 2023 02:56:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354577; x=1699959377; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S4s/6qoHBJWx8IDkipxLTMx5qIdSuDP9Fhxnx/OaR4U=; b=vPmItZM7nGGK6tzGcRAfDMCs8+OzzYEq9jsUudufmqf1/Wu5Edle1cnt3fIZ0F6XRz HLtyB92zp8Ol8LNLrEmHEhxS63jSEpLZkLrVH8oY2EBcpzHun4F+OCvM+yZxi6FnpAnC fGCNLBNI6Ka0hhwfeQtBjkT7S8IhtB4nCeWQa46bCCaIY6wLTeJGpnYkm/EOX3DRa1jS f2SlStsC+PrN0/AoK3gkVFndmljVuCWeK9/R721y8YXbTkdbAK5pBoOouqEHTsRcILyn 6TF6creSbONg4plKxqYvYZpqOOBQ1M32FA2bITa91nEBIUKyicOA1gb2CvKHrM9HupcG 448w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354577; x=1699959377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S4s/6qoHBJWx8IDkipxLTMx5qIdSuDP9Fhxnx/OaR4U=; b=aMpj0kdUM2ab3EPRvr4Ndua20zvLgT6pIyg3uwMs2w6jQ1RIPBhoeJlZIkXM55DojM HU3qszouEXmWjN/m6Ht6R06pNNLpUDKv+zzMazTE8gW2Lq5aVPoNQsqzaQmJgjrQzD7c 9zuXdDRx5NT+hzLAWCMJUzFqHiebo9al5FN+0Lz6jXpsJlp9bwMQY+eawYKD6vILshwl TWfBfnhnZUn8NfEq3xMXevX38s2KnHEp7WtaZ3Udy2vVc2Pu2SqrnPUK8kK1qscESOdb Rq/lTPIvR4Vjgy+hDmm3z5LM/1ocSsP5GUv1GdPrkuwGZgBVOdihBLycBH0Jy8a+170I WH1Q== X-Gm-Message-State: AOJu0YxUYjxMEdcS0+iVMHegTgLBeUpT38lE4A7KZ4y+CAKJ0glc0dfY TvQ8ZRHXFRdm5xFXJRjsM+0+0A== X-Google-Smtp-Source: AGHT+IHavrKs5gCTfWWE/t+GviSN/fOuRjyg21bPxGHplb1KOZPOkEuhUgKCY8nRPYJZqATj3n1jgw== X-Received: by 2002:a2e:9f10:0:b0:2c5:6ab:b817 with SMTP id u16-20020a2e9f10000000b002c506abb817mr22837219ljk.5.1699354576498; Tue, 07 Nov 2023 02:56:16 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:15 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 13/20] riscv: hwprobe: export Zhintntl ISA extension Date: Tue, 7 Nov 2023 11:55:49 +0100 Message-ID: <20231107105556.517187-14-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zihintntl extension[1] through hwprobe. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index ce0490e3130c..2f37b26d27da 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -143,6 +143,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 = is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 12680081c602..36c8d073c987 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -51,6 +51,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKT (1 << 25) #define RISCV_HWPROBE_EXT_ZFH (1 << 26) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) +#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 486e053a0797..af2b01b0a5b6 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -172,6 +172,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZKSED); CHECK_ISA_EXT(ZKSH); CHECK_ISA_EXT(ZKT); + CHECK_ISA_EXT(ZIHINTNTL); =20 if (has_vector()) { CHECK_ISA_EXT(ZVBB); --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BED54C4332F for ; Tue, 7 Nov 2023 10:57:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234260AbjKGK5B (ORCPT ); Tue, 7 Nov 2023 05:57:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234289AbjKGK4l (ORCPT ); Tue, 7 Nov 2023 05:56:41 -0500 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F83A10CA for ; Tue, 7 Nov 2023 02:56:20 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2c5bacef31aso11257641fa.0 for ; Tue, 07 Nov 2023 02:56:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354578; x=1699959378; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c7aEHK12fdFG0G9p5Ar5H42P12VBS+xQqa4RJxPd+e8=; b=ayg+6gMMwQQN8hONtjI0gXlKN5//lxIaiLRMm3z+XI5pRcz5oRJPAjz3sZIAXu8rXG EG3qYcyQAm0xYIEjefLnvVxZqOXSDC8MpMGdoSV0BJgIb2LfES8eGOfpgEErMJEBzZ0I e032kyevBqe+1YzlyxscLmOiDAMpxlhyqitti2VbYsLaIV7Q3XXLO5tlhQTf1jnbJG1B l1l7P/s3dEOfKqrmdPjHEP0aCfY13ecCvQR/VCGdPKEPMF0dbr1h4hTLOI5nVCoQdMjK wArv8Hb29G5EFWxqr2vGAhmX0NX0sxZC+Qhw+Ixlne/zQ4T4l2bthpzLdhWJNhi9oezG ivXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354578; x=1699959378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7aEHK12fdFG0G9p5Ar5H42P12VBS+xQqa4RJxPd+e8=; b=QPXb2MduXpAM/HP55eSnsy7mpIZjCcpANp6YTRoCtsz9fMTiGWrsI+c43Sb6WYjqiz kyZHLM/kwm6Xo+OKDFOuq3baFIDyVBkYJq4rXEfHgHnfoZ1ajZ0vAvzOH678eY0oOv30 M8UcMmIHEqWbgZ1qeLa/3DnlFUvMNhq1j0+zSQgodyxqPEIDsn1kz8bdeM41RyJHI7+9 AAzmz1KCi2CmQN5xMaVeM6ReK/eW2MfFCqMN5a2SsbpUg9K7VvyhB1J9lMeIoMx5dX21 DKYX5/bZZtSqCEF0lfOU2j9/e6Eqy2vHu5Hjd63dWJpX9IytVzdjGoZYzzHy+crqoEfY uTaw== X-Gm-Message-State: AOJu0Ywd9JsxDPGYb08b9Er7oQ57FSzkcZqW8xDyVicBAowCMVFMoA94 nJvRM+iGx89sBg/AYi8pODMPzA== X-Google-Smtp-Source: AGHT+IG6riKUjiH4caHBP0UY8y2QJ6HnExEb8OSRHzEi1uOV2r19/bcFPMSaXYWd+67hvhTH5Nkmjw== X-Received: by 2002:a05:651c:1317:b0:2c5:36e:31ef with SMTP id u23-20020a05651c131700b002c5036e31efmr23580871lja.5.1699354578058; Tue, 07 Nov 2023 02:56:18 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:17 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v3 14/20] dt-bindings: riscv: add Zihintntl ISA extension description Date: Tue, 7 Nov 2023 11:55:50 +0100 Message-ID: <20231107105556.517187-15-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zihintntl ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 62b5fe40b4a3..c80774b518c9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -336,6 +336,12 @@ properties: The standard Zihintpause extension for pause hints, as ratifie= d in commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-ma= nual. =20 + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hin= ts, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + - const: zihpm description: The standard Zihpm extension for hardware performance counters= , as --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99988C4332F for ; Tue, 7 Nov 2023 10:57:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234370AbjKGK5H (ORCPT ); Tue, 7 Nov 2023 05:57:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234213AbjKGK44 (ORCPT ); Tue, 7 Nov 2023 05:56:56 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1796D78 for ; Tue, 7 Nov 2023 02:56:22 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c5bacef31aso11257771fa.0 for ; Tue, 07 Nov 2023 02:56:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354580; x=1699959380; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VpHOk3VsdqfpPenBw33m97LFdLmT8/1+lQVgF+3Qq2k=; b=WknoiwOdL03mnzofkGnOWECirg656GaXTK2JzbrQynYWpVDUl99fv0TqUpkPBeay69 9NwMy8QQYjXrEyx4N5dU4bk6zeRYLzZzjk1Y8QjLC5chbDTVTjySLqhzdmli/HFD0JhL DN7NnWhrVJQ8+wyyVZ1iJX1urTSoNMJ2OhH/ngoPui3Ys1/pNN1G8spsyvcdLYbx5z3P HzhyCmIW/FHAdNmeIE6uEdSpQznhRWX0V4LWv8p5fm7XWPfDNz4Sd5EZhzwmBRlMg32B bmIzX7Is0h3yBASnqbNdKBfnJ2Q2UaG7xlz14qdlbukrAMWBoVVL7THHc9K3+Styk5KW Bt0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354580; x=1699959380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VpHOk3VsdqfpPenBw33m97LFdLmT8/1+lQVgF+3Qq2k=; b=iqqRlMCf94zI05ibKi70Uft2XX4ANd8t8iXoF5AT7d4xfQGHd2S5F3DZ9Oht8YSh7r 3vW8Li/bRI880YNkAl2OdxmskPc1CXOK/CcZ4NNNV7p38vopb6pbiytVyNqsdP9qXfhQ ERiqZtN0KtkVcWPa/B0MvBApYUFf9fESD6Zunpe1KRWTz90IdwWJIBnTTUBFv9TDn/NS eFaSSVgZDGDD98wiJgH5m3KHTbKDftQ78P1d42+qxD8arxeTWV5lnFTXt5mXHuN6/O+1 qJeGN0pl9juMG3kHWhqlSDHphffbRg0Ph9mkwpCKbKg02hUGQQohunhpYIIg1QNpngq6 1/Jw== X-Gm-Message-State: AOJu0YzDhVbFGYPMvpUqBCs9mFlby/Ku1W5Vr45OzC9uebm8DlpTixUR DUDzaKAN9huhMl1F+Q5rafnvEQ== X-Google-Smtp-Source: AGHT+IE+q2UlEWc6Qe9yztVIb0UfK9b3Z8SW8kIF2An9w1ZlDSwjmA5V2PrJhbGY+LL9yCEavwTs1A== X-Received: by 2002:a2e:980e:0:b0:2bc:d505:2bf3 with SMTP id a14-20020a2e980e000000b002bcd5052bf3mr22410080ljj.1.1699354579680; Tue, 07 Nov 2023 02:56:19 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:18 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 15/20] riscv: add ISA extension parsing for Zvfh[min] Date: Tue, 7 Nov 2023 11:55:51 +0100 Message-ID: <20231107105556.517187-16-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zvfh[min] ISA extension[1] which were ratified in june 2023 around commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]") in riscv-v-spec[2]. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Link: https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5b57b24db60c..752be910e7c3 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -84,6 +84,8 @@ #define RISCV_ISA_EXT_ZFH 66 #define RISCV_ISA_EXT_ZFHMIN 67 #define RISCV_ISA_EXT_ZIHINTNTL 68 +#define RISCV_ISA_EXT_ZVFH 69 +#define RISCV_ISA_EXT_ZVFHMIN 70 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index baa8edfb0e6a..0b9d16ea71f1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -282,6 +282,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), + __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C57A3C4332F for ; Tue, 7 Nov 2023 10:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234284AbjKGK5Q (ORCPT ); Tue, 7 Nov 2023 05:57:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234332AbjKGK46 (ORCPT ); Tue, 7 Nov 2023 05:56:58 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE1F710DD for ; Tue, 7 Nov 2023 02:56:23 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32f9baca5bcso817465f8f.0 for ; Tue, 07 Nov 2023 02:56:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354581; x=1699959381; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V5SlhQ+MFK/oE1hG84P6kssLtuGPrTemJS5B/ituwJs=; b=HuLzHD5+NUplFSRSEigRYCAeD0v0cEK2NPID/6oGjjEmaPDUHskQwVpB+cWEvkFNFN NLIXXtPCTYKJCr+iwcVISdLgyRoD0Ghc5Y2NxjsB4ERA1RuGWaxrgSEjhxJWZzcjOVgl epmv7DDwCUkdjvpTYcao+ZD/WCzd8c6rsMgyv97wph253i5bbm5UPKrZrBjBff97WAJ9 h6Gue5A1/boJ6p9HATQZo5uXfW53Wm9NjqMb/tTW5dwlygNm6B48cSqj1DxcosSFuZDq 5A7M8z5EsZSF5ssB7cD5fLPSiKSd7DBa32/fq1epkaUuLNBeewtAwqfJkmLsMF7rp3XE 1XGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354581; x=1699959381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V5SlhQ+MFK/oE1hG84P6kssLtuGPrTemJS5B/ituwJs=; b=A1DmjBq7PuTtHXRa2Tjbe1y4LjTXVqPmar+KKfIgSLnqu8hBa2SmVqS6gpZSvX8kQP kSyw3bU8HrE6/xCBPz+qd7ZP//+qoF0hWIyY9jxvROsLp0T2tyU+tLcNLE/g8RzOmqAq w5uDDRu9gExsjQUw49H/ezyUnIQpDVgKkcH58FSdKJnr9RDTo+fA4wmrS2MCUyT/ZZQJ zLgKPiiIaQmVTpHtWB2gn+Jjds+32fHFpc41XbXv0yWclydN8+qY9KP8vkF+ygL2zXX8 QDf9XdLSyL31kKFv1zdr+L76yhHcfgo69Gk3ZSfH3kqAe3kjS4/gwzuVUDPxms52J7aM iR7w== X-Gm-Message-State: AOJu0Yz91LI1sopBI8wM7tEIvHyHe24FkdPmOlDJlYR6E2I59X5c6Q1M ZJhaFLL3AOQMaO7eQT3Ewu8tyA== X-Google-Smtp-Source: AGHT+IFQS7qfkMNRtAKpq/tiaOzmGYA+PKb/n54XAFPfjBLLUBdHDw7kelXyOwVBWWtsxlUnnASLNQ== X-Received: by 2002:a05:600c:ac3:b0:404:72f9:d59a with SMTP id c3-20020a05600c0ac300b0040472f9d59amr26109516wmr.0.1699354580425; Tue, 07 Nov 2023 02:56:20 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:20 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 16/20] riscv: hwprobe: export Zvfh[min] ISA extensions Date: Tue, 7 Nov 2023 11:55:52 +0100 Message-ID: <20231107105556.517187-17-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zvfh[min] ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 8 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2f37b26d27da..2a2fe4b026e7 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -146,6 +146,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension versio= n 1.0 is supported as defined in the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is support= ed as + defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c + ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 36c8d073c987..5124327b70ff 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -52,6 +52,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFH (1 << 26) #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) +#define RISCV_HWPROBE_EXT_ZVFH (1 << 29) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index af2b01b0a5b6..3cd5d42ae01f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSED); CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); + CHECK_ISA_EXT(ZVFH); + CHECK_ISA_EXT(ZVFHMIN); } =20 if (has_fpu()) { --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A0A9C4332F for ; Tue, 7 Nov 2023 10:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234311AbjKGK5T (ORCPT ); Tue, 7 Nov 2023 05:57:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234271AbjKGK46 (ORCPT ); Tue, 7 Nov 2023 05:56:58 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B19CA10E9 for ; Tue, 7 Nov 2023 02:56:24 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-408434ce195so10593775e9.0 for ; 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([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:20 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz , Conor Dooley Subject: [PATCH v3 17/20] dt-bindings: riscv: add Zvfh[min] ISA extension description Date: Tue, 7 Nov 2023 11:55:53 +0100 Message-ID: <20231107105556.517187-18-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for Zvfh[min] ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index c80774b518c9..87c7e3608217 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -366,6 +366,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. =20 + - const: zvfh + description: + The standard Zvfh extension for vectored half-precision + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + + - const: zvfhmin + description: + The standard Zvfhmin extension for vectored minimal half-preci= sion + floating-point instructions, as ratified in commit e2ccd05 + ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. + - const: zvkb description: The standard Zvkb extension for vector cryptography bit-manipu= lation --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D801C4332F for ; Tue, 7 Nov 2023 10:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234391AbjKGK5Z (ORCPT ); Tue, 7 Nov 2023 05:57:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234309AbjKGK5C (ORCPT ); Tue, 7 Nov 2023 05:57:02 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C54910FD for ; Tue, 7 Nov 2023 02:56:25 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50799fe3422so1178723e87.1 for ; Tue, 07 Nov 2023 02:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354583; x=1699959383; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hPj7UJhNk4bEKBTXmbiQszNoP65XhPNjIiphPr/bFIg=; b=MP36DyflZOKAPqiiUO4zOTIblkY+I3R4Mx6kqJp51cjNnh2IqwlrKCfjDMsDJ7kEb5 5itall+Eq0m98N2YBS1nXxsuGQoNb+1+RUkrxmI3xYCil+xuyBnEaJOX45o7EQa/lJDx 9hbi94GfOavnhEYLeamIWM5e2PetTy86ozGev662HSLrK0l3wnr6CSDBDffq8T8N87JL SVnONHKpNLfCxRgu9p4wgVBCxvhOfXLcpSYOzUJZvl725+MjEqFyDZbbnx0/9NDDdvQA z5RToGxqRAieqQ35yFlbXP56X23Xqf0f3BjzuymXt/qAs+/cN9lzh/RhFJVvDPQqH/mD +D3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354583; x=1699959383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hPj7UJhNk4bEKBTXmbiQszNoP65XhPNjIiphPr/bFIg=; b=brPkfGr+Z4qb/Tnrugowrw4FXUKoFymQHM0CO4RApOxywSgMM3wod3l8oHtcRhEOnD sLERGVmf/g4cX40WObZj2CejNu0cQXiZ/gmYS0CV4IQAa73KI1SCXUzQzCU6xSMomU0E BSXZntIC91IKdmT7ze8qWInI6EhezwlsKptCWTphf2BeXrm/bObPypItE3RsXnX/eaiM VxkQSuMelG0zdEOu+ej+K2fv7fVBlP2XI8xndH7skwt0sqZOSzjgEWGH3Ux6uZnWopZg lEkzSq0ZHS4Q58YMWyilxpRbMAxknbErZRl9cCP0N0JyBjFPuhq1vDHI+MZClpUWb75P 3pmg== X-Gm-Message-State: AOJu0YyRKPpkIlwkpwbYITpX4ie8zed0PJaMdHHlpmJuDSMofMsURnPA GosHvUu+GCv1Or3XoJC1JO5lNQ== X-Google-Smtp-Source: AGHT+IGRA2Jq7n60JiFQFoG9YMwZlINwiDybS35zq6fryGJBSKL1K+FHC6LMZd0w5ZY6D/nx95IeyA== X-Received: by 2002:a05:6512:3196:b0:502:af44:21c2 with SMTP id i22-20020a056512319600b00502af4421c2mr23556282lfe.5.1699354583017; Tue, 07 Nov 2023 02:56:23 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:22 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 18/20] riscv: add ISA extension parsing for Zfa Date: Tue, 7 Nov 2023 11:55:54 +0100 Message-ID: <20231107105556.517187-19-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add parsing for Zfa ISA extension [1] which were ratified in commit 056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2]. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 752be910e7c3..3fceae60ca39 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZIHINTNTL 68 #define RISCV_ISA_EXT_ZVFH 69 #define RISCV_ISA_EXT_ZVFHMIN 70 +#define RISCV_ISA_EXT_ZFA 71 =20 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0b9d16ea71f1..d58c8e9ceb05 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08F27C4332F for ; Tue, 7 Nov 2023 10:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234363AbjKGK52 (ORCPT ); Tue, 7 Nov 2023 05:57:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234351AbjKGK5C (ORCPT ); Tue, 7 Nov 2023 05:57:02 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF004170B for ; Tue, 7 Nov 2023 02:56:26 -0800 (PST) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-9bf0bee9f2fso173873066b.1 for ; Tue, 07 Nov 2023 02:56:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354584; x=1699959384; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PQVPAaYHkpM0GEJ73m22K8qqx/erlq7lj5m1X7f1ukE=; b=GjRjIi6Sv0MkxFa6Gva3AkOyRO23adoWjNZNL7rnSjqaDj2XU9+4YUn4qR9VcfG4CF CCviy85my/Zd3XoPs+ULsx/+glkHYHDtuIuI4nE59dP2hiBGso2Sh5Sw0bFmIyNvMcPF gOQaF9lO9BTDt3qKZtt7dE0dSEaTQ5v+3qpeREuzy3TabgNoHyrYo9/FvaUNVlgM+Y5c 0aCxGgE9nI68/+E7brLL1kt+8F+NrNokul0m8wutHFQRP7ROvS0tuImjkYfLn1RA5B8H 3+YITbyThtbcvyKqqma26JeePZIRaN83wV9C7iqEq0AU4FL2f2UZyXuJZhyrngFF2H6S K4EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354584; x=1699959384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQVPAaYHkpM0GEJ73m22K8qqx/erlq7lj5m1X7f1ukE=; b=AqqhhP3Czeodn/eGAoMlV5S44+opGFq+qtaA6lXnrusnS/pCFv04GWPCFdYDUYYkz2 vF5Z29DijF2ecIptTbSbBLr+jjqqpCcCy1e4TG9Ote1hTkU90/09cXZZFuhAeHdHYoVp I3qkscy7aIXzNOx9oL6uFDLa2m2Mmeyy1qE7NYqU8dAR4cq4DnxuZzk4qcb8EOfFzQ6z WXDdcnC3R9QAesRYxHQXuiuQNxhXmgoOvI+Z1upxJXppyA3RUKyu9nKeshLwQbW6oaBj PVMVddgmlsioLvjFXT8xrLEpqBcp2zDwDsWAKQ6TKwXZtSNPuqiK45MKnwkiDXKDclrV hMAA== X-Gm-Message-State: AOJu0Yyx2vyMJFDD7MhqQugNEHDJKUAFMTiYEnvDdo1H5uBz53pchOhh bsVByQ3jfFGPsCDTYA9Ayml88g== X-Google-Smtp-Source: AGHT+IGj0yQcu+DGOcyOjDKINIocvRDdaol8XKw87jQoMj8DVyz/EpNBoI48Bn4wmnkpdAazd54/WA== X-Received: by 2002:a17:907:86aa:b0:9bf:b83c:5efd with SMTP id qa42-20020a17090786aa00b009bfb83c5efdmr24912005ejc.3.1699354584016; Tue, 07 Nov 2023 02:56:24 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:23 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 19/20] riscv: hwprobe: export Zfa ISA extension Date: Tue, 7 Nov 2023 11:55:55 +0100 Message-ID: <20231107105556.517187-20-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export Zfa ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Evan Green --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2a2fe4b026e7..a53fbc076d7e 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -154,6 +154,10 @@ The following keys are defined: defined in the RISC-V Vector manual starting from commit e2ccd0548d= 6c ("Remove draft warnings from Zvfh[min]"). =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as + defined in the RISC-V ISA manual starting from commit 056b6ff467c7 + ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 5124327b70ff..71f6cda52c4c 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -54,6 +54,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) #define RISCV_HWPROBE_EXT_ZVFH (1 << 29) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) +#define RISCV_HWPROBE_EXT_ZFA (1 << 31) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 3cd5d42ae01f..dedfe3c6a37b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -192,6 +192,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) { CHECK_ISA_EXT(ZFH); CHECK_ISA_EXT(ZFHMIN); + CHECK_ISA_EXT(ZFA); } #undef CHECK_ISA_EXT } --=20 2.42.0 From nobody Wed Dec 31 04:51:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E867EC4332F for ; Tue, 7 Nov 2023 10:57:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233813AbjKGK5b (ORCPT ); Tue, 7 Nov 2023 05:57:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234257AbjKGK5I (ORCPT ); Tue, 7 Nov 2023 05:57:08 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C97381720 for ; Tue, 7 Nov 2023 02:56:28 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-32fa4183535so811527f8f.1 for ; Tue, 07 Nov 2023 02:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1699354586; x=1699959386; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hiqFYUrrovnf1rhzBHvSluIgSBMGKUT9Q2F8cmlGclI=; b=qkxdtbQucEK7DLbiv1cKdTpCrLREePIFWimgYLnxfcHCSbA7Hw/4RlMhTwX/1y8H3i 2AiDmSFI5R39zutNt6ytF7rgteIp6ZWOcZSOkBaIw2Yft/iUbjHP5yYW0OrFlOl+OhmD qj/HHvD5wAp/Tg5wI6GLNdwgE09YsQ5v1vCByiqUjqJjY06RVKGCfYkpAvVYZSUP/ccp DvkUxcUGFC3nLlqONCqce/kgc2zhXkFw71pd2axoIKSvio7w0nO9p5mcvIRaSWF4Oayv cqw5JLEsEUKTgB4Xrr0sBDAjMmWNXO5X69EVzHR7Dihj2OnZIXZUHCQ3vAgHPSGM/hmZ cPyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699354586; x=1699959386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hiqFYUrrovnf1rhzBHvSluIgSBMGKUT9Q2F8cmlGclI=; b=w8rgIExmVNNCQkJHu7aG7+HJgaw3NX2pXy2i0lasL/qL2O520sTskVX6MhB8RU8a0V dTK8ZK5iIL41HqkqLWZtrFC7PwznmsFlHf/34xV8JvHBUCEPCaGOvEiCtaWZFdYwzaTs 18nt/x0CZWoYZXyQk+WeNAuJ/gIVFc1/2ZHK8hSpU/96nYrRrPU+MMgCMNe7j1dWbYW6 IuTXUOegCiTlteZVejkw7JO6Za2OcMQfupqph692yni3Ncsq50HGho8r0Lp9OwCGbGvw tK6ni6gRlgj1dU16Nk/5lqlzUn4CZLkzj1WbzQOZlILaJ4KSrxOvz0UXpITeS/ycAI9L zIzg== X-Gm-Message-State: AOJu0Yx9gXE5YW+aLW9akK2CwRJCmT11yBAnYsQY5zVnrBvLvr/T/0xo GYHHxKHV9SgiM9cFW91ntGezqQ== X-Google-Smtp-Source: AGHT+IF7Zo2YtACLiPHwQ6dLVhxCBp4VHRs60nrkUPyWwGQZ1utTTeaxqjcqGnJKdNMWHeSZvxGiKQ== X-Received: by 2002:a05:600c:3b91:b0:407:52f0:b01a with SMTP id n17-20020a05600c3b9100b0040752f0b01amr26054980wms.2.1699354585803; Tue, 07 Nov 2023 02:56:25 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7db3:bdd9:4cab:2ee3]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c501e00b00405442edc69sm15396853wmr.14.2023.11.07.02.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 02:56:24 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v3 20/20] dt-bindings: riscv: add Zfa ISA extension description Date: Tue, 7 Nov 2023 11:55:56 +0100 Message-ID: <20231107105556.517187-21-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231107105556.517187-1-cleger@rivosinc.com> References: <20231107105556.517187-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add description for the Zfa ISA extension[1] which can now be reported through hwprobe for userspace usage. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/vie= w [1] Signed-off-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 87c7e3608217..dcba5380f923 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -214,6 +214,12 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zfa + description: + The standard Zfa extension for additional floating point + instructions, as ratified in commit 056b6ff ("Zfa is ratified"= ) of + riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary --=20 2.42.0