From nobody Wed Dec 31 09:04:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B6DAC4167D for ; Mon, 6 Nov 2023 08:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231373AbjKFI44 (ORCPT ); Mon, 6 Nov 2023 03:56:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231285AbjKFI4x (ORCPT ); Mon, 6 Nov 2023 03:56:53 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66388E1; Mon, 6 Nov 2023 00:56:11 -0800 (PST) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 6 Nov 2023 16:56:08 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V6 1/4] dt-bindings: clock: add Amlogic C3 PLL clock controller bindings Date: Mon, 6 Nov 2023 16:55:51 +0800 Message-ID: <20231106085554.3237511-2-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> References: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.98.11.200] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the PLL clock controller dt-bindings for Amlogic C3 SoC family. Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++ .../dt-bindings/clock/amlogic,c3-pll-clkc.h | 44 ++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-= clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml new file mode 100644 index 000000000000..9ca047698045 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 Serials PLL Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,c3-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input Top pll + - description: input MCLK pll + + clock-names: + items: + - const: top + - const: mpll + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,c3-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&clkc_periphs 0>, + <&clkc_periphs 1>; + clock-names =3D "top", "mpll"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-b= indings/clock/amlogic,c3-pll-clkc.h new file mode 100644 index 000000000000..60df483629ed --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H + +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_50M_EN 2 +#define CLKID_FCLK_50M 3 +#define CLKID_FCLK_DIV2_DIV 4 +#define CLKID_FCLK_DIV2 5 +#define CLKID_FCLK_DIV2P5_DIV 6 +#define CLKID_FCLK_DIV2P5 7 +#define CLKID_FCLK_DIV3_DIV 8 +#define CLKID_FCLK_DIV3 9 +#define CLKID_FCLK_DIV4_DIV 10 +#define CLKID_FCLK_DIV4 11 +#define CLKID_FCLK_DIV5_DIV 12 +#define CLKID_FCLK_DIV5 13 +#define CLKID_FCLK_DIV7_DIV 14 +#define CLKID_FCLK_DIV7 15 +#define CLKID_GP0_PLL_DCO 16 +#define CLKID_GP0_PLL 17 +#define CLKID_GP1_PLL_DCO 18 +#define CLKID_GP1_PLL 19 +#define CLKID_HIFI_PLL_DCO 20 +#define CLKID_HIFI_PLL 21 +#define CLKID_MCLK_PLL_DCO 22 +#define CLKID_MCLK_PLL_OD 23 +#define CLKID_MCLK_PLL 24 +#define CLKID_MCLK0_SEL 25 +#define CLKID_MCLK0_SEL_EN 26 +#define CLKID_MCLK0_DIV 27 +#define CLKID_MCLK0 28 +#define CLKID_MCLK1_SEL 29 +#define CLKID_MCLK1_SEL_EN 30 +#define CLKID_MCLK1_DIV 31 +#define CLKID_MCLK1 32 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */ --=20 2.39.2 From nobody Wed Dec 31 09:04:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91586C4167D for ; Mon, 6 Nov 2023 08:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231539AbjKFI5N (ORCPT ); Mon, 6 Nov 2023 03:57:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231426AbjKFI5D (ORCPT ); Mon, 6 Nov 2023 03:57:03 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D87DCC; Mon, 6 Nov 2023 00:56:13 -0800 (PST) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 6 Nov 2023 16:56:10 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V6 2/4] dt-bindings: clock: add Amlogic C3 peripherals clock controller bindings Date: Mon, 6 Nov 2023 16:55:52 +0800 Message-ID: <20231106085554.3237511-3-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> References: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.98.11.200] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the peripherals clock controller dt-bindings for Amlogic C3 SoC family Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- .../clock/amlogic,c3-peripherals-clkc.yaml | 104 ++++++++ .../clock/amlogic,c3-peripherals-clkc.h | 237 ++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peri= pherals-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-peripherals= -clkc.yaml new file mode 100644 index 000000000000..af1807dfa94a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.y= aml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic C3 Serials Peripheral Clock Controller + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Xianwei Zhao + - Chuan Liu + +properties: + compatible: + const: amlogic,c3-peripherals-clkc + + reg: + maxItems: 1 + + clocks: + minItems: 12 + items: + - description: input oscillator (usually at 24MHz) + - description: input oscillator (usually at 32KHz) + - description: input Fix PLL + - description: input Fclk div 2 + - description: input Fclk div 2p5 + - description: input Fclk div 3 + - description: input Fclk div 4 + - description: input Fclk div 5 + - description: input Fclk div 7 + - description: input gp0 pll + - description: input gp1 pll + - description: input hifi pll + - description: input pad clock for rtc_clk (optional) + + clock-names: + minItems: 12 + items: + - const: xtal_24m + - const: xtal_32k + - const: fix + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: gp0 + - const: gp1 + - const: hifi + - const: pad + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@0 { + compatible =3D "amlogic,c3-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x49c>; + #clock-cells =3D <1>; + clocks =3D <&xtal_24m>, + <&xtal_32k>, + <&clkc_pll 1>, + <&clkc_pll 5>, + <&clkc_pll 7>, + <&clkc_pll 9>, + <&clkc_pll 11>, + <&clkc_pll 13>, + <&clkc_pll 15>, + <&clkc_pll 17>, + <&clkc_pll 19>, + <&clkc_pll 21>; + clock-names =3D "xtal_24m", + "xtal_32k", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "gp0", + "gp1", + "hifi"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,c3-peripherals-clkc.h new file mode 100644 index 000000000000..0175d8b9b32b --- /dev/null +++ b/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H + +#define CLKID_PLL_SRC 0 +#define CLKID_MCLK_PLL_SRC 1 +#define CLKID_DDR_PLL_SRC 2 +#define CLKID_DDR_PHY_SRC 3 +#define CLKID_USB_PLL_SRC 4 +#define CLKID_MIPI_ISP_VOUT_SRC 5 +#define CLKID_USB_CTRL_SRC 6 +#define CLKID_ETH_PLL_SRC 7 +#define CLKID_CTS_OSC_SRC 8 +#define CLKID_RTC_XTAL_CLKIN 9 +#define CLKID_RTC_32K_DIV 10 +#define CLKID_RTC_32K_MUX 11 +#define CLKID_RTC_32K 12 +#define CLKID_RTC_CLK 13 +#define CLKID_SYS_A_SEL 14 +#define CLKID_SYS_A_DIV 15 +#define CLKID_SYS_A 16 +#define CLKID_SYS_B_SEL 17 +#define CLKID_SYS_B_DIV 18 +#define CLKID_SYS_B 19 +#define CLKID_SYS_CLK 20 +#define CLKID_AXI_A_SEL 21 +#define CLKID_AXI_A_DIV 22 +#define CLKID_AXI_A 23 +#define CLKID_AXI_B_SEL 24 +#define CLKID_AXI_B_DIV 25 +#define CLKID_AXI_B 26 +#define CLKID_AXI_CLK 27 +#define CLKID_SYS_RESET_CTRL 28 +#define CLKID_SYS_PWR_CTRL 29 +#define CLKID_SYS_PAD_CTRL 30 +#define CLKID_SYS_CTRL 31 +#define CLKID_SYS_TS_PLL 32 +#define CLKID_SYS_DEV_ARB 33 +#define CLKID_SYS_MMC_PCLK 34 +#define CLKID_SYS_CAPU 35 +#define CLKID_SYS_CPU_CTRL 36 +#define CLKID_SYS_JTAG_CTRL 37 +#define CLKID_SYS_IR_CTRL 38 +#define CLKID_SYS_IRQ_CTRL 39 +#define CLKID_SYS_MSR_CLK 40 +#define CLKID_SYS_ROM 41 +#define CLKID_SYS_UART_F 42 +#define CLKID_SYS_CPU_ARB 43 +#define CLKID_SYS_RSA 44 +#define CLKID_SYS_SAR_ADC 45 +#define CLKID_SYS_STARTUP 46 +#define CLKID_SYS_SECURE 47 +#define CLKID_SYS_SPIFC 48 +#define CLKID_SYS_NNA 49 +#define CLKID_SYS_ETH_MAC 50 +#define CLKID_SYS_GIC 51 +#define CLKID_SYS_RAMA 52 +#define CLKID_SYS_BIG_NIC 53 +#define CLKID_SYS_RAMB 54 +#define CLKID_SYS_AUDIO_PCLK 55 +#define CLKID_SYS_PWM_KL 56 +#define CLKID_SYS_PWM_IJ 57 +#define CLKID_SYS_USB 58 +#define CLKID_SYS_SD_EMMC_A 59 +#define CLKID_SYS_SD_EMMC_C 60 +#define CLKID_SYS_PWM_AB 61 +#define CLKID_SYS_PWM_CD 62 +#define CLKID_SYS_PWM_EF 63 +#define CLKID_SYS_PWM_GH 64 +#define CLKID_SYS_SPICC_1 65 +#define CLKID_SYS_SPICC_0 66 +#define CLKID_SYS_UART_A 67 +#define CLKID_SYS_UART_B 68 +#define CLKID_SYS_UART_C 69 +#define CLKID_SYS_UART_D 70 +#define CLKID_SYS_UART_E 71 +#define CLKID_SYS_I2C_M_A 72 +#define CLKID_SYS_I2C_M_B 73 +#define CLKID_SYS_I2C_M_C 74 +#define CLKID_SYS_I2C_M_D 75 +#define CLKID_SYS_I2S_S_A 76 +#define CLKID_SYS_RTC 77 +#define CLKID_SYS_GE2D 78 +#define CLKID_SYS_ISP 79 +#define CLKID_SYS_GPV_ISP_NIC 80 +#define CLKID_SYS_GPV_CVE_NIC 81 +#define CLKID_SYS_MIPI_DSI_HOST 82 +#define CLKID_SYS_MIPI_DSI_PHY 83 +#define CLKID_SYS_ETH_PHY 84 +#define CLKID_SYS_ACODEC 85 +#define CLKID_SYS_DWAP 86 +#define CLKID_SYS_DOS 87 +#define CLKID_SYS_CVE 88 +#define CLKID_SYS_VOUT 89 +#define CLKID_SYS_VC9000E 90 +#define CLKID_SYS_PWM_MN 91 +#define CLKID_SYS_SD_EMMC_B 92 +#define CLKID_AXI_SYS_NIC 93 +#define CLKID_AXI_ISP_NIC 94 +#define CLKID_AXI_CVE_NIC 95 +#define CLKID_AXI_RAMB 96 +#define CLKID_AXI_RAMA 97 +#define CLKID_AXI_CPU_DMC 98 +#define CLKID_AXI_NIC 99 +#define CLKID_AXI_DMA 100 +#define CLKID_AXI_MUX_NIC 101 +#define CLKID_AXI_CAPU 102 +#define CLKID_AXI_CVE 103 +#define CLKID_AXI_DEV1_DMC 104 +#define CLKID_AXI_DEV0_DMC 105 +#define CLKID_AXI_DSP_DMC 106 +#define CLKID_12_24M_IN 107 +#define CLKID_12M_24M 108 +#define CLKID_FCLK_25M_DIV 109 +#define CLKID_FCLK_25M 110 +#define CLKID_GEN_SEL 111 +#define CLKID_GEN_DIV 112 +#define CLKID_GEN 113 +#define CLKID_SARADC_SEL 114 +#define CLKID_SARADC_DIV 115 +#define CLKID_SARADC 116 +#define CLKID_PWM_A_SEL 117 +#define CLKID_PWM_A_DIV 118 +#define CLKID_PWM_A 119 +#define CLKID_PWM_B_SEL 120 +#define CLKID_PWM_B_DIV 121 +#define CLKID_PWM_B 122 +#define CLKID_PWM_C_SEL 123 +#define CLKID_PWM_C_DIV 124 +#define CLKID_PWM_C 125 +#define CLKID_PWM_D_SEL 126 +#define CLKID_PWM_D_DIV 127 +#define CLKID_PWM_D 128 +#define CLKID_PWM_E_SEL 129 +#define CLKID_PWM_E_DIV 130 +#define CLKID_PWM_E 131 +#define CLKID_PWM_F_SEL 132 +#define CLKID_PWM_F_DIV 133 +#define CLKID_PWM_F 134 +#define CLKID_PWM_G_SEL 135 +#define CLKID_PWM_G_DIV 136 +#define CLKID_PWM_G 137 +#define CLKID_PWM_H_SEL 138 +#define CLKID_PWM_H_DIV 139 +#define CLKID_PWM_H 140 +#define CLKID_PWM_I_SEL 141 +#define CLKID_PWM_I_DIV 142 +#define CLKID_PWM_I 143 +#define CLKID_PWM_J_SEL 144 +#define CLKID_PWM_J_DIV 145 +#define CLKID_PWM_J 146 +#define CLKID_PWM_K_SEL 147 +#define CLKID_PWM_K_DIV 148 +#define CLKID_PWM_K 149 +#define CLKID_PWM_L_SEL 150 +#define CLKID_PWM_L_DIV 151 +#define CLKID_PWM_L 152 +#define CLKID_PWM_M_SEL 153 +#define CLKID_PWM_M_DIV 154 +#define CLKID_PWM_M 155 +#define CLKID_PWM_N_SEL 156 +#define CLKID_PWM_N_DIV 157 +#define CLKID_PWM_N 158 +#define CLKID_SPICC_A_SEL 159 +#define CLKID_SPICC_A_DIV 160 +#define CLKID_SPICC_A 161 +#define CLKID_SPICC_B_SEL 162 +#define CLKID_SPICC_B_DIV 163 +#define CLKID_SPICC_B 164 +#define CLKID_SPIFC_SEL 165 +#define CLKID_SPIFC_DIV 166 +#define CLKID_SPIFC 167 +#define CLKID_SD_EMMC_A_SEL 168 +#define CLKID_SD_EMMC_A_DIV 169 +#define CLKID_SD_EMMC_A 170 +#define CLKID_SD_EMMC_B_SEL 171 +#define CLKID_SD_EMMC_B_DIV 172 +#define CLKID_SD_EMMC_B 173 +#define CLKID_SD_EMMC_C_SEL 174 +#define CLKID_SD_EMMC_C_DIV 175 +#define CLKID_SD_EMMC_C 176 +#define CLKID_TS_DIV 177 +#define CLKID_TS 178 +#define CLKID_ETH_125M_DIV 179 +#define CLKID_ETH_125M 180 +#define CLKID_ETH_RMII_DIV 181 +#define CLKID_ETH_RMII 182 +#define CLKID_MIPI_DSI_MEAS_SEL 183 +#define CLKID_MIPI_DSI_MEAS_DIV 184 +#define CLKID_MIPI_DSI_MEAS 185 +#define CLKID_DSI_PHY_SEL 186 +#define CLKID_DSI_PHY_DIV 187 +#define CLKID_DSI_PHY 188 +#define CLKID_VOUT_MCLK_SEL 189 +#define CLKID_VOUT_MCLK_DIV 190 +#define CLKID_VOUT_MCLK 191 +#define CLKID_VOUT_ENC_SEL 192 +#define CLKID_VOUT_ENC_DIV 193 +#define CLKID_VOUT_ENC 194 +#define CLKID_HCODEC_0_SEL 195 +#define CLKID_HCODEC_0_DIV 196 +#define CLKID_HCODEC_0 197 +#define CLKID_HCODEC_1_SEL 198 +#define CLKID_HCODEC_1_DIV 199 +#define CLKID_HCODEC_1 200 +#define CLKID_HCODEC 201 +#define CLKID_VC9000E_ACLK_SEL 202 +#define CLKID_VC9000E_ACLK_DIV 203 +#define CLKID_VC9000E_ACLK 204 +#define CLKID_VC9000E_CORE_SEL 205 +#define CLKID_VC9000E_CORE_DIV 206 +#define CLKID_VC9000E_CORE 207 +#define CLKID_CSI_PHY0_SEL 208 +#define CLKID_CSI_PHY0_DIV 209 +#define CLKID_CSI_PHY0 210 +#define CLKID_DEWARPA_SEL 211 +#define CLKID_DEWARPA_DIV 212 +#define CLKID_DEWARPA 213 +#define CLKID_ISP0_SEL 214 +#define CLKID_ISP0_DIV 215 +#define CLKID_ISP0 216 +#define CLKID_NNA_CORE_SEL 217 +#define CLKID_NNA_CORE_DIV 218 +#define CLKID_NNA_CORE 219 +#define CLKID_GE2D_SEL 220 +#define CLKID_GE2D_DIV 221 +#define CLKID_GE2D 222 +#define CLKID_VAPB_SEL 223 +#define CLKID_VAPB_DIV 224 +#define CLKID_VAPB 225 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */ --=20 2.39.2 From nobody Wed Dec 31 09:04:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21CD5C4167D for ; Mon, 6 Nov 2023 08:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231247AbjKFI4Z (ORCPT ); Mon, 6 Nov 2023 03:56:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231243AbjKFI4V (ORCPT ); Mon, 6 Nov 2023 03:56:21 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D323D51; Mon, 6 Nov 2023 00:56:16 -0800 (PST) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 6 Nov 2023 16:56:13 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V6 3/4] clk: meson: c3: add support for the C3 SoC PLL clock Date: Mon, 6 Nov 2023 16:55:53 +0800 Message-ID: <20231106085554.3237511-4-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> References: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.98.11.200] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/c3-pll.c | 895 +++++++++++++++++++++++++++++++++++++ 3 files changed, 909 insertions(+) create mode 100644 drivers/clk/meson/c3-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index c5303e4c1604..eab796f3d25b 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -128,6 +128,19 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_C3_PLL + tristate "Amlogic C3 PLL clock controller" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + select COMMON_CLK_MESON_CLKC_UTILS + help + Support for the PLL clock controller on Amlogic C302X and C308L devices, + AKA c3. Amlogic C302X and C308L devices include AW402 and the others. + Say Y if you want the board to work, because PLLs are the parent of most + peripherals. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 9ee4b954c896..4420af628b31 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c new file mode 100644 index 000000000000..b663666e3755 --- /dev/null +++ b/drivers/clk/meson/c3-pll.c @@ -0,0 +1,895 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic C3 PLL Controller Driver + * + * Copyright (c) 2023 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-pll.h" +#include "meson-clkc-utils.h" +#include + +#define ANACTRL_FIXPLL_CTRL0 0x40 +#define ANACTRL_FIXPLL_CTRL4 0x50 +#define ANACTRL_GP0PLL_CTRL0 0x80 +#define ANACTRL_GP0PLL_CTRL1 0x84 +#define ANACTRL_GP0PLL_CTRL2 0x88 +#define ANACTRL_GP0PLL_CTRL3 0x8c +#define ANACTRL_GP0PLL_CTRL4 0x90 +#define ANACTRL_GP0PLL_CTRL5 0x94 +#define ANACTRL_GP0PLL_CTRL6 0x98 +#define ANACTRL_GP0PLL_STS 0x9c +#define ANACTRL_GP1PLL_CTRL0 0xc0 +#define ANACTRL_GP1PLL_CTRL1 0xc4 +#define ANACTRL_GP1PLL_CTRL2 0xc8 +#define ANACTRL_GP1PLL_CTRL3 0xcc +#define ANACTRL_GP1PLL_CTRL4 0xd0 +#define ANACTRL_GP1PLL_CTRL5 0xd4 +#define ANACTRL_GP1PLL_CTRL6 0xd8 +#define ANACTRL_GP1PLL_STS 0xdc +#define ANACTRL_HIFIPLL_CTRL0 0x100 +#define ANACTRL_HIFIPLL_CTRL1 0x104 +#define ANACTRL_HIFIPLL_CTRL2 0x108 +#define ANACTRL_HIFIPLL_CTRL3 0x10c +#define ANACTRL_HIFIPLL_CTRL4 0x110 +#define ANACTRL_HIFIPLL_CTRL5 0x114 +#define ANACTRL_HIFIPLL_CTRL6 0x118 +#define ANACTRL_HIFIPLL_STS 0x11c +#define ANACTRL_MPLL_CTRL0 0x180 +#define ANACTRL_MPLL_CTRL1 0x184 +#define ANACTRL_MPLL_CTRL2 0x188 +#define ANACTRL_MPLL_CTRL3 0x18c +#define ANACTRL_MPLL_CTRL4 0x190 +#define ANACTRL_MPLL_STS 0x1a4 + +/* + * These clock are a fixed value (fixed_pll is 2GHz) that is initialized b= y ROMcode. + * The chip was changed fixed pll for security reasons. Fixed PLL register= s are not writable + * in the kernel phase. Write of fixed PLL-related register will cause the= system to crash. + * Meanwhile, these clock won't ever change at runtime. + * For the above reasons, we can only use ro_ops for fixed PLL related clo= cks. + */ +static struct clk_regmap fixed_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 16, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fixed_pll_dco", + .ops =3D &meson_clk_pll_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fixed_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 12, + .width =3D 3, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fixed_pll", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll_dco.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_50m_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_50m_en", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_50m =3D { + .mult =3D 1, + .div =3D 40, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_50m", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_50m_en.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div2_div =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div2p5_div =3D { + .mult =3D 2, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2p5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2p5 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div2p5", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2p5_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div3_div =3D { + .mult =3D 1, + .div =3D 3, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div3_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div3 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div3", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div3_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div4_div =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div4_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div4 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 21, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div4", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div4_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div5_div =3D { + .mult =3D 1, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div5 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 22, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div5", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div5_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div7_div =3D { + .mult =3D 1, + .div =3D 7, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div7_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div7 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_FIXPLL_CTRL4, + .bit_idx =3D 23, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_div7", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div7_div.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct reg_sequence c3_gp0_init_regs[] =3D { + { .reg =3D ANACTRL_GP0PLL_CTRL2, .def =3D 0x0 }, + { .reg =3D ANACTRL_GP0PLL_CTRL3, .def =3D 0x48681c00 }, + { .reg =3D ANACTRL_GP0PLL_CTRL4, .def =3D 0x88770290 }, + { .reg =3D ANACTRL_GP0PLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D ANACTRL_GP0PLL_CTRL6, .def =3D 0x56540000 }, +}; + +static const struct pll_mult_range c3_gp0_pll_mult_range =3D { + .min =3D 125, + .max =3D 250, +}; + +static struct clk_regmap gp0_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .frac =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .n =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_gp0_pll_mult_range, + .init_regs =3D c3_gp0_init_regs, + .init_count =3D ARRAY_SIZE(c3_gp0_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + }, +}; + +/* The maximum frequency divider supports is 32, not 128(2^7) */ +static const struct clk_div_table c3_gp0_pll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { 5, 32 }, + { /* sentinel */ } +}; + +static struct clk_regmap gp0_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_GP0PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + .table =3D c3_gp0_pll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp0_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gp0_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * The register corresponding to gp1_pll has permission restrictions, + * The corresponding register is read-only in the kernel. + * For the above reasons, we can only use ro_ops for gp1_pll related clock= s. + */ +static struct clk_regmap gp1_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 0, + .width =3D 9, + }, + .frac =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .n =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp1_pll_dco", + .ops =3D &meson_clk_pll_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap gp1_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_GP1PLL_CTRL0, + .shift =3D 16, + .width =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gp1_pll", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gp1_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static const struct reg_sequence c3_hifi_init_regs[] =3D { + { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x0 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x6a285c00 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL4, .def =3D 0x65771290 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL5, .def =3D 0x3927200a }, + { .reg =3D ANACTRL_HIFIPLL_CTRL6, .def =3D 0x56540000 }, +}; + +static struct clk_regmap hifi_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .frac =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .n =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_gp0_pll_mult_range, + .init_regs =3D c3_hifi_init_regs, + .init_count =3D ARRAY_SIZE(c3_hifi_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "top", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap hifi_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 16, + .width =3D 2, + .flags =3D CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifi_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hifi_pll_dco.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence c3_mclk_init_regs[] =3D { + { .reg =3D ANACTRL_MPLL_CTRL1, .def =3D 0x1420500f }, + { .reg =3D ANACTRL_MPLL_CTRL2, .def =3D 0x00023041 }, + { .reg =3D ANACTRL_MPLL_CTRL3, .def =3D 0x18180000 }, + { .reg =3D ANACTRL_MPLL_CTRL2, .def =3D 0x00023001 } +}; + +static const struct pll_mult_range c3_mclk_pll_mult_range =3D { + .min =3D 67, + .max =3D 133, +}; + +static struct clk_regmap mclk_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data) { + .en =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .l =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_MPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + .range =3D &c3_mclk_pll_mult_range, + .init_regs =3D c3_mclk_init_regs, + .init_count =3D ARRAY_SIZE(c3_mclk_init_regs), + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll_dco", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "mpll", + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_div_table c3_mpll_od_table[] =3D { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap mclk_pll_od =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL0, + .shift =3D 12, + .width =3D 3, + .table =3D c3_mpll_od_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll_od", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk_pll_dco.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* both value 0 and 1 gives divide the input rate by one */ +static struct clk_regmap mclk_pll =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 16, + .width =3D 5, + .flags =3D CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk_pll_od.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data mclk_parent[] =3D { + { .hw =3D &mclk_pll.hw }, + { .fw_name =3D "mpll" }, + { .hw =3D &fclk_50m.hw } +}; + +static struct clk_regmap mclk0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .mask =3D 0x3, + .shift =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D mclk_parent, + .num_parents =3D ARRAY_SIZE(mclk_parent), + }, +}; + +static struct clk_regmap mclk0_div_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_div_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 2, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_div_en.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .mask =3D 0x3, + .shift =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D mclk_parent, + .num_parents =3D ARRAY_SIZE(mclk_parent), + }, +}; + +static struct clk_regmap mclk1_div_en =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_div_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_div_en.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ANACTRL_MPLL_CTRL4, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mclk1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *c3_pll_hw_clks[] =3D { + [CLKID_FIXED_PLL_DCO] =3D &fixed_pll_dco.hw, + [CLKID_FIXED_PLL] =3D &fixed_pll.hw, + [CLKID_FCLK_50M_EN] =3D &fclk_50m_en.hw, + [CLKID_FCLK_50M] =3D &fclk_50m.hw, + [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, + [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, + [CLKID_FCLK_DIV2P5_DIV] =3D &fclk_div2p5_div.hw, + [CLKID_FCLK_DIV2P5] =3D &fclk_div2p5.hw, + [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, + [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, + [CLKID_FCLK_DIV4_DIV] =3D &fclk_div4_div.hw, + [CLKID_FCLK_DIV4] =3D &fclk_div4.hw, + [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, + [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, + [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, + [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, + [CLKID_GP0_PLL_DCO] =3D &gp0_pll_dco.hw, + [CLKID_GP0_PLL] =3D &gp0_pll.hw, + [CLKID_GP1_PLL_DCO] =3D &gp1_pll_dco.hw, + [CLKID_GP1_PLL] =3D &gp1_pll.hw, + [CLKID_HIFI_PLL_DCO] =3D &hifi_pll_dco.hw, + [CLKID_HIFI_PLL] =3D &hifi_pll.hw, + [CLKID_MCLK_PLL_DCO] =3D &mclk_pll_dco.hw, + [CLKID_MCLK_PLL_OD] =3D &mclk_pll_od.hw, + [CLKID_MCLK_PLL] =3D &mclk_pll.hw, + [CLKID_MCLK0_SEL] =3D &mclk0_sel.hw, + [CLKID_MCLK0_SEL_EN] =3D &mclk0_div_en.hw, + [CLKID_MCLK0_DIV] =3D &mclk0_div.hw, + [CLKID_MCLK0] =3D &mclk0.hw, + [CLKID_MCLK1_SEL] =3D &mclk1_sel.hw, + [CLKID_MCLK1_SEL_EN] =3D &mclk1_div_en.hw, + [CLKID_MCLK1_DIV] =3D &mclk1_div.hw, + [CLKID_MCLK1] =3D &mclk1.hw +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const c3_pll_clk_regmaps[] =3D { + &fixed_pll_dco, + &fixed_pll, + &fclk_50m_en, + &fclk_div2, + &fclk_div2p5, + &fclk_div3, + &fclk_div4, + &fclk_div5, + &fclk_div7, + &gp0_pll_dco, + &gp0_pll, + &gp1_pll_dco, + &gp1_pll, + &hifi_pll_dco, + &hifi_pll, + &mclk_pll_dco, + &mclk_pll_od, + &mclk_pll, + &mclk0_sel, + &mclk0_div_en, + &mclk0_div, + &mclk0, + &mclk1_sel, + &mclk1_div_en, + &mclk1_div, + &mclk1, +}; + +static struct regmap_config clkc_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static struct meson_clk_hw_data c3_pll_clks =3D { + .hws =3D c3_pll_hw_clks, + .num =3D ARRAY_SIZE(c3_pll_hw_clks), +}; + +static int aml_c3_pll_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int clkid, ret, i; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++) + c3_pll_clk_regmaps[i]->map =3D regmap; + + for (clkid =3D 0; clkid < c3_pll_clks.num; clkid++) { + /* array might be sparse */ + if (!c3_pll_clks.hws[clkid]) + continue; + + ret =3D devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, + &c3_pll_clks); +} + +static const struct of_device_id c3_pll_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,c3-pll-clkc", + }, + {} +}; +MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table); + +static struct platform_driver c3_pll_driver =3D { + .probe =3D aml_c3_pll_probe, + .driver =3D { + .name =3D "c3-pll-clkc", + .of_match_table =3D c3_pll_clkc_match_table, + }, +}; + +module_platform_driver(c3_pll_driver); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); --=20 2.39.2 From nobody Wed Dec 31 09:04:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C73FC4167D for ; Mon, 6 Nov 2023 08:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231574AbjKFI5X (ORCPT ); Mon, 6 Nov 2023 03:57:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231375AbjKFI5L (ORCPT ); Mon, 6 Nov 2023 03:57:11 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A5CE136; Mon, 6 Nov 2023 00:56:20 -0800 (PST) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 6 Nov 2023 16:56:15 +0800 From: Xianwei Zhao To: , , , , CC: Neil Armstrong , Jerome Brunet , Michael Turquette , "Stephen Boyd" , Rob Herring , "Krzysztof Kozlowski" , Kevin Hilman , Martin Blumenstingl , Chuan Liu , Xianwei Zhao Subject: [PATCH V6 4/4] clk: meson: c3: add c3 clock peripherals controller driver Date: Mon, 6 Nov 2023 16:55:54 +0800 Message-ID: <20231106085554.3237511-5-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> References: <20231106085554.3237511-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.98.11.200] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the C3 peripherals clock controller driver in the C3 SoC family. Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/c3-peripherals.c | 2745 ++++++++++++++++++++++++++++ 3 files changed, 2759 insertions(+) create mode 100644 drivers/clk/meson/c3-peripherals.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index eab796f3d25b..f3ad3030a6b9 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -141,6 +141,19 @@ config COMMON_CLK_C3_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_C3_PERIPHERALS + tristate "Amlogic C3 peripherals clock controller" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + help + Support for the Peripherals clock controller on Amlogic C302X and + C308L devices, AKA c3. Amlogic C302X and C308L devices include + AW402 and others. Say Y if you want the peripherals clock to + work. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 4420af628b31..20ad9482c892 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o +obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c new file mode 100644 index 000000000000..ea0f71d4deb0 --- /dev/null +++ b/drivers/clk/meson/c3-peripherals.c @@ -0,0 +1,2745 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic C3 Peripherals Clock Controller Driver + * + * Copyright (c) 2023 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define OSCIN_CTRL 0x4 +#define RTC_BY_OSCIN_CTRL0 0x8 +#define RTC_BY_OSCIN_CTRL1 0xc +#define RTC_CTRL 0x10 +#define SYS_CLK_CTRL0 0x40 +#define SYS_CLK_EN0_REG0 0x44 +#define SYS_CLK_EN0_REG1 0x48 +#define SYS_CLK_EN0_REG2 0x4c +#define AXI_CLK_CTRL0 0x6c +#define CLK12_24_CTRL 0xa8 +#define AXI_CLK_EN0 0xac +#define VDIN_MEAS_CLK_CTRL 0xf8 +#define VAPB_CLK_CTRL 0xfc +#define MIPIDSI_PHY_CLK_CTRL 0x104 +#define GE2D_CLK_CTRL 0x10c +#define ISP0_CLK_CTRL 0x110 +#define DEWARPA_CLK_CTRL 0x114 +#define VOUTENC_CLK_CTRL 0x118 +#define VDEC_CLK_CTRL 0x140 +#define VDEC3_CLK_CTRL 0x148 +#define TS_CLK_CTRL 0x158 +#define ETH_CLK_CTRL 0x164 +#define NAND_CLK_CTRL 0x168 +#define SD_EMMC_CLK_CTRL 0x16c +#define SPICC_CLK_CTRL 0x174 +#define GEN_CLK_CTRL 0x178 +#define SAR_CLK_CTRL0 0x17c +#define PWM_CLK_AB_CTRL 0x180 +#define PWM_CLK_CD_CTRL 0x184 +#define PWM_CLK_EF_CTRL 0x188 +#define PWM_CLK_GH_CTRL 0x18c +#define PWM_CLK_IJ_CTRL 0x190 +#define PWM_CLK_KL_CTRL 0x194 +#define PWM_CLK_MN_CTRL 0x198 +#define VC9000E_CLK_CTRL 0x19c +#define SPIFC_CLK_CTRL 0x1a0 +#define NNA_CLK_CTRL 0x220 + +static struct clk_regmap pll_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pll_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap mclk_pll_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mclk_pll_in", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +/* + * These clocks can't be closed, the system will crash or + * not work good for some peripherals if close, + * so use read-only ops. + */ +static struct clk_regmap ddr_pll_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ddr_pll_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ddr_phy_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 2, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ddr_phy_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap usb_pll_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "usb_pll_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap mipi_isp_vout_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mipi_isp_vout_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap usb_ctrl_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "usb_ctrl_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_pll_src =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D OSCIN_CTRL, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_pll_src", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data cts_osc_src_parent_data[] =3D { + { .fw_name =3D "xtal_32k" }, + { .fw_name =3D "xtal_24m" } +}; + +static struct clk_regmap cts_osc_src =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D OSCIN_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_osc_src", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D cts_osc_src_parent_data, + .num_parents =3D ARRAY_SIZE(cts_osc_src_parent_data), + }, +}; + +static struct clk_regmap rtc_xtal_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_xtal_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &cts_osc_src.hw, + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param rtc_32k_div_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap rtc_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D rtc_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_xtal_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data rtc_32k_mux_parent_data[] =3D { + { .hw =3D &rtc_32k_div.hw }, + { .hw =3D &rtc_xtal_clkin.hw } +}; + +static struct clk_regmap rtc_32k_mux =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_mux", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D rtc_32k_mux_parent_data, + .num_parents =3D ARRAY_SIZE(rtc_32k_mux_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc_32k =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_mux.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Index 2 clock is pad input clock, here we had not used. + * Index 3 is grounded. + */ +static const struct clk_parent_data rtc_clk_mux_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .hw =3D &rtc_32k.hw } +}; + +static struct clk_regmap rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D rtc_clk_mux_parent_data, + .num_parents =3D ARRAY_SIZE(rtc_clk_mux_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 5(axi_clk_frcpu) is an external axi_cpu clock that is not handl= ed + * right now. The corresponding registers are not placed in PLL or periphe= rals + * and are not readable or writable by the kernel, only accessed through + * SMC to SCP. + * Channel 6 is not connected. + */ +static u32 sys_axi_parent_table[] =3D { 0, 1, 2, 3, 4, 7 }; + +static const struct clk_parent_data sys_axi_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .hw =3D &rtc_clk.hw } +}; + +/* + * These clocks are initialized by ROM code. + * The chip was changed SYS_CLK for security reason. SYS_CLK registers are + * not writable in the kernel phase. Writing of SYS related register will = cause + * the system to crash. Meanwhile, these clocks won't be changed at runtim= e. + * For the above reasons, we can only use ro_ops for SYS related clocks. + */ +static struct clk_regmap sys_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D sys_axi_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_a_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D sys_axi_parent_data, + .num_parents =3D ARRAY_SIZE(sys_axi_parent_data), + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap sys_a_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SYS_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_a_div", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap sys_a =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SYS_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_a", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap sys_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D sys_axi_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_b_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D sys_axi_parent_data, + .num_parents =3D ARRAY_SIZE(sys_axi_parent_data), + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap sys_b_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SYS_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_b_div", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_regmap sys_b =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SYS_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_b", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +static const struct clk_parent_data sys_clk_parent_data[] =3D { + { .hw =3D &sys_a.hw }, + { .hw =3D &sys_b.hw } +}; + +static struct clk_regmap sys_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_clk", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D sys_clk_parent_data, + .num_parents =3D ARRAY_SIZE(sys_clk_parent_data), + .flags =3D CLK_GET_RATE_NOCACHE, + }, +}; + +/* + * In the system, high-speed modules such as DDR, SRAM, ROM, CAPU and + * other key modules communicate through AXI_BUS and the clock is + * provided by the axi_clk. While the axi_clock is source of several + * peripheral gates, and that all should in theory be described and + * properly handled, it is not the case at the moment. + * The system will crash if the axi_clock is turned off, so the + * clock is critical, at least for now. + */ +static struct clk_regmap axi_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D AXI_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D sys_axi_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D sys_axi_parent_data, + .num_parents =3D ARRAY_SIZE(sys_axi_parent_data), + }, +}; + +static struct clk_regmap axi_a_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D AXI_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &axi_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axi_a =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D AXI_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &axi_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axi_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D AXI_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D sys_axi_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D sys_axi_parent_data, + .num_parents =3D ARRAY_SIZE(sys_axi_parent_data), + }, +}; + +static struct clk_regmap axi_b_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D AXI_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &axi_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axi_b =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D AXI_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &axi_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data axi_clk_parent_data[] =3D { + { .hw =3D &axi_a.hw }, + { .hw =3D &axi_b.hw } +}; + +static struct clk_regmap axi_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D AXI_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "axi_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D axi_clk_parent_data, + .num_parents =3D ARRAY_SIZE(axi_clk_parent_data), + .flags =3D CLK_IS_CRITICAL, + }, +}; + +#define AML_CLK_GATE_SYS_CLK(_name, _reg, _bit)\ + MESON_PCLK(_name, _reg, _bit, &sys_clk.hw) +#define AML_CLK_GATE_AXI_CLK(_name, _reg, _bit)\ + MESON_PCLK(_name, _reg, _bit, &axi_clk.hw) + +static AML_CLK_GATE_SYS_CLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1); +static AML_CLK_GATE_SYS_CLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3); +static AML_CLK_GATE_SYS_CLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4); +static AML_CLK_GATE_SYS_CLK(sys_ctrl, SYS_CLK_EN0_REG0, 5); +static AML_CLK_GATE_SYS_CLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6); +static AML_CLK_GATE_SYS_CLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7); +static AML_CLK_GATE_SYS_CLK(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8); +static AML_CLK_GATE_SYS_CLK(sys_capu, SYS_CLK_EN0_REG0, 9); +static AML_CLK_GATE_SYS_CLK(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11); +static AML_CLK_GATE_SYS_CLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12); +static AML_CLK_GATE_SYS_CLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13); +static AML_CLK_GATE_SYS_CLK(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14); +static AML_CLK_GATE_SYS_CLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15); +static AML_CLK_GATE_SYS_CLK(sys_rom, SYS_CLK_EN0_REG0, 16); +static AML_CLK_GATE_SYS_CLK(sys_uart_f, SYS_CLK_EN0_REG0, 17); +static AML_CLK_GATE_SYS_CLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18); +static AML_CLK_GATE_SYS_CLK(sys_rsa, SYS_CLK_EN0_REG0, 19); +static AML_CLK_GATE_SYS_CLK(sys_sar_adc, SYS_CLK_EN0_REG0, 20); +static AML_CLK_GATE_SYS_CLK(sys_startup, SYS_CLK_EN0_REG0, 21); +static AML_CLK_GATE_SYS_CLK(sys_secure, SYS_CLK_EN0_REG0, 22); +static AML_CLK_GATE_SYS_CLK(sys_spifc, SYS_CLK_EN0_REG0, 23); +static AML_CLK_GATE_SYS_CLK(sys_nna, SYS_CLK_EN0_REG0, 25); +static AML_CLK_GATE_SYS_CLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26); +static AML_CLK_GATE_SYS_CLK(sys_gic, SYS_CLK_EN0_REG0, 27); +static AML_CLK_GATE_SYS_CLK(sys_rama, SYS_CLK_EN0_REG0, 28); +static AML_CLK_GATE_SYS_CLK(sys_big_nic, SYS_CLK_EN0_REG0, 29); +static AML_CLK_GATE_SYS_CLK(sys_ramb, SYS_CLK_EN0_REG0, 30); +static AML_CLK_GATE_SYS_CLK(sys_audio_pclk, SYS_CLK_EN0_REG0, 31); +static AML_CLK_GATE_SYS_CLK(sys_pwm_kl, SYS_CLK_EN0_REG1, 0); +static AML_CLK_GATE_SYS_CLK(sys_pwm_ij, SYS_CLK_EN0_REG1, 1); +static AML_CLK_GATE_SYS_CLK(sys_usb, SYS_CLK_EN0_REG1, 2); +static AML_CLK_GATE_SYS_CLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3); +static AML_CLK_GATE_SYS_CLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4); +static AML_CLK_GATE_SYS_CLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5); +static AML_CLK_GATE_SYS_CLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6); +static AML_CLK_GATE_SYS_CLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7); +static AML_CLK_GATE_SYS_CLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8); +static AML_CLK_GATE_SYS_CLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9); +static AML_CLK_GATE_SYS_CLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10); +static AML_CLK_GATE_SYS_CLK(sys_uart_a, SYS_CLK_EN0_REG1, 11); +static AML_CLK_GATE_SYS_CLK(sys_uart_b, SYS_CLK_EN0_REG1, 12); +static AML_CLK_GATE_SYS_CLK(sys_uart_c, SYS_CLK_EN0_REG1, 13); +static AML_CLK_GATE_SYS_CLK(sys_uart_d, SYS_CLK_EN0_REG1, 14); +static AML_CLK_GATE_SYS_CLK(sys_uart_e, SYS_CLK_EN0_REG1, 15); +static AML_CLK_GATE_SYS_CLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16); +static AML_CLK_GATE_SYS_CLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17); +static AML_CLK_GATE_SYS_CLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18); +static AML_CLK_GATE_SYS_CLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19); +static AML_CLK_GATE_SYS_CLK(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20); +static AML_CLK_GATE_SYS_CLK(sys_rtc, SYS_CLK_EN0_REG1, 21); +static AML_CLK_GATE_SYS_CLK(sys_ge2d, SYS_CLK_EN0_REG1, 22); +static AML_CLK_GATE_SYS_CLK(sys_isp, SYS_CLK_EN0_REG1, 23); +static AML_CLK_GATE_SYS_CLK(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24); +static AML_CLK_GATE_SYS_CLK(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25); +static AML_CLK_GATE_SYS_CLK(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26); +static AML_CLK_GATE_SYS_CLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27); +static AML_CLK_GATE_SYS_CLK(sys_eth_phy, SYS_CLK_EN0_REG1, 28); +static AML_CLK_GATE_SYS_CLK(sys_acodec, SYS_CLK_EN0_REG1, 29); +static AML_CLK_GATE_SYS_CLK(sys_dwap, SYS_CLK_EN0_REG1, 30); +static AML_CLK_GATE_SYS_CLK(sys_dos, SYS_CLK_EN0_REG1, 31); +static AML_CLK_GATE_SYS_CLK(sys_cve, SYS_CLK_EN0_REG2, 0); +static AML_CLK_GATE_SYS_CLK(sys_vout, SYS_CLK_EN0_REG2, 1); +static AML_CLK_GATE_SYS_CLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2); +static AML_CLK_GATE_SYS_CLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3); +static AML_CLK_GATE_SYS_CLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4); + +static AML_CLK_GATE_AXI_CLK(axi_sys_nic, AXI_CLK_EN0, 2); +static AML_CLK_GATE_AXI_CLK(axi_isp_nic, AXI_CLK_EN0, 3); +static AML_CLK_GATE_AXI_CLK(axi_cve_nic, AXI_CLK_EN0, 4); +static AML_CLK_GATE_AXI_CLK(axi_ramb, AXI_CLK_EN0, 5); +static AML_CLK_GATE_AXI_CLK(axi_rama, AXI_CLK_EN0, 6); +static AML_CLK_GATE_AXI_CLK(axi_cpu_dmc, AXI_CLK_EN0, 7); +static AML_CLK_GATE_AXI_CLK(axi_nic, AXI_CLK_EN0, 8); +static AML_CLK_GATE_AXI_CLK(axi_dma, AXI_CLK_EN0, 9); +static AML_CLK_GATE_AXI_CLK(axi_mux_nic, AXI_CLK_EN0, 10); +static AML_CLK_GATE_AXI_CLK(axi_capu, AXI_CLK_EN0, 11); +static AML_CLK_GATE_AXI_CLK(axi_cve, AXI_CLK_EN0, 12); +static AML_CLK_GATE_AXI_CLK(axi_dev1_dmc, AXI_CLK_EN0, 13); +static AML_CLK_GATE_AXI_CLK(axi_dev0_dmc, AXI_CLK_EN0, 14); +static AML_CLK_GATE_AXI_CLK(axi_dsp_dmc, AXI_CLK_EN0, 15); + +/* + * clk_12_24m model + * + * |------| |-----| clk_12m_24m |-----| + * xtal---->| gate |---->| div |------------>| pad | + * |------| |-----| |-----| + */ +static struct clk_regmap clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +/* Fix me: set value 0 will div by 2 like value 1 */ +static struct clk_regmap fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 2(sys_pll_div16), 17(sys_cpu_clk_div16) registers have + * permission restrictions. These registers are not readable or writable + * by the kernel, only accessed through SMC to SCP. This is not + * available at the moment. + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_= msr_clk) + * is manged by clock measures module. Their hardware are out of clock tre= e. + * Channel 4 8 9 10 11 13 14 15 16 18 are not connected. + */ +static u32 gen_parent_table[] =3D { 0, 1, 5, 6, 7, 19, 20, 21, 22, 23, 24}; + +static const struct clk_parent_data gen_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .hw =3D &rtc_clk.hw }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D gen_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D gen_parent_data, + .num_parents =3D ARRAY_SIZE(gen_parent_data), + }, +}; + +static struct clk_regmap gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data saradc_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .hw =3D &sys_clk.hw } +}; + +static struct clk_regmap saradc_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SAR_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D saradc_parent_data, + .num_parents =3D ARRAY_SIZE(saradc_parent_data), + }, +}; + +static struct clk_regmap saradc_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SAR_CLK_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap saradc =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SAR_CLK_CTRL0, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D _reg, \ + .mask =3D 0x3, \ + .shift =3D _shift, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D pwm_parent_data, \ + .num_parents =3D ARRAY_SIZE(pwm_parent_data), \ + }, \ +} + +#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D _reg, \ + .shift =3D _shift, \ + .width =3D 8, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_names =3D (const char *[]) { #_name "_sel" },\ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D _reg, \ + .bit_idx =3D _bit, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_names =3D (const char *[]) { #_name "_div" },\ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +static struct clk_regmap pwm_a_sel =3D + AML_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); +static struct clk_regmap pwm_a_div =3D + AML_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); +static struct clk_regmap pwm_a =3D + AML_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static struct clk_regmap pwm_b_sel =3D + AML_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); +static struct clk_regmap pwm_b_div =3D + AML_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); +static struct clk_regmap pwm_b =3D + AML_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static struct clk_regmap pwm_c_sel =3D + AML_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); +static struct clk_regmap pwm_c_div =3D + AML_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); +static struct clk_regmap pwm_c =3D + AML_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static struct clk_regmap pwm_d_sel =3D + AML_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); +static struct clk_regmap pwm_d_div =3D + AML_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); +static struct clk_regmap pwm_d =3D + AML_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static struct clk_regmap pwm_e_sel =3D + AML_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); +static struct clk_regmap pwm_e_div =3D + AML_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); +static struct clk_regmap pwm_e =3D + AML_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static struct clk_regmap pwm_f_sel =3D + AML_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); +static struct clk_regmap pwm_f_div =3D + AML_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); +static struct clk_regmap pwm_f =3D + AML_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static struct clk_regmap pwm_g_sel =3D + AML_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); +static struct clk_regmap pwm_g_div =3D + AML_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); +static struct clk_regmap pwm_g =3D + AML_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static struct clk_regmap pwm_h_sel =3D + AML_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); +static struct clk_regmap pwm_h_div =3D + AML_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); +static struct clk_regmap pwm_h =3D + AML_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static struct clk_regmap pwm_i_sel =3D + AML_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); +static struct clk_regmap pwm_i_div =3D + AML_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); +static struct clk_regmap pwm_i =3D + AML_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static struct clk_regmap pwm_j_sel =3D + AML_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); +static struct clk_regmap pwm_j_div =3D + AML_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); +static struct clk_regmap pwm_j =3D + AML_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static struct clk_regmap pwm_k_sel =3D + AML_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); +static struct clk_regmap pwm_k_div =3D + AML_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); +static struct clk_regmap pwm_k =3D + AML_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static struct clk_regmap pwm_l_sel =3D + AML_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); +static struct clk_regmap pwm_l_div =3D + AML_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); +static struct clk_regmap pwm_l =3D + AML_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static struct clk_regmap pwm_m_sel =3D + AML_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); +static struct clk_regmap pwm_m_div =3D + AML_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); +static struct clk_regmap pwm_m =3D + AML_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static struct clk_regmap pwm_n_sel =3D + AML_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); +static struct clk_regmap pwm_n_div =3D + AML_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); +static struct clk_regmap pwm_n =3D + AML_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); + +static const struct clk_parent_data spicc_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .hw =3D &sys_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap spicc_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SPICC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_parent_data, + .num_parents =3D ARRAY_SIZE(spicc_parent_data), + }, +}; + +static struct clk_regmap spicc_a_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SPICC_CLK_CTRL, + .shift =3D 0, + .width =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_a =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SPICC_CLK_CTRL, + .bit_idx =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SPICC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 23, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_parent_data, + .num_parents =3D ARRAY_SIZE(spicc_parent_data), + }, +}; + +static struct clk_regmap spicc_b_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SPICC_CLK_CTRL, + .shift =3D 16, + .width =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_b =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SPICC_CLK_CTRL, + .bit_idx =3D 22, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data spifc_parent_data[] =3D { + { .fw_name =3D "gp0" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap spifc_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SPIFC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spifc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spifc_parent_data, + .num_parents =3D ARRAY_SIZE(spifc_parent_data), + }, +}; + +static struct clk_regmap spifc_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SPIFC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spifc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spifc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spifc =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SPIFC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spifc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spifc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data emmc_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "gp0" } +}; + +static struct clk_regmap sd_emmc_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D emmc_parent_data, + .num_parents =3D ARRAY_SIZE(emmc_parent_data), + }, +}; + +static struct clk_regmap sd_emmc_a_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_a =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D emmc_parent_data, + .num_parents =3D ARRAY_SIZE(emmc_parent_data), + }, +}; + +static struct clk_regmap sd_emmc_b_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_b =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D SD_EMMC_CLK_CTRL, + .bit_idx =3D 23, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_c_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D NAND_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D emmc_parent_data, + .num_parents =3D ARRAY_SIZE(emmc_parent_data), + }, +}; + +static struct clk_regmap sd_emmc_c_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D NAND_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_c_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_c =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D NAND_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_c_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &cts_osc_src.hw, + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data eth_parent =3D { + .fw_name =3D "fdiv2", +}; + +static struct clk_fixed_factor eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D ð_parent, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + ð_125m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D ð_parent, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + ð_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data mipi_dsi_meas_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap mipi_dsi_meas_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VDIN_MEAS_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 21, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mipi_dsi_meas_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D mipi_dsi_meas_parent_data, + .num_parents =3D ARRAY_SIZE(mipi_dsi_meas_parent_data), + }, +}; + +static struct clk_regmap mipi_dsi_meas_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VDIN_MEAS_CLK_CTRL, + .shift =3D 12, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mipi_dsi_meas_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mipi_dsi_meas_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_dsi_meas =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VDIN_MEAS_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "mipi_dsi_meas", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &mipi_dsi_meas_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data dsi_phy_parent_data[] =3D { + { .fw_name =3D "gp1" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap dsi_phy_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D MIPIDSI_PHY_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dsi_phy_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dsi_phy_parent_data, + .num_parents =3D ARRAY_SIZE(dsi_phy_parent_data), + }, +}; + +static struct clk_regmap dsi_phy_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D MIPIDSI_PHY_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dsi_phy_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dsi_phy_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dsi_phy =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D MIPIDSI_PHY_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dsi_phy", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dsi_phy_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data vout_parent_data[] =3D { + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap vout_mclk_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VOUTENC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_mclk_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D vout_parent_data, + .num_parents =3D ARRAY_SIZE(vout_parent_data), + }, +}; + +static struct clk_regmap vout_mclk_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VOUTENC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_mclk_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vout_mclk_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vout_mclk =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D MIPIDSI_PHY_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_mclk", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vout_mclk_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vout_enc_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VOUTENC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_enc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D vout_parent_data, + .num_parents =3D ARRAY_SIZE(vout_parent_data), + }, +}; + +static struct clk_regmap vout_enc_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VOUTENC_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_enc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vout_enc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vout_enc =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VOUTENC_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vout_enc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vout_enc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data hcodec_pre_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp0" }, + { .hw =3D &cts_osc_src.hw } +}; + +static struct clk_regmap hcodec_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VDEC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D hcodec_pre_parent_data, + .num_parents =3D ARRAY_SIZE(hcodec_pre_parent_data), + }, +}; + +static struct clk_regmap hcodec_0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VDEC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hcodec_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap hcodec_0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VDEC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hcodec_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap hcodec_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VDEC3_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D hcodec_pre_parent_data, + .num_parents =3D ARRAY_SIZE(hcodec_pre_parent_data), + }, +}; + +static struct clk_regmap hcodec_1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VDEC3_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hcodec_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap hcodec_1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VDEC3_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &hcodec_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data hcodec_parent_data[] =3D { + { .hw =3D &hcodec_0.hw }, + { .hw =3D &hcodec_1.hw } +}; + +static struct clk_regmap hcodec =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VDEC3_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hcodec", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D hcodec_parent_data, + .num_parents =3D ARRAY_SIZE(hcodec_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data vc9000e_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp0" } +}; + +static struct clk_regmap vc9000e_aclk_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VC9000E_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_aclk_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D vc9000e_parent_data, + .num_parents =3D ARRAY_SIZE(vc9000e_parent_data), + }, +}; + +static struct clk_regmap vc9000e_aclk_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VC9000E_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_aclk_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vc9000e_aclk_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vc9000e_aclk =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VC9000E_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_aclk", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vc9000e_aclk_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vc9000e_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VC9000E_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D vc9000e_parent_data, + .num_parents =3D ARRAY_SIZE(vc9000e_parent_data), + }, +}; + +static struct clk_regmap vc9000e_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VC9000E_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vc9000e_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vc9000e_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VC9000E_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vc9000e_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vc9000e_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data csi_phy_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp1" }, + { .hw =3D &cts_osc_src.hw } +}; + +static struct clk_regmap csi_phy0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ISP0_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "csi_phy0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D csi_phy_parent_data, + .num_parents =3D ARRAY_SIZE(csi_phy_parent_data), + }, +}; + +static struct clk_regmap csi_phy0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ISP0_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "csi_phy0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &csi_phy0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap csi_phy0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ISP0_CLK_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "csi_phy0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &csi_phy0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data dewarpa_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap dewarpa_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D DEWARPA_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dewarpa_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dewarpa_parent_data, + .num_parents =3D ARRAY_SIZE(dewarpa_parent_data), + }, +}; + +static struct clk_regmap dewarpa_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D DEWARPA_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dewarpa_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dewarpa_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dewarpa =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D DEWARPA_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dewarpa", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dewarpa_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data isp_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp1" }, + { .hw =3D &cts_osc_src.hw } +}; + +static struct clk_regmap isp0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D ISP0_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "isp0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D isp_parent_data, + .num_parents =3D ARRAY_SIZE(isp_parent_data), + }, +}; + +static struct clk_regmap isp0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D ISP0_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "isp0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &isp0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap isp0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D ISP0_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "isp0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &isp0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data nna_core_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" } +}; + +static struct clk_regmap nna_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D NNA_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D nna_core_parent_data, + .num_parents =3D ARRAY_SIZE(nna_core_parent_data), + }, +}; + +static struct clk_regmap nna_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D NNA_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap nna_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D NNA_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data ge2d_parent_data[] =3D { + { .hw =3D &cts_osc_src.hw }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .hw =3D &rtc_clk.hw } +}; + +static struct clk_regmap ge2d_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D GE2D_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ge2d_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D ge2d_parent_data, + .num_parents =3D ARRAY_SIZE(ge2d_parent_data), + }, +}; + +static struct clk_regmap ge2d_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D GE2D_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ge2d_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ge2d_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ge2d =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D GE2D_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ge2d", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ge2d_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data vapb_parent_data[] =3D { + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "gp0" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "gp1" }, + { .hw =3D &cts_osc_src.hw } +}; + +static struct clk_regmap vapb_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D VAPB_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vapb_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D vapb_parent_data, + .num_parents =3D ARRAY_SIZE(vapb_parent_data), + }, +}; + +static struct clk_regmap vapb_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D VAPB_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vapb_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vapb_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap vapb =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D VAPB_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "vapb", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &vapb_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *c3_periphs_hw_clks[] =3D { + [CLKID_PLL_SRC] =3D &pll_src.hw, + [CLKID_MCLK_PLL_SRC] =3D &mclk_pll_src.hw, + [CLKID_DDR_PLL_SRC] =3D &ddr_pll_src.hw, + [CLKID_DDR_PHY_SRC] =3D &ddr_phy_src.hw, + [CLKID_USB_PLL_SRC] =3D &usb_pll_src.hw, + [CLKID_MIPI_ISP_VOUT_SRC] =3D &mipi_isp_vout_src.hw, + [CLKID_USB_CTRL_SRC] =3D &usb_ctrl_src.hw, + [CLKID_ETH_PLL_SRC] =3D ð_pll_src.hw, + [CLKID_CTS_OSC_SRC] =3D &cts_osc_src.hw, + [CLKID_RTC_XTAL_CLKIN] =3D &rtc_xtal_clkin.hw, + [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, + [CLKID_RTC_32K_MUX] =3D &rtc_32k_mux.hw, + [CLKID_RTC_32K] =3D &rtc_32k.hw, + [CLKID_RTC_CLK] =3D &rtc_clk.hw, + [CLKID_SYS_A_SEL] =3D &sys_a_sel.hw, + [CLKID_SYS_A_DIV] =3D &sys_a_div.hw, + [CLKID_SYS_A] =3D &sys_a.hw, + [CLKID_SYS_B_SEL] =3D &sys_b_sel.hw, + [CLKID_SYS_B_DIV] =3D &sys_b_div.hw, + [CLKID_SYS_B] =3D &sys_b.hw, + [CLKID_SYS_CLK] =3D &sys_clk.hw, + [CLKID_AXI_A_SEL] =3D &axi_a_sel.hw, + [CLKID_AXI_A_DIV] =3D &axi_a_div.hw, + [CLKID_AXI_A] =3D &axi_a.hw, + [CLKID_AXI_B_SEL] =3D &axi_b_sel.hw, + [CLKID_AXI_B_DIV] =3D &axi_b_div.hw, + [CLKID_AXI_B] =3D &axi_b.hw, + [CLKID_AXI_CLK] =3D &axi_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &sys_reset_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &sys_pwr_ctrl.hw, + [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &sys_dev_arb.hw, + [CLKID_SYS_MMC_PCLK] =3D &sys_mmc_pclk.hw, + [CLKID_SYS_CAPU] =3D &sys_capu.hw, + [CLKID_SYS_CPU_CTRL] =3D &sys_cpu_ctrl.hw, + [CLKID_SYS_JTAG_CTRL] =3D &sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &sys_ir_ctrl.hw, + [CLKID_SYS_IRQ_CTRL] =3D &sys_irq_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &sys_rom.hw, + [CLKID_SYS_UART_F] =3D &sys_uart_f.hw, + [CLKID_SYS_CPU_ARB] =3D &sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &sys_rsa.hw, + [CLKID_SYS_SAR_ADC] =3D &sys_sar_adc.hw, + [CLKID_SYS_STARTUP] =3D &sys_startup.hw, + [CLKID_SYS_SECURE] =3D &sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &sys_spifc.hw, + [CLKID_SYS_NNA] =3D &sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &sys_eth_mac.hw, + [CLKID_SYS_GIC] =3D &sys_gic.hw, + [CLKID_SYS_RAMA] =3D &sys_rama.hw, + [CLKID_SYS_BIG_NIC] =3D &sys_big_nic.hw, + [CLKID_SYS_RAMB] =3D &sys_ramb.hw, + [CLKID_SYS_AUDIO_PCLK] =3D &sys_audio_pclk.hw, + [CLKID_SYS_PWM_KL] =3D &sys_pwm_kl.hw, + [CLKID_SYS_PWM_IJ] =3D &sys_pwm_ij.hw, + [CLKID_SYS_USB] =3D &sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &sys_i2c_m_d.hw, + [CLKID_SYS_I2S_S_A] =3D &sys_i2c_s_a.hw, + [CLKID_SYS_RTC] =3D &sys_rtc.hw, + [CLKID_SYS_GE2D] =3D &sys_ge2d.hw, + [CLKID_SYS_ISP] =3D &sys_isp.hw, + [CLKID_SYS_GPV_ISP_NIC] =3D &sys_gpv_isp_nic.hw, + [CLKID_SYS_GPV_CVE_NIC] =3D &sys_gpv_cve_nic.hw, + [CLKID_SYS_MIPI_DSI_HOST] =3D &sys_mipi_dsi_host.hw, + [CLKID_SYS_MIPI_DSI_PHY] =3D &sys_mipi_dsi_phy.hw, + [CLKID_SYS_ETH_PHY] =3D &sys_eth_phy.hw, + [CLKID_SYS_ACODEC] =3D &sys_acodec.hw, + [CLKID_SYS_DWAP] =3D &sys_dwap.hw, + [CLKID_SYS_DOS] =3D &sys_dos.hw, + [CLKID_SYS_CVE] =3D &sys_cve.hw, + [CLKID_SYS_VOUT] =3D &sys_vout.hw, + [CLKID_SYS_VC9000E] =3D &sys_vc9000e.hw, + [CLKID_SYS_PWM_MN] =3D &sys_pwm_mn.hw, + [CLKID_SYS_SD_EMMC_B] =3D &sys_sd_emmc_b.hw, + [CLKID_AXI_SYS_NIC] =3D &axi_sys_nic.hw, + [CLKID_AXI_ISP_NIC] =3D &axi_isp_nic.hw, + [CLKID_AXI_CVE_NIC] =3D &axi_cve_nic.hw, + [CLKID_AXI_RAMB] =3D &axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &axi_rama.hw, + [CLKID_AXI_CPU_DMC] =3D &axi_cpu_dmc.hw, + [CLKID_AXI_NIC] =3D &axi_nic.hw, + [CLKID_AXI_DMA] =3D &axi_dma.hw, + [CLKID_AXI_MUX_NIC] =3D &axi_mux_nic.hw, + [CLKID_AXI_CAPU] =3D &axi_capu.hw, + [CLKID_AXI_CVE] =3D &axi_cve.hw, + [CLKID_AXI_DEV1_DMC] =3D &axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &fclk_25m.hw, + [CLKID_GEN_SEL] =3D &gen_sel.hw, + [CLKID_GEN_DIV] =3D &gen_div.hw, + [CLKID_GEN] =3D &gen.hw, + [CLKID_SARADC_SEL] =3D &saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &saradc_div.hw, + [CLKID_SARADC] =3D &saradc.hw, + [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, + [CLKID_PWM_A] =3D &pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, + [CLKID_PWM_B] =3D &pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, + [CLKID_PWM_C] =3D &pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, + [CLKID_PWM_D] =3D &pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, + [CLKID_PWM_E] =3D &pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, + [CLKID_PWM_F] =3D &pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &pwm_g_div.hw, + [CLKID_PWM_G] =3D &pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &pwm_h_div.hw, + [CLKID_PWM_H] =3D &pwm_h.hw, + [CLKID_PWM_I_SEL] =3D &pwm_i_sel.hw, + [CLKID_PWM_I_DIV] =3D &pwm_i_div.hw, + [CLKID_PWM_I] =3D &pwm_i.hw, + [CLKID_PWM_J_SEL] =3D &pwm_j_sel.hw, + [CLKID_PWM_J_DIV] =3D &pwm_j_div.hw, + [CLKID_PWM_J] =3D &pwm_j.hw, + [CLKID_PWM_K_SEL] =3D &pwm_k_sel.hw, + [CLKID_PWM_K_DIV] =3D &pwm_k_div.hw, + [CLKID_PWM_K] =3D &pwm_k.hw, + [CLKID_PWM_L_SEL] =3D &pwm_l_sel.hw, + [CLKID_PWM_L_DIV] =3D &pwm_l_div.hw, + [CLKID_PWM_L] =3D &pwm_l.hw, + [CLKID_PWM_M_SEL] =3D &pwm_m_sel.hw, + [CLKID_PWM_M_DIV] =3D &pwm_m_div.hw, + [CLKID_PWM_M] =3D &pwm_m.hw, + [CLKID_PWM_N_SEL] =3D &pwm_n_sel.hw, + [CLKID_PWM_N_DIV] =3D &pwm_n_div.hw, + [CLKID_PWM_N] =3D &pwm_n.hw, + [CLKID_SPICC_A_SEL] =3D &spicc_a_sel.hw, + [CLKID_SPICC_A_DIV] =3D &spicc_a_div.hw, + [CLKID_SPICC_A] =3D &spicc_a.hw, + [CLKID_SPICC_B_SEL] =3D &spicc_b_sel.hw, + [CLKID_SPICC_B_DIV] =3D &spicc_b_div.hw, + [CLKID_SPICC_B] =3D &spicc_b.hw, + [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, + [CLKID_SPIFC_DIV] =3D &spifc_div.hw, + [CLKID_SPIFC] =3D &spifc.hw, + [CLKID_SD_EMMC_A_SEL] =3D &sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] =3D &sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] =3D &sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] =3D &sd_emmc_b.hw, + [CLKID_SD_EMMC_C_SEL] =3D &sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &ts_div.hw, + [CLKID_TS] =3D &ts.hw, + [CLKID_ETH_125M_DIV] =3D ð_125m_div.hw, + [CLKID_ETH_125M] =3D ð_125m.hw, + [CLKID_ETH_RMII_DIV] =3D ð_rmii_div.hw, + [CLKID_ETH_RMII] =3D ð_rmii.hw, + [CLKID_MIPI_DSI_MEAS_SEL] =3D &mipi_dsi_meas_sel.hw, + [CLKID_MIPI_DSI_MEAS_DIV] =3D &mipi_dsi_meas_div.hw, + [CLKID_MIPI_DSI_MEAS] =3D &mipi_dsi_meas.hw, + [CLKID_DSI_PHY_SEL] =3D &dsi_phy_sel.hw, + [CLKID_DSI_PHY_DIV] =3D &dsi_phy_div.hw, + [CLKID_DSI_PHY] =3D &dsi_phy.hw, + [CLKID_VOUT_MCLK_SEL] =3D &vout_mclk_sel.hw, + [CLKID_VOUT_MCLK_DIV] =3D &vout_mclk_div.hw, + [CLKID_VOUT_MCLK] =3D &vout_mclk.hw, + [CLKID_VOUT_ENC_SEL] =3D &vout_enc_sel.hw, + [CLKID_VOUT_ENC_DIV] =3D &vout_enc_div.hw, + [CLKID_VOUT_ENC] =3D &vout_enc.hw, + [CLKID_HCODEC_0_SEL] =3D &hcodec_0_sel.hw, + [CLKID_HCODEC_0_DIV] =3D &hcodec_0_div.hw, + [CLKID_HCODEC_0] =3D &hcodec_0.hw, + [CLKID_HCODEC_1_SEL] =3D &hcodec_1_sel.hw, + [CLKID_HCODEC_1_DIV] =3D &hcodec_1_div.hw, + [CLKID_HCODEC_1] =3D &hcodec_1.hw, + [CLKID_HCODEC] =3D &hcodec.hw, + [CLKID_VC9000E_ACLK_SEL] =3D &vc9000e_aclk_sel.hw, + [CLKID_VC9000E_ACLK_DIV] =3D &vc9000e_aclk_div.hw, + [CLKID_VC9000E_ACLK] =3D &vc9000e_aclk.hw, + [CLKID_VC9000E_CORE_SEL] =3D &vc9000e_core_sel.hw, + [CLKID_VC9000E_CORE_DIV] =3D &vc9000e_core_div.hw, + [CLKID_VC9000E_CORE] =3D &vc9000e_core.hw, + [CLKID_CSI_PHY0_SEL] =3D &csi_phy0_sel.hw, + [CLKID_CSI_PHY0_DIV] =3D &csi_phy0_div.hw, + [CLKID_CSI_PHY0] =3D &csi_phy0.hw, + [CLKID_DEWARPA_SEL] =3D &dewarpa_sel.hw, + [CLKID_DEWARPA_DIV] =3D &dewarpa_div.hw, + [CLKID_DEWARPA] =3D &dewarpa.hw, + [CLKID_ISP0_SEL] =3D &isp0_sel.hw, + [CLKID_ISP0_DIV] =3D &isp0_div.hw, + [CLKID_ISP0] =3D &isp0.hw, + [CLKID_NNA_CORE_SEL] =3D &nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &nna_core_div.hw, + [CLKID_NNA_CORE] =3D &nna_core.hw, + [CLKID_GE2D_SEL] =3D &ge2d_sel.hw, + [CLKID_GE2D_DIV] =3D &ge2d_div.hw, + [CLKID_GE2D] =3D &ge2d.hw, + [CLKID_VAPB_SEL] =3D &vapb_sel.hw, + [CLKID_VAPB_DIV] =3D &vapb_div.hw, + [CLKID_VAPB] =3D &vapb.hw, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const c3_periphs_clk_regmaps[] =3D { + &pll_src, + &mclk_pll_src, + &ddr_pll_src, + &ddr_phy_src, + &usb_pll_src, + &mipi_isp_vout_src, + &usb_ctrl_src, + ð_pll_src, + &cts_osc_src, + &rtc_xtal_clkin, + &rtc_32k_div, + &rtc_32k_mux, + &rtc_32k, + &rtc_clk, + &sys_a_sel, + &sys_a_div, + &sys_a, + &sys_b_sel, + &sys_b_div, + &sys_b, + &sys_clk, + &axi_a_sel, + &axi_a_div, + &axi_a, + &axi_b_sel, + &axi_b_div, + &axi_b, + &axi_clk, + &sys_reset_ctrl, + &sys_pwr_ctrl, + &sys_pad_ctrl, + &sys_ctrl, + &sys_ts_pll, + &sys_dev_arb, + &sys_mmc_pclk, + &sys_capu, + &sys_cpu_ctrl, + &sys_jtag_ctrl, + &sys_ir_ctrl, + &sys_irq_ctrl, + &sys_msr_clk, + &sys_rom, + &sys_uart_f, + &sys_cpu_apb, + &sys_rsa, + &sys_sar_adc, + &sys_startup, + &sys_secure, + &sys_spifc, + &sys_nna, + &sys_eth_mac, + &sys_gic, + &sys_rama, + &sys_big_nic, + &sys_ramb, + &sys_audio_pclk, + &sys_pwm_kl, + &sys_pwm_ij, + &sys_usb, + &sys_sd_emmc_a, + &sys_sd_emmc_c, + &sys_pwm_ab, + &sys_pwm_cd, + &sys_pwm_ef, + &sys_pwm_gh, + &sys_spicc_1, + &sys_spicc_0, + &sys_uart_a, + &sys_uart_b, + &sys_uart_c, + &sys_uart_d, + &sys_uart_e, + &sys_i2c_m_a, + &sys_i2c_m_b, + &sys_i2c_m_c, + &sys_i2c_m_d, + &sys_i2c_s_a, + &sys_rtc, + &sys_ge2d, + &sys_isp, + &sys_gpv_isp_nic, + &sys_gpv_cve_nic, + &sys_mipi_dsi_host, + &sys_mipi_dsi_phy, + &sys_eth_phy, + &sys_acodec, + &sys_dwap, + &sys_dos, + &sys_cve, + &sys_vout, + &sys_vc9000e, + &sys_pwm_mn, + &sys_sd_emmc_b, + &axi_sys_nic, + &axi_isp_nic, + &axi_cve_nic, + &axi_ramb, + &axi_rama, + &axi_cpu_dmc, + &axi_nic, + &axi_dma, + &axi_mux_nic, + &axi_capu, + &axi_cve, + &axi_dev1_dmc, + &axi_dev0_dmc, + &axi_dsp_dmc, + &clk_12_24m_in, + &clk_12_24m, + &fclk_25m_div, + &fclk_25m, + &gen_sel, + &gen_div, + &gen, + &saradc_sel, + &saradc_div, + &saradc, + &pwm_a_sel, + &pwm_a_div, + &pwm_a, + &pwm_b_sel, + &pwm_b_div, + &pwm_b, + &pwm_c_sel, + &pwm_c_div, + &pwm_c, + &pwm_d_sel, + &pwm_d_div, + &pwm_d, + &pwm_e_sel, + &pwm_e_div, + &pwm_e, + &pwm_f_sel, + &pwm_f_div, + &pwm_f, + &pwm_g_sel, + &pwm_g_div, + &pwm_g, + &pwm_h_sel, + &pwm_h_div, + &pwm_h, + &pwm_i_sel, + &pwm_i_div, + &pwm_i, + &pwm_j_sel, + &pwm_j_div, + &pwm_j, + &pwm_k_sel, + &pwm_k_div, + &pwm_k, + &pwm_l_sel, + &pwm_l_div, + &pwm_l, + &pwm_m_sel, + &pwm_m_div, + &pwm_m, + &pwm_n_sel, + &pwm_n_div, + &pwm_n, + &spicc_a_sel, + &spicc_a_div, + &spicc_a, + &spicc_b_sel, + &spicc_b_div, + &spicc_b, + &spifc_sel, + &spifc_div, + &spifc, + &sd_emmc_a_sel, + &sd_emmc_a_div, + &sd_emmc_a, + &sd_emmc_b_sel, + &sd_emmc_b_div, + &sd_emmc_b, + &sd_emmc_c_sel, + &sd_emmc_c_div, + &sd_emmc_c, + &ts_div, + &ts, + ð_125m, + ð_rmii_div, + ð_rmii, + &mipi_dsi_meas_sel, + &mipi_dsi_meas_div, + &mipi_dsi_meas, + &dsi_phy_sel, + &dsi_phy_div, + &dsi_phy, + &vout_mclk_sel, + &vout_mclk_div, + &vout_mclk, + &vout_enc_sel, + &vout_enc_div, + &vout_enc, + &hcodec_0_sel, + &hcodec_0_div, + &hcodec_0, + &hcodec_1_sel, + &hcodec_1_div, + &hcodec_1, + &hcodec, + &vc9000e_aclk_sel, + &vc9000e_aclk_div, + &vc9000e_aclk, + &vc9000e_core_sel, + &vc9000e_core_div, + &vc9000e_core, + &csi_phy0_sel, + &csi_phy0_div, + &csi_phy0, + &dewarpa_sel, + &dewarpa_div, + &dewarpa, + &isp0_sel, + &isp0_div, + &isp0, + &nna_core_sel, + &nna_core_div, + &nna_core, + &ge2d_sel, + &ge2d_div, + &ge2d, + &vapb_sel, + &vapb_div, + &vapb, +}; + +static struct regmap_config clkc_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static struct meson_clk_hw_data c3_periphs_clks =3D { + .hws =3D c3_periphs_hw_clks, + .num =3D ARRAY_SIZE(c3_periphs_hw_clks), +}; + +static int aml_c3_peripherals_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int clkid, ret, i; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(c3_periphs_clk_regmaps); i++) + c3_periphs_clk_regmaps[i]->map =3D regmap; + + for (clkid =3D 0; clkid < c3_periphs_clks.num; clkid++) { + /* array might be sparse */ + if (!c3_periphs_clks.hws[clkid]) + continue; + + ret =3D devm_clk_hw_register(dev, c3_periphs_clks.hws[clkid]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, + &c3_periphs_clks); +} + +static const struct of_device_id c3_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,c3-peripherals-clkc", + }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table); + +static struct platform_driver c3_peripherals_driver =3D { + .probe =3D aml_c3_peripherals_probe, + .driver =3D { + .name =3D "c3-peripherals-clkc", + .of_match_table =3D c3_peripherals_clkc_match_table, + }, +}; + +module_platform_driver(c3_peripherals_driver); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); --=20 2.39.2