From nobody Wed Dec 31 12:28:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F9DC4332F for ; Sat, 4 Nov 2023 00:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232238AbjKDADe (ORCPT ); Fri, 3 Nov 2023 20:03:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231672AbjKDAD2 (ORCPT ); Fri, 3 Nov 2023 20:03:28 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD0B510D7 for ; Fri, 3 Nov 2023 17:03:04 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5a8ee6a1801so36709657b3.3 for ; Fri, 03 Nov 2023 17:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056183; x=1699660983; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=dInD7ODh6HIif39LBjhxEmJKXw4IEIPO7aAD74ERLWY=; b=krWr//TT5QE2k47kfd4ra5+kA7X/LDFMYEldOyiH/MMt7VXGkyWGUBDHuM3ek5PnOr NxqP/pqVNQ6hHs9R+hncA9OL2WtPRgpiU+HQ/ORImmyteulQwkW65KdoCFT0gnblwzzK AzemkB0fMCYEOntzW/OPmurRQNrA4ZodmXt+JCKUTOcP6h2N2P1oPAxkeE+vOQ2pAb4Y SzypV40RtfWmF1QbTFX9jL7xLZWJHulCIJr9a7bdDTpBv4qhTHQh6JvdUNXHKHWB6Mh2 d64nIDMsCnWPOeuK1t6AE1zhJk/uaywu6AQoCABkCnohwkbk7qQPCWb33xGMHBSq9BLd H9CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056183; x=1699660983; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dInD7ODh6HIif39LBjhxEmJKXw4IEIPO7aAD74ERLWY=; b=Ix9GvWY9YGpEcX3ADZHNpDGsc/7tVyDw7B12Haq+isFi8xPMvI3/s1gtj9ncXqiTdT 8XrWDgSALQXFjmMjATdfnGlL1jOQDVkIKJtg68tBn5MqVpuuTROZwVV2LvQIjswXJo6g yCoWAC+9ldIVNxsR4q7CT0NmgEiId/25xbYLcmWqEfroteWGcNG7C5y+D7/RwKlfmEkS 6Qn/09dknYtoEnzgoFwCl98i/9oXuC+Op+lJvGoYdLyMLbcr+bh092pOAtt71UQ2DFqd fUdKr4ichkHR2xjvh0yAFKEPImuBd2xdXan6zZEqz+Li1sJsFH+Gt6spg6PeOQQZVNW9 axBg== X-Gm-Message-State: AOJu0Yz8IXV35doEIAxQvRtKs1ASl6x6hqppanv9Pw9OrElFjKcLlGPf 1GNeFuGoD8q9UJ0u81+4GSzj+gPU6hY= X-Google-Smtp-Source: AGHT+IFOlde1xVggzz2SjvZiRG/TRj1JHKgvpdfbkpxdSI1XSrI3j2mGJRQT/+DFSxp1g/XkaJYT+TW1YCs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:d494:0:b0:59b:ec33:ec6d with SMTP id w142-20020a0dd494000000b0059bec33ec6dmr87965ywd.5.1699056183496; Fri, 03 Nov 2023 17:03:03 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:30 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-13-seanjc@google.com> Subject: [PATCH v6 12/20] KVM: selftests: Test consistency of CPUID with num of gp counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Add a test to verify that KVM correctly emulates MSR-based accesses to general purpose counters based on guest CPUID, e.g. that accesses to non-existent counters #GP and accesses to existent counters succeed. Note, for compatibility reasons, KVM does not emulate #GP when MSR_P6_PERFCTR[0|1] is not present (writes should be dropped). Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 4d3a5c94b8ba..232b9a80a9db 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -270,9 +270,95 @@ static void test_arch_events(uint8_t pmu_version, uint= 64_t perf_capabilities, kvm_vm_free(vm); } =20 +/* + * Limit testing to MSRs that are actually defined by Intel (in the SDM). = MSRs + * that aren't defined counter MSRs *probably* don't exist, but there's no + * guarantee that currently undefined MSR indices won't be used for someth= ing + * other than PMCs in the future. + */ +#define MAX_NR_GP_COUNTERS 8 +#define MAX_NR_FIXED_COUNTERS 3 + +#define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ +__GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ + "Expected %s on " #insn "(0x%x), got vector %u", \ + expect_gp ? "#GP" : "no fault", msr, vector) \ + +static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_co= unters, + uint8_t nr_counters) +{ + uint8_t i; + + for (i =3D 0; i < nr_possible_counters; i++) { + const uint32_t msr =3D base_msr + i; + const bool expect_success =3D i < nr_counters; + + /* + * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are + * unsupported, i.e. doesn't #GP and reads back '0'. + */ + const uint64_t expected_val =3D expect_success ? 0xffff : 0; + const bool expect_gp =3D !expect_success && msr !=3D MSR_P6_PERFCTR0 && + msr !=3D MSR_P6_PERFCTR1; + uint8_t vector; + uint64_t val; + + vector =3D wrmsr_safe(msr, 0xffff); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); + + vector =3D rdmsr_safe(msr, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, msr, expect_gp, vector); + + /* On #GP, the result of RDMSR is undefined. */ + if (!expect_gp) + __GUEST_ASSERT(val =3D=3D expected_val, + "Expected RDMSR(0x%x) to yield 0x%lx, got 0x%lx", + msr, expected_val, val); + + vector =3D wrmsr_safe(msr, 0); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); + } + GUEST_DONE(); +} + +static void guest_test_gp_counters(void) +{ + uint8_t nr_gp_counters =3D 0; + uint32_t base_msr; + + if (guest_get_pmu_version()) + nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + + if (this_cpu_has(X86_FEATURE_PDCM) && + rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + base_msr =3D MSR_IA32_PMC0; + else + base_msr =3D MSR_IA32_PERFCTR0; + + guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters); +} + +static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, + uint8_t nr_gp_counters) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters, + pmu_version, perf_capabilities); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, + nr_gp_counters); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters(void) { uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; uint8_t v, j; @@ -337,6 +423,11 @@ static void test_intel_counters(void) for (k =3D 0; k < nr_arch_events; k++) test_arch_events(v, perf_caps[i], j, BIT(k)); } + + pr_info("Testing GP counters, PMU version %u, perf_caps =3D %lx\n", + v, perf_caps[i]); + for (j =3D 0; j <=3D nr_gp_counters; j++) + test_gp_counters(v, perf_caps[i], j); } } } --=20 2.42.0.869.gea05f2083d-goog