From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F882C4167D for ; Sat, 4 Nov 2023 00:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbjKDACs (ORCPT ); Fri, 3 Nov 2023 20:02:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230453AbjKDACq (ORCPT ); Fri, 3 Nov 2023 20:02:46 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3A1FD52 for ; Fri, 3 Nov 2023 17:02:43 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5a839b31a0dso53877677b3.0 for ; Fri, 03 Nov 2023 17:02:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056162; x=1699660962; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=nOzsUN1YNjo4mM3u1hilIKuxhzw1b/cPpyuR5vqvOEM=; b=CFMT/kaORlS2yU0gvAAAxQ1jOYqJYKqa+q1KZd9Zwuc+usFP6yHgxaoOBKETtlFsHv jHBAR8F7UnDz5/UBgKXgSZE84V7ckfz8L9jy+oCz+lPi+I36q8t/TEPLd4DfM78CMBED p8cd016sLD1tRfZhMOPhlHcPA3NAIY53MEk1kpzXdHjCkDHUdw/p6zociJAplcCG0JL6 5St3VZgwKFNnCnP9LEg523MvY0ckM1/Df3ELVoBjagBf33fjUSNOIyRfiNBMCHK/UlhA zqtzlxYHY6MY7US7zMVNGPip7G1VSzuMG90d9AqUq7d7kz1FF+fs1qTu9iFX6a3R49WZ ZmYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056162; x=1699660962; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=nOzsUN1YNjo4mM3u1hilIKuxhzw1b/cPpyuR5vqvOEM=; b=EWUM0NTOFz2hWFtr4XFuy1F0X7uR7tH1ubnWbHfW/J+Oz9M6NYly+WkPOSwARVJYIT YR+qhnPYLExOFXgIQhb9H5QH4TLut5izAFNdU0QXMgqvUO6Suk2aJ7P3T38D2ZGRU13t F5L8ub5hzExGo7phDt6/VRIonP/UzI7rP1LopGkKQcWzwQ7sITBTf9IqhlB4+gxMat5t ySr4+RybF88NsClZsNYnuah0hGXGvOon8m17ZQGtWP23yS8sf/SyIhubXMdEOzSDIb4a ni50M3fVrNTLiAuInu3tmD5DrFP8pV1wriZvllmsXbqpOJIbm8wtkXwyOmOx3U7viMOz bN/A== X-Gm-Message-State: AOJu0Yx3hlrl8wiWJmnRnTYTo9hFizAuC6sDVKpk3Ejxx52weQKf2Sm1 ZOY2cMW8xXTf4IfaMOnUGlZI5qTDPmg= X-Google-Smtp-Source: AGHT+IGAbN0m5ShzVxvluMl0W5kCIQjTup2IT2nxWsIkQodtNZB6+MZQkaVB8Sf70LHX1BZEnLV0C+dyiLg= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:df52:0:b0:5a7:b9b0:d23f with SMTP id i79-20020a0ddf52000000b005a7b9b0d23fmr83931ywe.6.1699056162701; Fri, 03 Nov 2023 17:02:42 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:19 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-2-seanjc@google.com> Subject: [PATCH v6 01/20] KVM: x86/pmu: Don't allow exposing unsupported architectural events From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hide architectural events that unsupported according to guest CPUID *or* hardware, i.e. don't let userspace advertise and potentially program unsupported architectural events. Note, KVM already limits the length of the reverse polarity field, only the mask itself is missing. Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests= ") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 820d3e1f6b4f..1b13a472e3f2 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -533,7 +533,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->counter_bitmask[KVM_PMC_GP] =3D ((u64)1 << eax.split.bit_width) - 1; eax.split.mask_length =3D min_t(int, eax.split.mask_length, kvm_pmu_cap.events_mask_len); - pmu->available_event_types =3D ~entry->ebx & + pmu->available_event_types =3D ~(entry->ebx | kvm_pmu_cap.events_mask) & ((1ull << eax.split.mask_length) - 1); =20 if (pmu->version =3D=3D 1) { --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE9E5C4167D for ; Sat, 4 Nov 2023 00:03:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231506AbjKDADA (ORCPT ); Fri, 3 Nov 2023 20:03:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230525AbjKDACs (ORCPT ); Fri, 3 Nov 2023 20:02:48 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D849D52 for ; Fri, 3 Nov 2023 17:02:45 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-5a7c97d5d5aso36356147b3.3 for ; Fri, 03 Nov 2023 17:02:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056164; x=1699660964; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=p4xV9oxEUCCvhRrb6fqtuKFYy/N3YfDlsPZEG53vyL0=; b=otFSU2wWsZyl6neWohK/oP5brqvW3GLUgh7Q9z4+AzrG2/RG/ZeNc6EanSs3Q5VcOo TRrENT125CPq3l9YFbCsGPuFjWXD1/RODD/vBgJ6yC9FZuWaoCeMQcDmNWZvVVmB0nSv nwlV2/LI+/7KTg3ZZeLx/VCKlQ0qgGmUAauD/3WwkJnHCooiv/i9Xe1BMMTD8MK2Br3Z tF9gFAeiDpDxCcUmod7qNxBHWGfOY6rKtYkBFv/CPldYLWzRXXXmtsRfY0pK/3DT/6lJ ZFRwt6DcwtiWD26JOzyj017zB1aGraj4kUwhZM42gUBFjbJUgDYm7YGG9tBofMSWhBYn ahcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056164; x=1699660964; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=p4xV9oxEUCCvhRrb6fqtuKFYy/N3YfDlsPZEG53vyL0=; b=G9udR8SO8uhOH8EtJKm640DlGdwbLKWWZgilf9XySeNp0WCkj5nwo/VZ4BavzaLmaw zIbwvvycSEekRtw4VDe3QBpJCAVjBC1Gc85UeSccIpEk1ZHnA1hZyPdXKM8tqkDsbwIC doZ09MATtU46SX/aUUCjvbm6MHuUUE0qhaOjhByOmctNH6UsQLQIxiWb+CY2sKsjBoiZ jBTgh/XLvGBILNQ8oJSAel07DPGp1reIA+V7RyHc+xvxv6T4I7B1r8al+pXejFvl2BBC ltB3XH99mtDbEq1jgo6Fd5UKgWomb+m4gO1gwxa/3L/OWr+v//fxGxcCfmBY+dCi3O/G iJJg== X-Gm-Message-State: AOJu0YzuOyX3nezg9RR6goAnBgolYPtLBNxmPr/HEnaMANafg4vWHJdQ BJ0FcT+9wlGCwFBaLmOc/qJJPzh+hxw= X-Google-Smtp-Source: AGHT+IFF5h6aHvxK72aMJUSi4VypGMmZlTaV053V/rwUhfhONXUsVv99CMju5sH06/LqKgg4wCIizIPYbAE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:bc90:0:b0:d9c:c9a8:8c27 with SMTP id e16-20020a25bc90000000b00d9cc9a88c27mr445478ybk.13.1699056164647; Fri, 03 Nov 2023 17:02:44 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:20 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-3-seanjc@google.com> Subject: [PATCH v6 02/20] KVM: x86/pmu: Don't enumerate support for fixed counters KVM can't virtualize From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hide fixed counters for which perf is incapable of creating the associated architectural event. Except for the so called pseudo-architectural event for counting TSC reference cycle, KVM virtualizes fixed counters by creating a perf event for the associated general purpose architectural event. If the associated event isn't supported in hardware, KVM can't actually virtualize the fixed counter because perf will likely not program up the correct event. Note, this issue is almost certainly limited to running KVM on a funky virtual CPU model, no known real hardware has an asymmetric PMU where a fixed counter is supported but the associated architectural event is not. Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests= ") Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.h | 4 ++++ arch/x86/kvm/vmx/pmu_intel.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 1d64113de488..5341e8f69a22 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -19,6 +19,7 @@ #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 =20 struct kvm_pmu_ops { + void (*init_pmu_capability)(void); bool (*hw_event_available)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, @@ -218,6 +219,9 @@ static inline void kvm_init_pmu_capability(const struct= kvm_pmu_ops *pmu_ops) pmu_ops->MAX_NR_GP_COUNTERS); kvm_pmu_cap.num_counters_fixed =3D min(kvm_pmu_cap.num_counters_fixed, KVM_PMC_MAX_FIXED); + + if (pmu_ops->init_pmu_capability) + pmu_ops->init_pmu_capability(); } =20 static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 1b13a472e3f2..3316fdea212a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -68,6 +68,36 @@ static int fixed_pmc_events[] =3D { [2] =3D PSEUDO_ARCH_REFERENCE_CYCLES, }; =20 +static void intel_init_pmu_capability(void) +{ + int i; + + /* + * Perf may (sadly) back a guest fixed counter with a general purpose + * counter, and so KVM must hide fixed counters whose associated + * architectural event are unsupported. On real hardware, this should + * never happen, but if KVM is running on a funky virtual CPU model... + * + * TODO: Drop this horror if/when KVM stops using perf events for + * guest fixed counters, or can explicitly request fixed counters. + */ + for (i =3D 0; i < kvm_pmu_cap.num_counters_fixed; i++) { + int event =3D fixed_pmc_events[i]; + + /* + * Ignore pseudo-architectural events, they're a bizarre way of + * requesting events from perf that _can't_ be backed with a + * general purpose architectural event, i.e. they're guaranteed + * to be backed by the real fixed counter. + */ + if (event < NR_REAL_INTEL_ARCH_EVENTS && + (kvm_pmu_cap.events_mask & BIT(event))) + break; + } + + kvm_pmu_cap.num_counters_fixed =3D i; +} + static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) { struct kvm_pmc *pmc; @@ -789,6 +819,7 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { + .init_pmu_capability =3D intel_init_pmu_capability, .hw_event_available =3D intel_hw_event_available, .pmc_idx_to_pmc =3D intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc =3D intel_rdpmc_ecx_to_pmc, --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C77C4332F for ; Sat, 4 Nov 2023 00:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231455AbjKDAC6 (ORCPT ); Fri, 3 Nov 2023 20:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231147AbjKDACu (ORCPT ); Fri, 3 Nov 2023 20:02:50 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E5C8D5A for ; Fri, 3 Nov 2023 17:02:47 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-d9a5a3f2d4fso3024044276.3 for ; Fri, 03 Nov 2023 17:02:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056166; x=1699660966; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=D/rIH8GJk/IJPB5pqHHZ2EWC6jVCZLZPq4HYOnxUc90=; b=Cf35BIGgAvlwQ+n1pQBl2TYlhFecQtLuiALXRejxKRxu8FSdNrEBVqY404/+ZunHwF 1/A3RdiT2KpfK2JDtTPWw6ZpVyqQ3yvWlSPj3KGXOQfokkhfhOQkS5uGWtQEy3LwIjSr F0VFdPqlsxuMHhKoAywFRRhmaTFU9pV1ZZIS5Mf2VBzp78alsa1P+sWhkFVvaiNUDL1u qCrziZX2Zcn/Od6TZfKIdGzumybkDniVdyWReh2/H0FxboEyC48+6GXzt11douvrP1Jk HuzG5VDnhyjY5G6xP+9/ETJ02RqrHTzAO5kGuKlLoE7Wds9yQle/VRJTnRBta/vjNq53 LalA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056166; x=1699660966; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=D/rIH8GJk/IJPB5pqHHZ2EWC6jVCZLZPq4HYOnxUc90=; b=C3SwEPJGAkvug0c3bHDA/T77C+s7IUMezEPcRRURkgGAGudBoCWfTTA6jGBVz0Nstm Q7m4obSVPhfDK2zl4hdKqmF4Zvs+fkkDXxJGKFKtOOdMlfMuy7XJuKutZxeDjdyzr5nw fBf9RhbOLdR0D85sXsOmtSNGm2WOG6DLcyCgZC4Ivk+97j/ENC3aNNgI6l10yqI/HUXK dCEjM3oINvdwn1/02lpxvkbXJsMrjZTQPGMChemHBJ9s8rIipNTgfv2VvsipYffisE3K bcKLXG2a2l0fdTRXyLOxfsc39jrpkAvcSy2Bflhqu4tPv9SqegL0gu9vGBGQZ/61VFq6 dYhA== X-Gm-Message-State: AOJu0YwN71i3BcrKKJYL928PKdM3ZroUWwE9Nkss3Y8YsJZ7qsP3qaOn 0IoEPVTqUEc5JT5JskVGInADKkBXAYg= X-Google-Smtp-Source: AGHT+IG48HKOrJNtDtKClRR1cSurzfdJukbcmuWuNiNDq8LQjymDh0gNZfHiM6JwALmJySH4WydrLAOP3ds= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1083:b0:d9a:c3b8:4274 with SMTP id v3-20020a056902108300b00d9ac3b84274mr544412ybu.7.1699056166538; Fri, 03 Nov 2023 17:02:46 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:21 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-4-seanjc@google.com> Subject: [PATCH v6 03/20] KVM: x86/pmu: Don't enumerate arch events KVM doesn't support From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't advertise support to userspace for architectural events that KVM doesn't support, i.e. for "real" events that aren't listed in intel_pmu_architectural_events. On current hardware, this effectively means "don't advertise support for Top Down Slots". Mask off the associated "unavailable" bits, as said bits for undefined events are reserved to zero. Arguably the events _are_ defined, but from a KVM perspective they might as well not exist, and there's absolutely no reason to leave useless unavailable bits set. Fixes: a6c06ed1a60a ("KVM: Expose the architectural performance monitoring = CPUID leaf") Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 3316fdea212a..8d545f84dc4a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -73,6 +73,15 @@ static void intel_init_pmu_capability(void) int i; =20 /* + * Do not enumerate support for architectural events that KVM doesn't + * support. Clear unsupported events "unavailable" bit as well, as + * architecturally such bits are reserved to zero. + */ + kvm_pmu_cap.events_mask_len =3D min(kvm_pmu_cap.events_mask_len, + NR_REAL_INTEL_ARCH_EVENTS); + kvm_pmu_cap.events_mask &=3D GENMASK(kvm_pmu_cap.events_mask_len - 1, 0); + + /* * Perf may (sadly) back a guest fixed counter with a general purpose * counter, and so KVM must hide fixed counters whose associated * architectural event are unsupported. On real hardware, this should --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A50CDC4167B for ; Sat, 4 Nov 2023 00:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbjKDADD (ORCPT ); Fri, 3 Nov 2023 20:03:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231183AbjKDACv (ORCPT ); Fri, 3 Nov 2023 20:02:51 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D44F2D49 for ; Fri, 3 Nov 2023 17:02:48 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1cc281f1214so20509305ad.2 for ; Fri, 03 Nov 2023 17:02:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056168; x=1699660968; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=qddZI5QlDYzkDDGMWXMNXP2vKdkDVMrPtOHGx6AbiEs=; b=byDXblP4cNIdEpE/d9r52ueFTlhR93MmVW7ZYBxtIjeNwlSRrs/pWCiS6ZL0gXgZeC 3+WyIjyee77RjBGJ5ws1LLp5hjyUWc15DqrMbDOIa4RL04oCeUauUZy1Q3JdHzRVInca jSlOJoygzuKi1+49VvB9fCCGjAKag1Y36mOSJqkz7njdd7U2P870wDCklI6pbd4KUjDN gFTc7XvR5AhSJGEqIPzn/qrGpbl/ViKg+AQ2RGpQgApggXo//rtIm5UZQ+V3tX1RG0Hy rldEN/EWdeJIMPtt2dUvZk86tjo8RNfqauEYpbm+yNS9l/Hdhsq3bz2MAcI6RM4MleIw g8Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056168; x=1699660968; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qddZI5QlDYzkDDGMWXMNXP2vKdkDVMrPtOHGx6AbiEs=; b=RtGM5sfw2i49Y8OSFUHl2qTa4vgFXI2g9D1L8F0Ywq0qd7FfTEhaT0wetvi1LqTTMF XI8koKhxYo/f9oqYm372v4c32vWRYXhGJFQILFR4txtMzHvlnuFJ2LsK7VppQQloLEnG 4HCKWGeTUaUvp3VyiAPyjLGQHKd1HIDRRHM7c8+H5P2tHVw+dG2zqUxXUY7KBDcfCBjb dgJ1IvIjSnGkfwb+NS3eQKwN7nLrq74Ji8YLcwOKIrdJS82z6EWTDemzYaZuXd/3ndpe kQqyT/YXiMqw3dsdGUJXn6JeQu+ONwuAKAyduGYze09ty3lN/41M58s1rM5keQCyLKp+ iLSw== X-Gm-Message-State: AOJu0Yxso9NSV1l4lQwB4nQaypVfvZlTHQO1B2Vk9MZYjnjjPpPg5El/ 6PpkS5dWJjqFBDDW/BH3GnYjbOJnG0k= X-Google-Smtp-Source: AGHT+IGx/PwxlYpOuRKdZYbE5Hej8a6OBTDWyR7ILfdU8v4Jzm6thIWMKr1A2kcm/hqxX7sahHWFkfGx6ug= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:ab84:b0:1c9:b045:5a8b with SMTP id f4-20020a170902ab8400b001c9b0455a8bmr372275plr.6.1699056168312; Fri, 03 Nov 2023 17:02:48 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:22 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-5-seanjc@google.com> Subject: [PATCH v6 04/20] KVM: x86/pmu: Always treat Fixed counters as available when supported From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that KVM hides fixed counters that can't be virtualized, treat fixed counters as available when they are supported, i.e. don't silently ignore an enabled fixed counter just because guest CPUID says the associated general purpose architectural event is unavailable. KVM originally treated fixed counters as always available, but that got changed as part of a fix to avoid confusing REF_CPU_CYCLES, which does NOT map to an architectural event, with the actual architectural event used associated with bit 7, TOPDOWN_SLOTS. The commit justified the change with: If the event is marked as unavailable in the Intel guest CPUID 0AH.EBX leaf, we need to avoid any perf_event creation, whether it's a gp or fixed counter. but that justification doesn't mesh with reality. The Intel SDM uses "architectural events" to refer to both general purpose events (the ones with the reverse polarity mask in CPUID.0xA.EBX) and the events for fixed counters, e.g. the SDM makes statements like: Each of the fixed-function PMC can count only one architectural performance event. but the fact that fixed counter 2 (TSC reference cycles) doesn't have an associated general purpose architectural makes trying to apply the mask from CPUID.0xA.EBX impossible. Furthermore, the SDM never explicitly says that an architectural events that's marked unavailable in EBX affects the fixed counters. Note, at the time of the change, KVM didn't enforce hardware support, i.e. didn't prevent userspace from enumerating support in guest CPUID.0xA.EBX for architectural events that aren't supported in hardware. I.e. silently dropping the fixed counter didn't somehow protection against counting the wrong event, it just enforced guest CPUID. Arguably, userspace is creating a bogus vCPU model by advertising a fixed counter but saying the associated general purpose architectural event is unavailable. But regardless of the validity of the vCPU model, letting the guest enable a fixed counter and then not actually having it count anything is completely nonsensical. I.e. even if all of the above is wrong and it's illegal for a fixed counter to exist when the architectural event is unavailable, silently doing nothing is still the wrong behavior and KVM should instead disallow enabling the fixed counter in the first place. Fixes: a21864486f7e ("KVM: x86/pmu: Fix available_event_types check for REF= _CPU_CYCLES event") Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 8d545f84dc4a..b239e7dbdc9b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -147,11 +147,24 @@ static bool intel_hw_event_available(struct kvm_pmc *= pmc) u8 unit_mask =3D (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; int i; =20 + /* + * Fixed counters are always available if KVM reaches this point. If a + * fixed counter is unsupported in hardware or guest CPUID, KVM doesn't + * allow the counter's corresponding MSR to be written. KVM does use + * architectural events to program fixed counters, as the interface to + * perf doesn't allow requesting a specific fixed counter, e.g. perf + * may (sadly) back a guest fixed PMC with a general purposed counter. + * But if _hardware_ doesn't support the associated event, KVM simply + * doesn't enumerate support for the fixed counter. + */ + if (pmc_is_fixed(pmc)) + return true; + BUILD_BUG_ON(ARRAY_SIZE(intel_arch_events) !=3D NR_INTEL_ARCH_EVENTS); =20 /* * Disallow events reported as unavailable in guest CPUID. Note, this - * doesn't apply to pseudo-architectural events. + * doesn't apply to pseudo-architectural events (see above). */ for (i =3D 0; i < NR_REAL_INTEL_ARCH_EVENTS; i++) { if (intel_arch_events[i].eventsel !=3D event_select || --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AA3AC4332F for ; Sat, 4 Nov 2023 00:15:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231136AbjKDAPz (ORCPT ); Fri, 3 Nov 2023 20:15:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231390AbjKDACy (ORCPT ); Fri, 3 Nov 2023 20:02:54 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8C6CD5F for ; Fri, 3 Nov 2023 17:02:50 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1cc1ddb34ccso20496745ad.1 for ; Fri, 03 Nov 2023 17:02:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056170; x=1699660970; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=2pNxubyeriZ6Kmw42WjydTECjrsrFHiPrAbYW9CF/sc=; b=gJetzBr3CpqUMGpntCX81WvKyVoDErGXgWpelljZ+JuXMZBIad+wHV/kct0zjLw1fk Y3p/IdCpj+toBYjOoFNtCx3ziHGp194N165Bqb6wegPhDQ/zlzrL8a3usYikAfAKCND4 q/Tc9z6XesvJnufC0Pbq3wrVTZczXI/fRdyvDvyviSUk+bXPqhJRa6FlVN6HPtfu+way +vspEeTVoX+BnL4w9Do0kAyf4Yuh5CYg0tX/pd7/in81SKVDkXjuen+aXqhe8YbLPSn1 r1e72IdDkMeBN5f/uQQmvMihaPA3qCmdq7P8BYiNgJJjS/h46jYf/rc4QgOxi849U9Kf iUZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056170; x=1699660970; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2pNxubyeriZ6Kmw42WjydTECjrsrFHiPrAbYW9CF/sc=; b=da9ehy8t0DM3s0zEJcIbhXxWRZn+YZ6sW0oJjWe4F0BoX53kyrQFSsq2HBYmUIpcTY s1PgGNUbigG6TyLItjoNP0AR5cbbvJQomphw+CdxDjdByBxQftUc/XpZSe3iOhGqpI5l 1USHS/QgqGLa5UkXgKlF4OKSYP7pOcxq7nYPADahNpdhBzvUdGGIyVaBSlgk0VZf/XHR hT/dyYVfD2027JJlYYbSPTF9AJrRcUyFt5lV03BbHb/j7Os7OmGYUtgiW9FvHhanDmZB vLFzrYMs0ei6w/CuB900UnmNWrJKmIA3KwxafrPM833+riZxAuuiLT50En1P+QkbNfgE ZgBg== X-Gm-Message-State: AOJu0Yyz4JScx4eXkLaP/B5ggOm7kDn0JIqNzHDbGIRW8mW75P/yar3o F4tcbP2065heG+JBbJ7u+Km/xp6Wn2k= X-Google-Smtp-Source: AGHT+IH2+5mojji7zEoMjMrzCTSwGzDwt7lgukPyzMV9CIrg/7JBSpqwd//N7kM1LacJ029i8Pe3LesZ8GY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:efd1:b0:1c6:2b9d:570b with SMTP id ja17-20020a170902efd100b001c62b9d570bmr414315plb.7.1699056170302; Fri, 03 Nov 2023 17:02:50 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:23 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-6-seanjc@google.com> Subject: [PATCH v6 05/20] KVM: x86/pmu: Allow programming events that match unsupported arch events From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove KVM's bogus restriction that the guest can't program an event whose encoding matches an unsupported architectural event. The enumeration of an architectural event only says that if a CPU supports an architectural event, then the event can be programmed using the architectural encoding. The enumeration does NOT say anything about the encoding when the CPU doesn't report support the architectural event. Preventing the guest from counting events whose encoding happens to match an architectural event breaks existing functionality whenever Intel adds an architectural encoding that was *ever* used for a CPU that doesn't enumerate support for the architectural event, even if the encoding is for the exact same event! E.g. the architectural encoding for Top-Down Slots is 0x01a4. Broadwell CPUs, which do not support the Top-Down Slots architectural event, 0x10a4 is a valid, model-specific event. Denying guest usage of 0x01a4 if/when KVM adds support for Top-Down slots would break any Broadwell-based guest. Reported-by: Kan Liang Closes: https://lore.kernel.org/all/2004baa6-b494-462c-a11f-8104ea152c6a@li= nux.intel.com Cc: Dapeng Mi Fixes: a21864486f7e ("KVM: x86/pmu: Fix available_event_types check for REF= _CPU_CYCLES event") Signed-off-by: Sean Christopherson Reviewed-by: Jim Mattson Reviewed-by:=C2=A0 Dapeng Mi --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/kvm/pmu.c | 1 - arch/x86/kvm/pmu.h | 1 - arch/x86/kvm/svm/pmu.c | 6 ---- arch/x86/kvm/vmx/pmu_intel.c | 38 -------------------------- 5 files changed, 47 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/= kvm-x86-pmu-ops.h index 6c98f4bb4228..884af8ef7657 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -12,7 +12,6 @@ BUILD_BUG_ON(1) * a NULL definition, for example if "static_call_cond()" will be used * at the call sites. */ -KVM_X86_PMU_OP(hw_event_available) KVM_X86_PMU_OP(pmc_idx_to_pmc) KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) KVM_X86_PMU_OP(msr_idx_to_pmc) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 9ae07db6f0f6..99ed72966528 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -374,7 +374,6 @@ static bool check_pmu_event_filter(struct kvm_pmc *pmc) static bool pmc_event_is_allowed(struct kvm_pmc *pmc) { return pmc_is_globally_enabled(pmc) && pmc_speculative_in_use(pmc) && - static_call(kvm_x86_pmu_hw_event_available)(pmc) && check_pmu_event_filter(pmc); } =20 diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 5341e8f69a22..f3e7a356fd81 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -20,7 +20,6 @@ =20 struct kvm_pmu_ops { void (*init_pmu_capability)(void); - bool (*hw_event_available)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, unsigned int idx, u64 *mask); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 373ff6a6687b..5596fe816ea8 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -73,11 +73,6 @@ static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_= pmu *pmu, u32 msr, return amd_pmc_idx_to_pmc(pmu, idx); } =20 -static bool amd_hw_event_available(struct kvm_pmc *pmc) -{ - return true; -} - static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -249,7 +244,6 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) } =20 struct kvm_pmu_ops amd_pmu_ops __initdata =3D { - .hw_event_available =3D amd_hw_event_available, .pmc_idx_to_pmc =3D amd_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc =3D amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc =3D amd_msr_idx_to_pmc, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index b239e7dbdc9b..9bf700da1e17 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -140,43 +140,6 @@ static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm= _pmu *pmu, int pmc_idx) } } =20 -static bool intel_hw_event_available(struct kvm_pmc *pmc) -{ - struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); - u8 event_select =3D pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT; - u8 unit_mask =3D (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; - int i; - - /* - * Fixed counters are always available if KVM reaches this point. If a - * fixed counter is unsupported in hardware or guest CPUID, KVM doesn't - * allow the counter's corresponding MSR to be written. KVM does use - * architectural events to program fixed counters, as the interface to - * perf doesn't allow requesting a specific fixed counter, e.g. perf - * may (sadly) back a guest fixed PMC with a general purposed counter. - * But if _hardware_ doesn't support the associated event, KVM simply - * doesn't enumerate support for the fixed counter. - */ - if (pmc_is_fixed(pmc)) - return true; - - BUILD_BUG_ON(ARRAY_SIZE(intel_arch_events) !=3D NR_INTEL_ARCH_EVENTS); - - /* - * Disallow events reported as unavailable in guest CPUID. Note, this - * doesn't apply to pseudo-architectural events (see above). - */ - for (i =3D 0; i < NR_REAL_INTEL_ARCH_EVENTS; i++) { - if (intel_arch_events[i].eventsel !=3D event_select || - intel_arch_events[i].unit_mask !=3D unit_mask) - continue; - - return pmu->available_event_types & BIT(i); - } - - return true; -} - static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int i= dx) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -842,7 +805,6 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { .init_pmu_capability =3D intel_init_pmu_capability, - .hw_event_available =3D intel_hw_event_available, .pmc_idx_to_pmc =3D intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc =3D intel_rdpmc_ecx_to_pmc, .msr_idx_to_pmc =3D intel_msr_idx_to_pmc, --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 822F6C4332F for ; Sat, 4 Nov 2023 00:03:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231608AbjKDADG (ORCPT ); Fri, 3 Nov 2023 20:03:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231203AbjKDAC6 (ORCPT ); Fri, 3 Nov 2023 20:02:58 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92EAED62 for ; Fri, 3 Nov 2023 17:02:53 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-da040c021aeso3008165276.3 for ; Fri, 03 Nov 2023 17:02:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056172; x=1699660972; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=yY/rmfF8uWP2qcFcrSxU2iBcqr1KyrUXkO4fHTVenYU=; b=bVxgGu2lCXmKuMm5QSCv4s4eEQMRPejB9mbV+VIMt8rwNnEbc4fGpD9gfpa/rIO62D a9YtZYAMX9/ZVajKB5TnBX6lraaMPSTFQGbb3kyLxn0b6AFUdHezzYwQviGz2GydGkWr js0oeQM1pRmxbl+jlS/Kk5Im2HNFp2H3XTCuHjtroLJi3sJl7vLc6MNeJrBi73Y+RZw/ yanHmcJyR6NWW5VC96HE+sxYFKF/MkbkWAu43pvYUWD61Peq0k/g2ztgNUCEOmPR6Ez/ blcVDM8flPsc/ljnxrf6iaeVLAXE0pTXboK1+CrKOv01ZvOPz8i4fsyCGEIxQSpkV+fi /BWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056172; x=1699660972; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=yY/rmfF8uWP2qcFcrSxU2iBcqr1KyrUXkO4fHTVenYU=; b=Be2ESMbya+3/fkCULnf9dHKN+8EpcQQNEfllQiyKySNYKT7Jq8kDcq/3sH+QHIUAUg xrQyDa0de7EQc4f2vm8Xk2BNx9PW9cQpIG8PFg65B01lP8zohKGJkMxTWxMKiYUjEUKb FNeW3qKCxU9oxDqgmA4x6dI3vPjk3U4IPVrDyHMK1G6K77XBxlMEwNGVvXWTzgGqI7AF 4CR5Fh4ZZVCU2Be1N0/7Ti6Rcc+c//XRuwsjwPCDlg69/lyP7DRflcooZ1suOmblWml7 dVx8iDjCm9p7lUVK29I6msXMlLJcCvgSzd/KnEqD7leY+EemP0/WuIMtjHdgp22KqEfR 39uw== X-Gm-Message-State: AOJu0YyxeZX0neWBv3lDfaEB9xYFpS1p755F6cw7oiQOyLPFLi5WXPn9 cPeGECqChfrm/6GWaMqN5fvu4a4vmZM= X-Google-Smtp-Source: AGHT+IFwZt1P5Flriq9GqFcVYmLFgZ3LqYDtH2Fw5lrbDAOEtYZcr2cmtoQB2HW7yndqlTSKrdJ1ZHlMIX8= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:9011:0:b0:da0:4f83:60c1 with SMTP id s17-20020a259011000000b00da04f8360c1mr432157ybl.9.1699056172262; Fri, 03 Nov 2023 17:02:52 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:24 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-7-seanjc@google.com> Subject: [PATCH v6 06/20] KVM: selftests: Add vcpu_set_cpuid_property() to set properties From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Add vcpu_set_cpuid_property() helper function for setting properties, and use it instead of open coding an equivalent for MAX_PHY_ADDR. Future vPMU testcases will also need to stuff various CPUID properties. Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- .../testing/selftests/kvm/include/x86_64/processor.h | 4 +++- tools/testing/selftests/kvm/lib/x86_64/processor.c | 12 +++++++++--- .../kvm/x86_64/smaller_maxphyaddr_emulation_test.c | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 25bc61dac5fb..a01931f7d954 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -994,7 +994,9 @@ static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); } =20 -void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr); +void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, + struct kvm_x86_cpu_property property, + uint32_t value); =20 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function); void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/tes= ting/selftests/kvm/lib/x86_64/processor.c index d8288374078e..9e717bc6bd6d 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -752,11 +752,17 @@ void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const str= uct kvm_cpuid2 *cpuid) vcpu_set_cpuid(vcpu); } =20 -void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr) +void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, + struct kvm_x86_cpu_property property, + uint32_t value) { - struct kvm_cpuid_entry2 *entry =3D vcpu_get_cpuid_entry(vcpu, 0x80000008); + struct kvm_cpuid_entry2 *entry; + + entry =3D __vcpu_get_cpuid_entry(vcpu, property.function, property.index); + + (&entry->eax)[property.reg] &=3D ~GENMASK(property.hi_bit, property.lo_bi= t); + (&entry->eax)[property.reg] |=3D value << (property.lo_bit); =20 - entry->eax =3D (entry->eax & ~0xff) | maxphyaddr; vcpu_set_cpuid(vcpu); } =20 diff --git a/tools/testing/selftests/kvm/x86_64/smaller_maxphyaddr_emulatio= n_test.c b/tools/testing/selftests/kvm/x86_64/smaller_maxphyaddr_emulation_= test.c index 06edf00a97d6..9b89440dff19 100644 --- a/tools/testing/selftests/kvm/x86_64/smaller_maxphyaddr_emulation_test.c +++ b/tools/testing/selftests/kvm/x86_64/smaller_maxphyaddr_emulation_test.c @@ -63,7 +63,7 @@ int main(int argc, char *argv[]) vm_init_descriptor_tables(vm); vcpu_init_descriptor_tables(vcpu); =20 - vcpu_set_cpuid_maxphyaddr(vcpu, MAXPHYADDR); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_MAX_PHY_ADDR, MAXPHYADDR); =20 rc =3D kvm_check_cap(KVM_CAP_EXIT_ON_EMULATION_FAILURE); TEST_ASSERT(rc, "KVM_CAP_EXIT_ON_EMULATION_FAILURE is unavailable"); --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF4ECC4332F for ; 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Fri, 03 Nov 2023 17:02:54 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:25 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-8-seanjc@google.com> Subject: [PATCH v6 07/20] KVM: selftests: Drop the "name" param from KVM_X86_PMU_FEATURE() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the "name" parameter from KVM_X86_PMU_FEATURE(), it's unused and the name is redundant with the macro, i.e. it's truly useless. Signed-off-by: Sean Christopherson Reviewed-by: Jim Mattson --- tools/testing/selftests/kvm/include/x86_64/processor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index a01931f7d954..2d9771151dd9 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -289,7 +289,7 @@ struct kvm_x86_cpu_property { struct kvm_x86_pmu_feature { struct kvm_x86_cpu_feature anti_feature; }; -#define KVM_X86_PMU_FEATURE(name, __bit) \ +#define KVM_X86_PMU_FEATURE(__bit) \ ({ \ struct kvm_x86_pmu_feature feature =3D { \ .anti_feature =3D KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ @@ -298,7 +298,7 @@ struct kvm_x86_pmu_feature { feature; \ }) =20 -#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(BRANCH_IN= SNS_RETIRED, 5) +#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(5) =20 static inline unsigned int x86_family(unsigned int eax) { --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10B4CC4167D for ; Sat, 4 Nov 2023 00:03:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231790AbjKDADL (ORCPT ); Fri, 3 Nov 2023 20:03:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231226AbjKDAC7 (ORCPT ); Fri, 3 Nov 2023 20:02:59 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96F4619D for ; Fri, 3 Nov 2023 17:02:56 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1cc29f3afe0so20466135ad.2 for ; Fri, 03 Nov 2023 17:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056176; x=1699660976; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=L3Ph1WGBEgHW7QvmfHelm4EacJM/EhO7PSNkxK0HmCo=; b=DccDeXfiDvfv1fBWEzY45WjEbiOWdrzZaTNQV4f0F7uJwEyYRbB+VVZf9wIn1IeCTE iUVhrrFl/42ZXS4ylZj3+rYQbFEFxo1SVJWWPyw6CfR3I1AzEgsH+SlCQqrCiYl6GZT3 MYnHtkO1Fn1LmgGtqObBctRZ7WRfIotrQqHt7wIFyJ6lvVudHnoKz/0402GO07m1C12a sHT3RmqN+J7A0OQqLbzMuwW8AMKjv8b2iU4mDN4lZYLYNMqS72px5WI4hPFrDV50O/mF YQLqOd7nEQvgbLuV+RXSkqHYfMgwkEowuSi7XSedAqeNJUx291KThC4BoNpi5+JXYlXc jLvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056176; x=1699660976; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=L3Ph1WGBEgHW7QvmfHelm4EacJM/EhO7PSNkxK0HmCo=; b=s4nVTl8k1N+503Y/ykA5GXwm3hMrunDeloZYWHUEwb0pSyEg6AUNLO/S/jEOtLeGJv ESZFuJDX5r46Ce1RSVaN9Eijzok+gjHQiMGWNS2TLQmcgUJ39rJVRDP+YKTkB6S2Fq9Y TlHPe+GeC9kY/RL/TwovOQRvoijGkmNJW1yDDTJbQmGHkvB0UGh2GubamdKbhk6TCo3i SDeZAjkkdQj6VS8R/87/4pfPbwvvIo+w6cP25b5l1laJnRwqpzLUd0tMrzIgVqNo3LEi NvR+mC7wgosr9tASfSITQVojthb+GOY+4AQdjG57G/6UUaYHC0n8hUHNvgn8sFaRTIQC IVFA== X-Gm-Message-State: AOJu0Yz/0iFiD/iTBuw7ROlUUnxeZ5/2L5k8k0tcWvrClhaZcNRtfFc3 aDcNuQlAyEgsgzqDwuu3wpYb+1fyupA= X-Google-Smtp-Source: AGHT+IF+xtFGk+3kSZATAuvt1FOAxavnxlitpSZmorzLd17NCJnmNvLwfKoliM6+iK7h6vXq068eMlQgu0k= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:d301:b0:1cc:32c6:e5d4 with SMTP id b1-20020a170902d30100b001cc32c6e5d4mr312291plc.6.1699056176128; Fri, 03 Nov 2023 17:02:56 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:26 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-9-seanjc@google.com> Subject: [PATCH v6 08/20] KVM: selftests: Extend {kvm,this}_pmu_has() to support fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the kvm_x86_pmu_feature framework to allow querying for fixed counters via {kvm,this}_pmu_has(). Like architectural events, checking for a fixed counter annoyingly requires checking multiple CPUID fields, as a fixed counter exists if: FxCtr[i]_is_supported :=3D ECX[i] || (EDX[4:0] > i); Note, KVM currently doesn't actually support exposing fixed counters via the bitmask, but that will hopefully change sooner than later, and Intel's SDM explicitly "recommends" checking both the number of counters and the mask. Rename the intermedate "anti_feature" field to simply 'f' since the fixed counter bitmask (thankfully) doesn't have reversed polarity like the architectural events bitmask. Note, ideally the helpers would use BUILD_BUG_ON() to assert on the incoming register, but the expected usage in PMU tests can't guarantee the inputs are compile-time constants. Opportunistically define macros for all of the architectural events and fixed counters that KVM currently supports. Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/x86_64/processor.h | 63 +++++++++++++------ 1 file changed, 45 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 2d9771151dd9..b103c462701b 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -281,24 +281,39 @@ struct kvm_x86_cpu_property { * that indicates the feature is _not_ supported, and a property that stat= es * the length of the bit mask of unsupported features. A feature is suppo= rted * if the size of the bit mask is larger than the "unavailable" bit, and s= aid - * bit is not set. + * bit is not set. Fixed counters also bizarre enumeration, but inverted = from + * arch events for general purpose counters. Fixed counters are supported= if a + * feature flag is set **OR** the total number of fixed counters is greater + * than index of the counter. * - * Wrap the "unavailable" feature to simplify checking whether or not a gi= ven - * architectural event is supported. + * Wrap the events for general purpose and fixed counters to simplify chec= king + * whether or not a given architectural event is supported. */ struct kvm_x86_pmu_feature { - struct kvm_x86_cpu_feature anti_feature; + struct kvm_x86_cpu_feature f; }; -#define KVM_X86_PMU_FEATURE(__bit) \ -({ \ - struct kvm_x86_pmu_feature feature =3D { \ - .anti_feature =3D KVM_X86_CPU_FEATURE(0xa, 0, EBX, __bit), \ - }; \ - \ - feature; \ +#define KVM_X86_PMU_FEATURE(__reg, __bit) \ +({ \ + struct kvm_x86_pmu_feature feature =3D { \ + .f =3D KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ + }; \ + \ + kvm_static_assert(KVM_CPUID_##__reg =3D=3D KVM_CPUID_EBX || \ + KVM_CPUID_##__reg =3D=3D KVM_CPUID_ECX); \ + feature; \ }) =20 -#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(5) +#define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) +#define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) +#define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) +#define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) +#define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) +#define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) +#define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) + +#define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) +#define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) +#define X86_PMU_FEATURE_REFERENCE_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) =20 static inline unsigned int x86_family(unsigned int eax) { @@ -697,10 +712,16 @@ static __always_inline bool this_cpu_has_p(struct kvm= _x86_cpu_property property) =20 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LE= NGTH); + uint32_t nr_bits; =20 - return nr_bits > feature.anti_feature.bit && - !this_cpu_has(feature.anti_feature); + if (feature.f.reg =3D=3D KVM_CPUID_EBX) { + nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.f.bit && !this_cpu_has(feature.f); + } + + GUEST_ASSERT(feature.f.reg =3D=3D KVM_CPUID_ECX); + nr_bits =3D this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.f.bit || this_cpu_has(feature.f); } =20 static __always_inline uint64_t this_cpu_supported_xcr0(void) @@ -916,10 +937,16 @@ static __always_inline bool kvm_cpu_has_p(struct kvm_= x86_cpu_property property) =20 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) { - uint32_t nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LEN= GTH); + uint32_t nr_bits; =20 - return nr_bits > feature.anti_feature.bit && - !kvm_cpu_has(feature.anti_feature); + if (feature.f.reg =3D=3D KVM_CPUID_EBX) { + nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); + return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); + } + + TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); + nr_bits =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); + return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); } =20 static __always_inline uint64_t kvm_cpu_supported_xcr0(void) --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04C45C4332F for ; Sat, 4 Nov 2023 00:03:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231836AbjKDADN (ORCPT ); Fri, 3 Nov 2023 20:03:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231629AbjKDADG (ORCPT ); Fri, 3 Nov 2023 20:03:06 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC1AE5 for ; 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bh=1N0GaX165iT66psQLFguu13B6wTdKAbnF/+ecMums54=; b=r+BRf8vDTeCiAqkhG8KkKE9iro3kNk5PjXOjwo96FJ3J5sg6Lns37BnE1KP5+bj6gK nwdCeekZ13U5bJVgFWNdk1vYOz5H1WJxxBia1mv/eG2wtXm3PimeDUazPoz2HNXKuOGi Qd3BIePmtgd0dV+ZoshglBCOcJM1K0NqERcqDRsd8xQIO+moPt+SzqLclmHpMteGAlmm YKpE3C8Dnw+b5/Ma9Nr4XKq6O0oFa6NC3z9mlQbmlFMl1C2mP2E/fnyu/zkT994oIqmD Vv39C/WGtKVauXfhM3ST2PAWQo/gQj48KbglqDZd3sTMNwu/hQwQiXcyEwLUP0pHg3gG 0fBg== X-Gm-Message-State: AOJu0YxgFN8Qi1OjrK7+D54sfrZes9qSHgVyuJF3aJfSHSu6N05c2ZOg UEETc1/tyKtkmR8KMuiwltlUCUSBjrs= X-Google-Smtp-Source: AGHT+IEQjT2v/PU5SLXROqSmaHsqanMiphnmX9YeDXgxUYF3idGqF/qqTh4wXE7Jcor4gDmM+946Bm8RILI= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:5c2:0:b0:d9a:68de:16a1 with SMTP id 185-20020a2505c2000000b00d9a68de16a1mr458880ybf.0.1699056178051; Fri, 03 Nov 2023 17:02:58 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:27 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-10-seanjc@google.com> Subject: [PATCH v6 09/20] KVM: selftests: Add pmu.h and lib/pmu.c for common PMU assets From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang By defining the PMU performance events and masks relevant for x86 in the new pmu.h and pmu.c, it becomes easier to reference them, minimizing potential errors in code that handles these values. Clean up pmu_event_filter_test.c by including pmu.h and removing unnecessary macros. Suggested-by: Sean Christopherson Signed-off-by: Jinrong Liang [sean: drop PSEUDO_ARCH_REFERENCE_CYCLES] Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/Makefile | 1 + tools/testing/selftests/kvm/include/pmu.h | 84 +++++++++++++++++++ tools/testing/selftests/kvm/lib/pmu.c | 28 +++++++ .../kvm/x86_64/pmu_event_filter_test.c | 32 ++----- 4 files changed, 122 insertions(+), 23 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/pmu.h create mode 100644 tools/testing/selftests/kvm/lib/pmu.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index a5963ab9215b..44d8d022b023 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -32,6 +32,7 @@ LIBKVM +=3D lib/guest_modes.c LIBKVM +=3D lib/io.c LIBKVM +=3D lib/kvm_util.c LIBKVM +=3D lib/memstress.c +LIBKVM +=3D lib/pmu.c LIBKVM +=3D lib/guest_sprintf.c LIBKVM +=3D lib/rbtree.c LIBKVM +=3D lib/sparsebit.c diff --git a/tools/testing/selftests/kvm/include/pmu.h b/tools/testing/self= tests/kvm/include/pmu.h new file mode 100644 index 000000000000..987602c62b51 --- /dev/null +++ b/tools/testing/selftests/kvm/include/pmu.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, Tencent, Inc. + */ +#ifndef SELFTEST_KVM_PMU_H +#define SELFTEST_KVM_PMU_H + +#include + +#define X86_PMC_IDX_MAX 64 +#define INTEL_PMC_MAX_GENERIC 32 +#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300 + +#define GP_COUNTER_NR_OFS_BIT 8 +#define EVENT_LENGTH_OFS_BIT 24 + +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) +#define EVENT_LENGTH_MASK GENMASK_ULL(31, EVENT_LENGTH_OFS_BIT) +#define GP_COUNTER_NR_MASK GENMASK_ULL(15, GP_COUNTER_NR_OFS_BIT) +#define FIXED_COUNTER_NR_MASK GENMASK_ULL(4, 0) + +#define ARCH_PERFMON_EVENTSEL_EVENT GENMASK_ULL(7, 0) +#define ARCH_PERFMON_EVENTSEL_UMASK GENMASK_ULL(15, 8) +#define ARCH_PERFMON_EVENTSEL_USR BIT_ULL(16) +#define ARCH_PERFMON_EVENTSEL_OS BIT_ULL(17) +#define ARCH_PERFMON_EVENTSEL_EDGE BIT_ULL(18) +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL BIT_ULL(19) +#define ARCH_PERFMON_EVENTSEL_INT BIT_ULL(20) +#define ARCH_PERFMON_EVENTSEL_ANY BIT_ULL(21) +#define ARCH_PERFMON_EVENTSEL_ENABLE BIT_ULL(22) +#define ARCH_PERFMON_EVENTSEL_INV BIT_ULL(23) +#define ARCH_PERFMON_EVENTSEL_CMASK GENMASK_ULL(31, 24) + +#define PMC_MAX_FIXED 16 +#define PMC_IDX_FIXED 32 + +/* RDPMC offset for Fixed PMCs */ +#define PMC_FIXED_RDPMC_BASE BIT_ULL(30) +#define PMC_FIXED_RDPMC_METRICS BIT_ULL(29) + +#define FIXED_BITS_MASK 0xFULL +#define FIXED_BITS_STRIDE 4 +#define FIXED_0_KERNEL BIT_ULL(0) +#define FIXED_0_USER BIT_ULL(1) +#define FIXED_0_ANYTHREAD BIT_ULL(2) +#define FIXED_0_ENABLE_PMI BIT_ULL(3) + +#define fixed_bits_by_idx(_idx, _bits) \ + ((_bits) << ((_idx) * FIXED_BITS_STRIDE)) + +#define AMD64_NR_COUNTERS 4 +#define AMD64_NR_COUNTERS_CORE 6 + +#define PMU_CAP_FW_WRITES BIT_ULL(13) +#define PMU_CAP_LBR_FMT 0x3f + +enum intel_pmu_architectural_events { + /* + * The order of the architectural events matters as support for each + * event is enumerated via CPUID using the index of the event. + */ + INTEL_ARCH_CPU_CYCLES, + INTEL_ARCH_INSTRUCTIONS_RETIRED, + INTEL_ARCH_REFERENCE_CYCLES, + INTEL_ARCH_LLC_REFERENCES, + INTEL_ARCH_LLC_MISSES, + INTEL_ARCH_BRANCHES_RETIRED, + INTEL_ARCH_BRANCHES_MISPREDICTED, + NR_INTEL_ARCH_EVENTS, +}; + +enum amd_pmu_k7_events { + AMD_ZEN_CORE_CYCLES, + AMD_ZEN_INSTRUCTIONS, + AMD_ZEN_BRANCHES, + AMD_ZEN_BRANCH_MISSES, + NR_AMD_ARCH_EVENTS, +}; + +extern const uint64_t intel_pmu_arch_events[]; +extern const uint64_t amd_pmu_arch_events[]; +extern const int intel_pmu_fixed_pmc_events[]; + +#endif /* SELFTEST_KVM_PMU_H */ diff --git a/tools/testing/selftests/kvm/lib/pmu.c b/tools/testing/selftest= s/kvm/lib/pmu.c new file mode 100644 index 000000000000..27a6c35f98a1 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/pmu.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Tencent, Inc. + */ + +#include + +#include "pmu.h" + +/* Definitions for Architectural Performance Events */ +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) <<= 8) + +const uint64_t intel_pmu_arch_events[] =3D { + [INTEL_ARCH_CPU_CYCLES] =3D ARCH_EVENT(0x3c, 0x0), + [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D ARCH_EVENT(0xc0, 0x0), + [INTEL_ARCH_REFERENCE_CYCLES] =3D ARCH_EVENT(0x3c, 0x1), + [INTEL_ARCH_LLC_REFERENCES] =3D ARCH_EVENT(0x2e, 0x4f), + [INTEL_ARCH_LLC_MISSES] =3D ARCH_EVENT(0x2e, 0x41), + [INTEL_ARCH_BRANCHES_RETIRED] =3D ARCH_EVENT(0xc4, 0x0), + [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D ARCH_EVENT(0xc5, 0x0), +}; + +const uint64_t amd_pmu_arch_events[] =3D { + [AMD_ZEN_CORE_CYCLES] =3D ARCH_EVENT(0x76, 0x00), + [AMD_ZEN_INSTRUCTIONS] =3D ARCH_EVENT(0xc0, 0x00), + [AMD_ZEN_BRANCHES] =3D ARCH_EVENT(0xc2, 0x00), + [AMD_ZEN_BRANCH_MISSES] =3D ARCH_EVENT(0xc3, 0x00), +}; diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/t= ools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index 283cc55597a4..b6e4f57a8651 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -11,31 +11,18 @@ */ =20 #define _GNU_SOURCE /* for program_invocation_short_name */ -#include "test_util.h" + #include "kvm_util.h" +#include "pmu.h" #include "processor.h" - -/* - * In lieu of copying perf_event.h into tools... - */ -#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) -#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) - -/* End of stuff taken from perf_event.h. */ - -/* Oddly, this isn't in perf_event.h. */ -#define ARCH_PERFMON_BRANCHES_RETIRED 5 +#include "test_util.h" =20 #define NUM_BRANCHES 42 -#define INTEL_PMC_IDX_FIXED 32 - -/* Matches KVM_PMU_EVENT_FILTER_MAX_EVENTS in pmu.c */ -#define MAX_FILTER_EVENTS 300 #define MAX_TEST_EVENTS 10 =20 #define PMU_EVENT_FILTER_INVALID_ACTION (KVM_PMU_EVENT_DENY + 1) #define PMU_EVENT_FILTER_INVALID_FLAGS (KVM_PMU_EVENT_FLAGS_VALID_MASK <= < 1) -#define PMU_EVENT_FILTER_INVALID_NEVENTS (MAX_FILTER_EVENTS + 1) +#define PMU_EVENT_FILTER_INVALID_NEVENTS (KVM_PMU_EVENT_FILTER_MAX_EVENTS= + 1) =20 /* * This is how the event selector and unit mask are stored in an AMD @@ -63,7 +50,6 @@ =20 #define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0) =20 - /* * "Retired instructions", from Processor Programming Reference * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors, @@ -84,7 +70,7 @@ struct __kvm_pmu_event_filter { __u32 fixed_counter_bitmap; __u32 flags; __u32 pad[4]; - __u64 events[MAX_FILTER_EVENTS]; + __u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; }; =20 /* @@ -729,14 +715,14 @@ static void add_dummy_events(uint64_t *events, int ne= vents) =20 static void test_masked_events(struct kvm_vcpu *vcpu) { - int nevents =3D MAX_FILTER_EVENTS - MAX_TEST_EVENTS; - uint64_t events[MAX_FILTER_EVENTS]; + int nevents =3D KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS; + uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS]; =20 /* Run the test cases against a sparse PMU event filter. */ run_masked_events_tests(vcpu, events, 0); =20 /* Run the test cases against a dense PMU event filter. */ - add_dummy_events(events, MAX_FILTER_EVENTS); + add_dummy_events(events, KVM_PMU_EVENT_FILTER_MAX_EVENTS); run_masked_events_tests(vcpu, events, nevents); } =20 @@ -818,7 +804,7 @@ static void intel_run_fixed_counter_guest_code(uint8_t = fixed_ctr_idx) /* Only OS_EN bit is enabled for fixed counter[idx]. */ wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * fixed_ctr_idx)); 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charset="utf-8" From: Jinrong Liang Add test cases to verify that Intel's Architectural PMU events work as expected when the are (un)available according to guest CPUID. Iterate over a range of sane PMU versions, with and without full-width writes enabled, and over interesting combinations of lengths/masks for the bit vector that enumerates unavailable events. Test up to vPMU version 5, i.e. the current architectural max. KVM only officially supports up to version 2, but the behavior of the counters is backwards compatible, i.e. KVM shouldn't do something completely different for a higher, architecturally-defined vPMU version. Verify KVM behavior against the effective vPMU version, e.g. advertising vPMU 5 when KVM only supports vPMU 2 shouldn't magically unlock vPMU 5 features. According to Intel SDM, the number of architectural events is reported through CPUID.0AH:EAX[31:24] and the architectural event x is supported if EBX[x]=3D0 && EAX[31:24]>x. Note, KVM's ABI is that unavailable events do not count, even though strictly speaking that's not required by the SDM (the behavior is effectively undefined). Handcode the entirety of the measured section so that the test can precisely assert on the number of instructions and branches retired. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/x86_64/pmu_counters_test.c | 321 ++++++++++++++++++ 2 files changed, 322 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/pmu_counters_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 44d8d022b023..09f5d6fe84de 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -91,6 +91,7 @@ TEST_GEN_PROGS_x86_64 +=3D x86_64/mmio_warning_test TEST_GEN_PROGS_x86_64 +=3D x86_64/monitor_mwait_test TEST_GEN_PROGS_x86_64 +=3D x86_64/nested_exceptions_test TEST_GEN_PROGS_x86_64 +=3D x86_64/platform_info_test +TEST_GEN_PROGS_x86_64 +=3D x86_64/pmu_counters_test TEST_GEN_PROGS_x86_64 +=3D x86_64/pmu_event_filter_test TEST_GEN_PROGS_x86_64 +=3D x86_64/set_boot_cpu_id TEST_GEN_PROGS_x86_64 +=3D x86_64/set_sregs_test diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c new file mode 100644 index 000000000000..dd9a7864410c --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Tencent, Inc. + */ + +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include + +#include "pmu.h" +#include "processor.h" + +/* Number of LOOP instructions for the guest measurement payload. */ +#define NUM_BRANCHES 10 +/* + * Number of "extra" instructions that will be counted, i.e. the number of + * instructions that are needed to set up the loop and then disabled the + * counter. 2 MOV, 2 XOR, 1 WRMSR. + */ +#define NUM_EXTRA_INSNS 5 +#define NUM_INSNS_RETIRED (NUM_BRANCHES + NUM_EXTRA_INSNS) + +static uint8_t kvm_pmu_version; +static bool kvm_has_perf_caps; + +static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, + void *guest_code, + uint8_t pmu_version, + uint64_t perf_capabilities) +{ + struct kvm_vm *vm; + + vm =3D vm_create_with_one_vcpu(vcpu, guest_code); + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(*vcpu); + + sync_global_to_guest(vm, kvm_pmu_version); + + /* + * Set PERF_CAPABILITIES before PMU version as KVM disallows enabling + * features via PERF_CAPABILITIES if the guest doesn't have a vPMU. + */ + if (kvm_has_perf_caps) + vcpu_set_msr(*vcpu, MSR_IA32_PERF_CAPABILITIES, perf_capabilities); + + vcpu_set_cpuid_property(*vcpu, X86_PROPERTY_PMU_VERSION, pmu_version); + return vm; +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + do { + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_SYNC: + break; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_PRINTF: + pr_info("%s", uc.buffer); + break; + case UCALL_DONE: + break; + default: + TEST_FAIL("Unexpected ucall: %lu", uc.cmd); + } + } while (uc.cmd !=3D UCALL_DONE); +} + +static uint8_t guest_get_pmu_version(void) +{ + /* + * Return the effective PMU version, i.e. the minimum between what KVM + * supports and what is enumerated to the guest. The host deliberately + * advertises a PMU version to the guest beyond what is actually + * supported by KVM to verify KVM doesn't freak out and do something + * bizarre with an architecturally valid, but unsupported, version. + */ + return min_t(uint8_t, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU= _VERSION)); +} + +/* + * If an architectural event is supported and guaranteed to generate at le= ast + * one "hit, assert that its count is non-zero. If an event isn't support= ed or + * the test can't guarantee the associated action will occur, then all bet= s are + * off regarding the count, i.e. no checks can be done. + * + * Sanity check that in all cases, the event doesn't count when it's disab= led, + * and that KVM correctly emulates the write of an arbitrary value. + */ +static void guest_assert_event_count(uint8_t idx, + struct kvm_x86_pmu_feature event, + uint32_t pmc, uint32_t pmc_msr) +{ + uint64_t count; + + count =3D _rdpmc(pmc); + if (!this_pmu_has(event)) + goto sanity_checks; + + switch (idx) { + case INTEL_ARCH_INSTRUCTIONS_RETIRED: + GUEST_ASSERT_EQ(count, NUM_INSNS_RETIRED); + break; + case INTEL_ARCH_BRANCHES_RETIRED: + GUEST_ASSERT_EQ(count, NUM_BRANCHES); + break; + case INTEL_ARCH_CPU_CYCLES: + case INTEL_ARCH_REFERENCE_CYCLES: + GUEST_ASSERT_NE(count, 0); + break; + default: + break; + } + +sanity_checks: + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + GUEST_ASSERT_EQ(_rdpmc(pmc), count); + + wrmsr(pmc_msr, 0xdead); + GUEST_ASSERT_EQ(_rdpmc(pmc), 0xdead); +} + +static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_featur= e event, + uint32_t pmc, uint32_t pmc_msr, + uint32_t ctrl_msr, uint64_t ctrl_msr_value) +{ + wrmsr(pmc_msr, 0); + + /* + * Enable and disable the PMC in a monolithic asm blob to ensure that + * the compiler can't insert _any_ code into the measured sequence. + * Note, ECX doesn't need to be clobbered as the input value, @pmc_msr, + * is restored before the end of the sequence. + */ + __asm__ __volatile__("wrmsr\n\t" + "mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" + "loop .\n\t" + "mov %%edi, %%ecx\n\t" + "xor %%eax, %%eax\n\t" + "xor %%edx, %%edx\n\t" + "wrmsr\n\t" + :: "a"((uint32_t)ctrl_msr_value), + "d"(ctrl_msr_value >> 32), + "c"(ctrl_msr), "D"(ctrl_msr) + ); + + guest_assert_event_count(idx, event, pmc, pmc_msr); +} + +static void guest_test_arch_event(uint8_t idx) +{ + const struct { + struct kvm_x86_pmu_feature gp_event; + } intel_event_to_feature[] =3D { + [INTEL_ARCH_CPU_CYCLES] =3D { X86_PMU_FEATURE_CPU_CYCLES }, + [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D { X86_PMU_FEATURE_INSNS_RETIRED }, + [INTEL_ARCH_REFERENCE_CYCLES] =3D { X86_PMU_FEATURE_REFERENCE_CYCLES = }, + [INTEL_ARCH_LLC_REFERENCES] =3D { X86_PMU_FEATURE_LLC_REFERENCES }, + [INTEL_ARCH_LLC_MISSES] =3D { X86_PMU_FEATURE_LLC_MISSES }, + [INTEL_ARCH_BRANCHES_RETIRED] =3D { X86_PMU_FEATURE_BRANCH_INSNS_RETI= RED }, + [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D { X86_PMU_FEATURE_BRANCHES_MISPRE= DICTED }, + }; + + uint32_t nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUN= TERS); + uint32_t pmu_version =3D guest_get_pmu_version(); + /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ + bool guest_has_perf_global_ctrl =3D pmu_version >=3D 2; + struct kvm_x86_pmu_feature gp_event; + uint32_t base_pmc_msr; + unsigned int i; + + /* The host side shouldn't invoke this without a guest PMU. */ + GUEST_ASSERT(pmu_version); + + if (this_cpu_has(X86_FEATURE_PDCM) && + rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + base_pmc_msr =3D MSR_IA32_PMC0; + else + base_pmc_msr =3D MSR_IA32_PERFCTR0; + + gp_event =3D intel_event_to_feature[idx].gp_event; + GUEST_ASSERT_EQ(idx, gp_event.f.bit); + + GUEST_ASSERT(nr_gp_counters); + + for (i =3D 0; i < nr_gp_counters; i++) { + uint64_t eventsel =3D ARCH_PERFMON_EVENTSEL_OS | + ARCH_PERFMON_EVENTSEL_ENABLE | + intel_pmu_arch_events[idx]; + + wrmsr(MSR_P6_EVNTSEL0 + i, 0); + if (guest_has_perf_global_ctrl) + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); + + __guest_test_arch_event(idx, gp_event, i, base_pmc_msr + i, + MSR_P6_EVNTSEL0 + i, eventsel); + } +} + +static void guest_test_arch_events(void) +{ + uint8_t i; + + for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) + guest_test_arch_event(i); + + GUEST_DONE(); +} + +static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabiliti= es, + uint8_t length, uint32_t unavailable_mask) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + /* Testing arch events requires a vPMU (there are no negative tests). */ + if (!pmu_version) + return; + + vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_arch_events, + pmu_version, perf_capabilities); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH, + length); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK, + unavailable_mask); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + +static void test_intel_counters(void) +{ + uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + unsigned int i; + uint8_t v, j; + uint32_t k; + + const uint64_t perf_caps[] =3D { + 0, + PMU_CAP_FW_WRITES, + }; + + /* + * Test up to PMU v5, which is the current maximum version defined by + * Intel, i.e. is the last version that is guaranteed to be backwards + * compatible with KVM's existing behavior. + */ + uint8_t max_pmu_version =3D max_t(typeof(pmu_version), pmu_version, 5); + + /* + * Verify that KVM is sanitizing the architectural events, i.e. hiding + * events that KVM doesn't support. This will fail any time KVM adds + * support for a new event, but it's worth paying that price to be able + * to detect KVM bugs. + */ + TEST_ASSERT(nr_arch_events <=3D NR_INTEL_ARCH_EVENTS, + "KVM is either buggy, or has learned new tricks (length =3D %u, mask= =3D %x)", + nr_arch_events, kvm_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); + + /* + * Force iterating over known arch events regardless of whether or not + * KVM/hardware supports a given event. + */ + nr_arch_events =3D max_t(typeof(nr_arch_events), nr_arch_events, NR_INTEL= _ARCH_EVENTS); + + for (v =3D 0; v <=3D max_pmu_version; v++) { + for (i =3D 0; i < ARRAY_SIZE(perf_caps); i++) { + if (!kvm_has_perf_caps && perf_caps[i]) + continue; + + pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", + v, perf_caps[i]); + /* + * To keep the total runtime reasonable, test every + * possible non-zero, non-reserved bitmap combination + * only with the native PMU version and the full bit + * vector length. + */ + if (v =3D=3D pmu_version) { + for (k =3D 1; k < (BIT(nr_arch_events) - 1); k++) + test_arch_events(v, perf_caps[i], nr_arch_events, k); + } + /* + * Test single bits for all PMU version and lengths up + * the number of events +1 (to verify KVM doesn't do + * weird things if the guest length is greater than the + * host length). Explicitly test a mask of '0' and all + * ones i.e. all events being available and unavailable. + */ + for (j =3D 0; j <=3D nr_arch_events + 1; j++) { + test_arch_events(v, perf_caps[i], j, 0); + test_arch_events(v, perf_caps[i], j, -1u); + + for (k =3D 0; k < nr_arch_events; k++) + test_arch_events(v, perf_caps[i], j, BIT(k)); + } + } + } +} + +int main(int argc, char *argv[]) +{ + TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + + TEST_REQUIRE(host_cpu_is_intel); + TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + + kvm_pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + kvm_has_perf_caps =3D kvm_cpu_has(X86_FEATURE_PDCM); + + test_intel_counters(); + + return 0; +} --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C8D2C4332F for ; Sat, 4 Nov 2023 00:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231888AbjKDADb (ORCPT ); Fri, 3 Nov 2023 20:03:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230525AbjKDADH (ORCPT ); Fri, 3 Nov 2023 20:03:07 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C6BB10C7 for ; Fri, 3 Nov 2023 17:03:02 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1cc1ddb34ccso20498015ad.1 for ; Fri, 03 Nov 2023 17:03:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1699056181; x=1699660981; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=huxX/xt+b9dPHfuMpHR5dh+UJzcxoKeSK8eYFJnQY04=; b=xyWlo+0PhDtyZBfITYk1h+NiUbcJlkmoXY7aNJO0GYNnJYonbNcZqCLrmzbG0ShycX cFsFpC85m89eHUXRtRhrTlYbfCQje4Xxs4mApvouuKRzz8otwv1XJK9iDI5cQEGw8TRJ vUD0rfzI6F6ZQRswQvQDbIGd/xcNBQP4FsHtCALMSxPRKdQ2K/8uJJmydUOpvTUK1CW2 JMDQ4YQuo17Jf09Yg8LLPF149noJA4jN3f8j2ZKMdLTwIs+xo5xuv26fSOQmml3ZAlKg SwKjL9j9DLbV6LO2CFHHRNtdxokBJDiKl3niVQ3ZrswB2/AWqVU5Ly7szIkBoDQYteKl vBGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699056181; x=1699660981; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=huxX/xt+b9dPHfuMpHR5dh+UJzcxoKeSK8eYFJnQY04=; b=eq5yXQc1XXmdEpdnGhqyzQxgnRDpceBeVd5FT9cZvFCTUvgjXyX5irRh+d9KCXYXNe 2zI05A2c6cpTHcfG1SWt68mqU5PgDqDc6GFSBf7u01d/1hr63/uM36aI7fQZQxj23W7l jqfvg8iHLX+KleafgMlFOLbjHBjHhkmne6mFjwg8G2ZZB/u4sSdr2q9syU7HnaGbOT14 bA4If+48wYj8Q3byEosu7nxofZP9OChJ0+zAZY7novs3UHm66acDAE7spFc/m6wd5qYd 1cJuuK1p+bm2GdxMCGVMUo0Zsm8Q9fY7OkZl8C6ObvDIAes8FoG+BsvH4g9FQWyAvFzT 1cDw== X-Gm-Message-State: AOJu0Yyboc0Dwa9VkntckP5YS2Xbte9jKAP1WcoTMUsBxgCh6ASVXiuo lZpddenMMqL4xXJiq6sGXJeXqxjnCKw= X-Google-Smtp-Source: AGHT+IFB1K09JzPWaQ59nalHXl5/iog4zxKzuE/c4guWe8d0N5OC3W/euaS1KW35bpmUHU00WC2Y0XCYMKY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:efd1:b0:1c6:2b9d:570b with SMTP id ja17-20020a170902efd100b001c62b9d570bmr414318plb.7.1699056181585; Fri, 03 Nov 2023 17:03:01 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:29 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-12-seanjc@google.com> Subject: [PATCH v6 11/20] KVM: selftests: Test Intel PMU architectural events on fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Extend the PMU counters test to validate architectural events using fixed counters. The core logic is largely the same, the biggest difference being that if a fixed counter exists, its associated event is available (the SDM doesn't explicitly state this to be true, but it's KVM's ABI and letting software program a fixed counter that doesn't actually count would be quite bizarre). Note, fixed counters rely on PERF_GLOBAL_CTRL. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson Reviewed-by: Jim Mattson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 53 ++++++++++++++++--- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index dd9a7864410c..4d3a5c94b8ba 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -150,25 +150,46 @@ static void __guest_test_arch_event(uint8_t idx, stru= ct kvm_x86_pmu_feature even guest_assert_event_count(idx, event, pmc, pmc_msr); } =20 +#define X86_PMU_FEATURE_NULL \ +({ \ + struct kvm_x86_pmu_feature feature =3D {}; \ + \ + feature; \ +}) + +static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) +{ + return !(*(u64 *)&event); +} + static void guest_test_arch_event(uint8_t idx) { const struct { struct kvm_x86_pmu_feature gp_event; + struct kvm_x86_pmu_feature fixed_event; } intel_event_to_feature[] =3D { - [INTEL_ARCH_CPU_CYCLES] =3D { X86_PMU_FEATURE_CPU_CYCLES }, - [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D { X86_PMU_FEATURE_INSNS_RETIRED }, - [INTEL_ARCH_REFERENCE_CYCLES] =3D { X86_PMU_FEATURE_REFERENCE_CYCLES = }, - [INTEL_ARCH_LLC_REFERENCES] =3D { X86_PMU_FEATURE_LLC_REFERENCES }, - [INTEL_ARCH_LLC_MISSES] =3D { X86_PMU_FEATURE_LLC_MISSES }, - [INTEL_ARCH_BRANCHES_RETIRED] =3D { X86_PMU_FEATURE_BRANCH_INSNS_RETI= RED }, - [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D { X86_PMU_FEATURE_BRANCHES_MISPRE= DICTED }, + [INTEL_ARCH_CPU_CYCLES] =3D { X86_PMU_FEATURE_CPU_CYCLES, X86_PMU_FE= ATURE_CPU_CYCLES_FIXED }, + [INTEL_ARCH_INSTRUCTIONS_RETIRED] =3D { X86_PMU_FEATURE_INSNS_RETIRED, = X86_PMU_FEATURE_INSNS_RETIRED_FIXED }, + /* + * Note, the fixed counter for reference cycles is NOT the same + * as the general purpose architectural event (because the GP + * event is garbage). The fixed counter explicitly counts at + * the same frequency as the TSC, whereas the GP event counts + * at a fixed, but uarch specific, frequency. Bundle them here + * for simplicity. + */ + [INTEL_ARCH_REFERENCE_CYCLES] =3D { X86_PMU_FEATURE_REFERENCE_CYCLES,= X86_PMU_FEATURE_REFERENCE_CYCLES_FIXED }, + [INTEL_ARCH_LLC_REFERENCES] =3D { X86_PMU_FEATURE_LLC_REFERENCES, X86= _PMU_FEATURE_NULL }, + [INTEL_ARCH_LLC_MISSES] =3D { X86_PMU_FEATURE_LLC_MISSES, X86_PMU_FE= ATURE_NULL }, + [INTEL_ARCH_BRANCHES_RETIRED] =3D { X86_PMU_FEATURE_BRANCH_INSNS_RETI= RED, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_BRANCHES_MISPREDICTED] =3D { X86_PMU_FEATURE_BRANCHES_MISPRE= DICTED, X86_PMU_FEATURE_NULL }, }; =20 uint32_t nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUN= TERS); uint32_t pmu_version =3D guest_get_pmu_version(); /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ bool guest_has_perf_global_ctrl =3D pmu_version >=3D 2; - struct kvm_x86_pmu_feature gp_event; + struct kvm_x86_pmu_feature gp_event, fixed_event; uint32_t base_pmc_msr; unsigned int i; =20 @@ -198,6 +219,22 @@ static void guest_test_arch_event(uint8_t idx) __guest_test_arch_event(idx, gp_event, i, base_pmc_msr + i, MSR_P6_EVNTSEL0 + i, eventsel); } + + if (!guest_has_perf_global_ctrl) + return; + + fixed_event =3D intel_event_to_feature[idx].fixed_event; + if (pmu_is_null_feature(fixed_event) || !this_pmu_has(fixed_event)) + return; + + i =3D fixed_event.f.bit; + + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + + __guest_test_arch_event(idx, fixed_event, PMC_FIXED_RDPMC_BASE | i, + MSR_CORE_PERF_FIXED_CTR0 + i, + MSR_CORE_PERF_GLOBAL_CTRL, + BIT_ULL(PMC_IDX_FIXED + i)); } =20 static void guest_test_arch_events(void) --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F9DC4332F for ; Sat, 4 Nov 2023 00:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232238AbjKDADe (ORCPT ); Fri, 3 Nov 2023 20:03:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231672AbjKDAD2 (ORCPT ); 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Fri, 03 Nov 2023 17:03:03 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:30 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-13-seanjc@google.com> Subject: [PATCH v6 12/20] KVM: selftests: Test consistency of CPUID with num of gp counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Add a test to verify that KVM correctly emulates MSR-based accesses to general purpose counters based on guest CPUID, e.g. that accesses to non-existent counters #GP and accesses to existent counters succeed. Note, for compatibility reasons, KVM does not emulate #GP when MSR_P6_PERFCTR[0|1] is not present (writes should be dropped). Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 4d3a5c94b8ba..232b9a80a9db 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -270,9 +270,95 @@ static void test_arch_events(uint8_t pmu_version, uint= 64_t perf_capabilities, kvm_vm_free(vm); } =20 +/* + * Limit testing to MSRs that are actually defined by Intel (in the SDM). = MSRs + * that aren't defined counter MSRs *probably* don't exist, but there's no + * guarantee that currently undefined MSR indices won't be used for someth= ing + * other than PMCs in the future. + */ +#define MAX_NR_GP_COUNTERS 8 +#define MAX_NR_FIXED_COUNTERS 3 + +#define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ +__GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ + "Expected %s on " #insn "(0x%x), got vector %u", \ + expect_gp ? "#GP" : "no fault", msr, vector) \ + +static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_co= unters, + uint8_t nr_counters) +{ + uint8_t i; + + for (i =3D 0; i < nr_possible_counters; i++) { + const uint32_t msr =3D base_msr + i; + const bool expect_success =3D i < nr_counters; + + /* + * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are + * unsupported, i.e. doesn't #GP and reads back '0'. + */ + const uint64_t expected_val =3D expect_success ? 0xffff : 0; + const bool expect_gp =3D !expect_success && msr !=3D MSR_P6_PERFCTR0 && + msr !=3D MSR_P6_PERFCTR1; + uint8_t vector; + uint64_t val; + + vector =3D wrmsr_safe(msr, 0xffff); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); + + vector =3D rdmsr_safe(msr, &val); + GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, msr, expect_gp, vector); + + /* On #GP, the result of RDMSR is undefined. */ + if (!expect_gp) + __GUEST_ASSERT(val =3D=3D expected_val, + "Expected RDMSR(0x%x) to yield 0x%lx, got 0x%lx", + msr, expected_val, val); + + vector =3D wrmsr_safe(msr, 0); + GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); + } + GUEST_DONE(); +} + +static void guest_test_gp_counters(void) +{ + uint8_t nr_gp_counters =3D 0; + uint32_t base_msr; + + if (guest_get_pmu_version()) + nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + + if (this_cpu_has(X86_FEATURE_PDCM) && + rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + base_msr =3D MSR_IA32_PMC0; + else + base_msr =3D MSR_IA32_PERFCTR0; + + guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters); +} + +static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, + uint8_t nr_gp_counters) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters, + pmu_version, perf_capabilities); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, + nr_gp_counters); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters(void) { uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; uint8_t v, j; @@ -337,6 +423,11 @@ static void test_intel_counters(void) for (k =3D 0; k < nr_arch_events; k++) test_arch_events(v, perf_caps[i], j, BIT(k)); } + + pr_info("Testing GP counters, PMU version %u, perf_caps =3D %lx\n", + v, perf_caps[i]); + for (j =3D 0; j <=3D nr_gp_counters; j++) + test_gp_counters(v, perf_caps[i], j); } } } --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF485C4332F for ; Sat, 4 Nov 2023 00:03:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232651AbjKDADm (ORCPT ); Fri, 3 Nov 2023 20:03:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232012AbjKDAD3 (ORCPT ); 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Fri, 03 Nov 2023 17:03:05 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:31 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-14-seanjc@google.com> Subject: [PATCH v6 13/20] KVM: selftests: Test consistency of CPUID with num of fixed counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Extend the PMU counters test to verify KVM emulation of fixed counters in addition to general purpose counters. Fixed counters add an extra wrinkle in the form of an extra supported bitmask. Thus quoth the SDM: fixed-function performance counter 'i' is supported if ECX[i] || (EDX[4:0= ] > i) Test that KVM handles a counter being available through either method. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 60 ++++++++++++++++++- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 232b9a80a9db..52b9d9f615eb 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -285,13 +285,19 @@ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : = !vector, \ expect_gp ? "#GP" : "no fault", msr, vector) \ =20 static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_co= unters, - uint8_t nr_counters) + uint8_t nr_counters, uint32_t or_mask) { uint8_t i; =20 for (i =3D 0; i < nr_possible_counters; i++) { const uint32_t msr =3D base_msr + i; - const bool expect_success =3D i < nr_counters; + + /* + * Fixed counters are supported if the counter is less than the + * number of enumerated contiguous counters *or* the counter is + * explicitly enumerated in the supported counters mask. + */ + const bool expect_success =3D i < nr_counters || (or_mask & BIT(i)); =20 /* * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are @@ -335,7 +341,7 @@ static void guest_test_gp_counters(void) else base_msr =3D MSR_IA32_PERFCTR0; =20 - guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters); + guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters, 0); } =20 static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, @@ -355,9 +361,50 @@ static void test_gp_counters(uint8_t pmu_version, uint= 64_t perf_capabilities, kvm_vm_free(vm); } =20 +static void guest_test_fixed_counters(void) +{ + uint64_t supported_bitmask =3D 0; + uint8_t nr_fixed_counters =3D 0; + + /* Fixed counters require Architectural vPMU Version 2+. */ + if (guest_get_pmu_version() >=3D 2) + nr_fixed_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTE= RS); + + /* + * The supported bitmask for fixed counters was introduced in PMU + * version 5. + */ + if (guest_get_pmu_version() >=3D 5) + supported_bitmask =3D this_cpu_property(X86_PROPERTY_PMU_FIXED_COUNTERS_= BITMASK); + + guest_rd_wr_counters(MSR_CORE_PERF_FIXED_CTR0, MAX_NR_FIXED_COUNTERS, + nr_fixed_counters, supported_bitmask); +} + +static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabil= ities, + uint8_t nr_fixed_counters, + uint32_t supported_bitmask) +{ + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_fixed_counters, + pmu_version, perf_capabilities); + + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, + supported_bitmask); + vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS, + nr_fixed_counters); + + run_vcpu(vcpu); + + kvm_vm_free(vm); +} + static void test_intel_counters(void) { uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_= COUNTERS); uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; @@ -428,6 +475,13 @@ static void test_intel_counters(void) v, perf_caps[i]); for (j =3D 0; j <=3D nr_gp_counters; j++) test_gp_counters(v, perf_caps[i], j); + + pr_info("Testing fixed counters, PMU version %u, perf_caps =3D %lx\n", + v, perf_caps[i]); + for (j =3D 0; j <=3D nr_fixed_counters; j++) { + for (k =3D 0; k <=3D (BIT(nr_fixed_counters) - 1); k++) + test_fixed_counters(v, perf_caps[i], j, k); + } } } } --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2047BC4332F for ; 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Fri, 03 Nov 2023 17:03:07 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:32 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-15-seanjc@google.com> Subject: [PATCH v6 14/20] KVM: selftests: Add functional test for Intel's fixed PMU counters From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jinrong Liang Extend the fixed counters test to verify that supported counters can actually be enabled in the control MSRs, that unsupported counters cannot, and that enabled counters actually count. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang [sean: fold into the rd/wr access test, massage changelog] Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 52b9d9f615eb..5e3a1575bffc 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -324,7 +324,6 @@ static void guest_rd_wr_counters(uint32_t base_msr, uin= t8_t nr_possible_counters vector =3D wrmsr_safe(msr, 0); GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector); } - GUEST_DONE(); } =20 static void guest_test_gp_counters(void) @@ -342,6 +341,7 @@ static void guest_test_gp_counters(void) base_msr =3D MSR_IA32_PERFCTR0; =20 guest_rd_wr_counters(base_msr, MAX_NR_GP_COUNTERS, nr_gp_counters, 0); + GUEST_DONE(); } =20 static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabiliti= es, @@ -365,6 +365,7 @@ static void guest_test_fixed_counters(void) { uint64_t supported_bitmask =3D 0; uint8_t nr_fixed_counters =3D 0; + uint8_t i; =20 /* Fixed counters require Architectural vPMU Version 2+. */ if (guest_get_pmu_version() >=3D 2) @@ -379,6 +380,32 @@ static void guest_test_fixed_counters(void) =20 guest_rd_wr_counters(MSR_CORE_PERF_FIXED_CTR0, MAX_NR_FIXED_COUNTERS, nr_fixed_counters, supported_bitmask); + + for (i =3D 0; i < MAX_NR_FIXED_COUNTERS; i++) { + uint8_t vector; + uint64_t val; + + if (i >=3D nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) { + vector =3D wrmsr_safe(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + __GUEST_ASSERT(vector =3D=3D GP_VECTOR, + "Expected #GP for counter %u in FIXED_CTRL_CTRL", i); + + vector =3D wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(PMC_IDX_FIXED = + i)); + __GUEST_ASSERT(vector =3D=3D GP_VECTOR, + "Expected #GP for counter %u in PERF_GLOBAL_CTRL", i); + continue; + } + + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(PMC_IDX_FIXED + i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + val =3D rdmsr(MSR_CORE_PERF_FIXED_CTR0 + i); + + GUEST_ASSERT_NE(val, 0); + } + GUEST_DONE(); } =20 static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabil= ities, --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D14DC4332F for ; Sat, 4 Nov 2023 00:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231899AbjKDADu (ORCPT ); Fri, 3 Nov 2023 20:03:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231522AbjKDADb (ORCPT ); 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Fri, 03 Nov 2023 17:03:09 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:33 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-16-seanjc@google.com> Subject: [PATCH v6 15/20] KVM: selftests: Expand PMU counters test to verify LLC events From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expand the PMU counters test to verify that LLC references and misses have non-zero counts when the code being executed while the LLC event(s) is active is evicted via CFLUSH{,OPT}. Note, CLFLUSH{,OPT} requires a fence of some kind to ensure the cache lines are flushed before execution continues. Use MFENCE for simplicity (performance is not a concern). Suggested-by: Jim Mattson Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 59 +++++++++++++------ 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 5e3a1575bffc..780f62e6a0f2 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -14,9 +14,9 @@ /* * Number of "extra" instructions that will be counted, i.e. the number of * instructions that are needed to set up the loop and then disabled the - * counter. 2 MOV, 2 XOR, 1 WRMSR. + * counter. 1 CLFLUSH/CLFLUSHOPT/NOP, 1 MFENCE, 2 MOV, 2 XOR, 1 WRMSR. */ -#define NUM_EXTRA_INSNS 5 +#define NUM_EXTRA_INSNS 7 #define NUM_INSNS_RETIRED (NUM_BRANCHES + NUM_EXTRA_INSNS) =20 static uint8_t kvm_pmu_version; @@ -107,6 +107,12 @@ static void guest_assert_event_count(uint8_t idx, case INTEL_ARCH_BRANCHES_RETIRED: GUEST_ASSERT_EQ(count, NUM_BRANCHES); break; + case INTEL_ARCH_LLC_REFERENCES: + case INTEL_ARCH_LLC_MISSES: + if (!this_cpu_has(X86_FEATURE_CLFLUSHOPT) && + !this_cpu_has(X86_FEATURE_CLFLUSH)) + break; + fallthrough; case INTEL_ARCH_CPU_CYCLES: case INTEL_ARCH_REFERENCE_CYCLES: GUEST_ASSERT_NE(count, 0); @@ -123,29 +129,44 @@ static void guest_assert_event_count(uint8_t idx, GUEST_ASSERT_EQ(_rdpmc(pmc), 0xdead); } =20 +/* + * Enable and disable the PMC in a monolithic asm blob to ensure that the + * compiler can't insert _any_ code into the measured sequence. Note, ECX + * doesn't need to be clobbered as the input value, @pmc_msr, is restored + * before the end of the sequence. + * + * If CLFUSH{,OPT} is supported, flush the cacheline containing (at least)= the + * start of the loop to force LLC references and misses, i.e. to allow tes= ting + * that those events actually count. + */ +#define GUEST_MEASURE_EVENT(_msr, _value, clflush) \ +do { \ + __asm__ __volatile__("wrmsr\n\t" \ + clflush "\n\t" \ + "mfence\n\t" \ + "1: mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" \ + "loop .\n\t" \ + "mov %%edi, %%ecx\n\t" \ + "xor %%eax, %%eax\n\t" \ + "xor %%edx, %%edx\n\t" \ + "wrmsr\n\t" \ + :: "a"((uint32_t)_value), "d"(_value >> 32), \ + "c"(_msr), "D"(_msr) \ + ); \ +} while (0) + static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_featur= e event, uint32_t pmc, uint32_t pmc_msr, uint32_t ctrl_msr, uint64_t ctrl_msr_value) { wrmsr(pmc_msr, 0); =20 - /* - * Enable and disable the PMC in a monolithic asm blob to ensure that - * the compiler can't insert _any_ code into the measured sequence. - * Note, ECX doesn't need to be clobbered as the input value, @pmc_msr, - * is restored before the end of the sequence. - */ - __asm__ __volatile__("wrmsr\n\t" - "mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" - "loop .\n\t" - "mov %%edi, %%ecx\n\t" - "xor %%eax, %%eax\n\t" - "xor %%edx, %%edx\n\t" - "wrmsr\n\t" - :: "a"((uint32_t)ctrl_msr_value), - "d"(ctrl_msr_value >> 32), - "c"(ctrl_msr), "D"(ctrl_msr) - ); + if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflushopt 1f"); + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflush 1f"); + else + GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "nop"); =20 guest_assert_event_count(idx, event, pmc, pmc_msr); } --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A50DC4332F for ; Sat, 4 Nov 2023 00:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232060AbjKDAED (ORCPT ); Fri, 3 Nov 2023 20:04:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230512AbjKDADi (ORCPT ); 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Fri, 03 Nov 2023 17:03:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:34 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-17-seanjc@google.com> Subject: [PATCH v6 16/20] KVM: selftests: Add a helper to query if the PMU module param is enabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper to problem KVM's "enable_pmu" param, open coding strings in multiple places is just asking for a false negatives and/or runtime errors due to typos. Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/include/x86_64/processor.h | 5 +++++ tools/testing/selftests/kvm/x86_64/pmu_counters_test.c | 2 +- tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c | 2 +- tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index b103c462701b..1885e758eb4d 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -1214,6 +1214,11 @@ static inline uint8_t xsetbv_safe(uint32_t index, ui= nt64_t value) =20 bool kvm_is_tdp_enabled(void); =20 +static inline bool kvm_is_pmu_enabled(void) +{ + return get_kvm_param_bool("enable_pmu"); +} + uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, int *level); uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 780f62e6a0f2..e6cf76d3499b 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -536,7 +536,7 @@ static void test_intel_counters(void) =20 int main(int argc, char *argv[]) { - TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + TEST_REQUIRE(kvm_is_pmu_enabled()); =20 TEST_REQUIRE(host_cpu_is_intel); TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/t= ools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c index b6e4f57a8651..95bdb6d5af50 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c @@ -906,7 +906,7 @@ int main(int argc, char *argv[]) struct kvm_vcpu *vcpu, *vcpu2 =3D NULL; struct kvm_vm *vm; =20 - TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + TEST_REQUIRE(kvm_is_pmu_enabled()); TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_FILTER)); TEST_REQUIRE(kvm_has_cap(KVM_CAP_PMU_EVENT_MASKED_EVENTS)); =20 diff --git a/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c b/tools= /testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c index ebbcb0a3f743..562b0152a122 100644 --- a/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c +++ b/tools/testing/selftests/kvm/x86_64/vmx_pmu_caps_test.c @@ -237,7 +237,7 @@ int main(int argc, char *argv[]) { union perf_capabilities host_cap; =20 - TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + TEST_REQUIRE(kvm_is_pmu_enabled()); TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); =20 TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A728EC4332F for ; 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Fri, 03 Nov 2023 17:03:13 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:35 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-18-seanjc@google.com> Subject: [PATCH v6 17/20] KVM: selftests: Add helpers to read integer module params From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helpers to read integer module params, which is painfully non-trivial because the pain of dealing with strings in C is exacerbated by the kernel inserting a newline. Don't bother differentiating between int, uint, short, etc. They all fit in an int, and KVM (thankfully) doesn't have any integer params larger than an int. Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/kvm_util_base.h | 4 ++ tools/testing/selftests/kvm/lib/kvm_util.c | 62 +++++++++++++++++-- 2 files changed, 60 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/te= sting/selftests/kvm/include/kvm_util_base.h index a18db6a7b3cf..46b71241216e 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_base.h +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h @@ -238,6 +238,10 @@ bool get_kvm_param_bool(const char *param); bool get_kvm_intel_param_bool(const char *param); bool get_kvm_amd_param_bool(const char *param); =20 +int get_kvm_param_integer(const char *param); +int get_kvm_intel_param_integer(const char *param); +int get_kvm_amd_param_integer(const char *param); + unsigned int kvm_check_cap(long cap); =20 static inline bool kvm_has_cap(long cap) diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/sel= ftests/kvm/lib/kvm_util.c index 7a8af1821f5d..65101c7d1a1a 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -51,13 +51,13 @@ int open_kvm_dev_path_or_exit(void) return _open_kvm_dev_path_or_exit(O_RDONLY); } =20 -static bool get_module_param_bool(const char *module_name, const char *par= am) +static ssize_t get_module_param(const char *module_name, const char *param, + void *buffer, size_t buffer_size) { const int path_size =3D 128; char path[path_size]; - char value; - ssize_t r; - int fd; + ssize_t bytes_read; + int fd, r; =20 r =3D snprintf(path, path_size, "/sys/module/%s/parameters/%s", module_name, param); @@ -66,11 +66,46 @@ static bool get_module_param_bool(const char *module_na= me, const char *param) =20 fd =3D open_path_or_exit(path, O_RDONLY); =20 - r =3D read(fd, &value, 1); - TEST_ASSERT(r =3D=3D 1, "read(%s) failed", path); + bytes_read =3D read(fd, buffer, buffer_size); + TEST_ASSERT(bytes_read > 0, "read(%s) returned %ld, wanted %ld bytes", + path, bytes_read, buffer_size); =20 r =3D close(fd); TEST_ASSERT(!r, "close(%s) failed", path); + return bytes_read; +} + +static int get_module_param_integer(const char *module_name, const char *p= aram) +{ + /* + * 16 bytes to hold a 64-bit value (1 byte per char), 1 byte for the + * NUL char, and 1 byte because the kernel sucks and inserts a newline + * at the end. + */ + char value[16 + 1 + 1]; + ssize_t r; + + memset(value, '\0', sizeof(value)); + + r =3D get_module_param(module_name, param, value, sizeof(value)); + TEST_ASSERT(value[r - 1] =3D=3D '\n', + "Expected trailing newline, got char '%c'", value[r - 1]); + + /* + * Squash the newline, otherwise atoi_paranoid() will complain about + * trailing non-NUL characters in the string. + */ + value[r - 1] =3D '\0'; + return atoi_paranoid(value); +} + +static bool get_module_param_bool(const char *module_name, const char *par= am) +{ + char value; + ssize_t r; + + r =3D get_module_param(module_name, param, &value, sizeof(value)); + TEST_ASSERT_EQ(r, 1); =20 if (value =3D=3D 'Y') return true; @@ -95,6 +130,21 @@ bool get_kvm_amd_param_bool(const char *param) return get_module_param_bool("kvm_amd", param); } =20 +int get_kvm_param_integer(const char *param) +{ + return get_module_param_integer("kvm", param); +} + +int get_kvm_intel_param_integer(const char *param) +{ + return get_module_param_integer("kvm_intel", param); +} + +int get_kvm_amd_param_integer(const char *param) +{ + return get_module_param_integer("kvm_amd", param); +} + /* * Capability * --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD136C4332F for ; Sat, 4 Nov 2023 00:04:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232570AbjKDAEP (ORCPT ); Fri, 3 Nov 2023 20:04:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231972AbjKDADj (ORCPT ); Fri, 3 Nov 2023 20:03:39 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E0D0171D for ; Fri, 3 Nov 2023 17:03:16 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-da307fb7752so3211570276.0 for ; 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charset="utf-8" Add a helper to detect KVM support for forced emulation by querying the module param, and use the helper to detect support for the MSR filtering test instead of throwing a noodle/NOP at KVM to see if it sticks. Cc: Aaron Lewis Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/x86_64/processor.h | 5 ++++ .../kvm/x86_64/userspace_msr_exit_test.c | 27 +++++++------------ 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 1885e758eb4d..47612742968d 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -1219,6 +1219,11 @@ static inline bool kvm_is_pmu_enabled(void) return get_kvm_param_bool("enable_pmu"); } =20 +static inline bool kvm_is_forced_emulation_enabled(void) +{ + return !!get_kvm_param_integer("force_emulation_prefix"); +} + uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr, int *level); uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr); diff --git a/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c b= /tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c index 3533dc2fbfee..9e12dbc47a72 100644 --- a/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c +++ b/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c @@ -14,8 +14,7 @@ =20 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" -#define KVM_FEP_LENGTH 5 -static int fep_available =3D 1; +static bool fep_available; =20 #define MSR_NON_EXISTENT 0x474f4f00 =20 @@ -260,13 +259,6 @@ static void guest_code_filter_allow(void) GUEST_ASSERT(data =3D=3D 2); GUEST_ASSERT(guest_exception_count =3D=3D 0); =20 - /* - * Test to see if the instruction emulator is available (ie: the module - * parameter 'kvm.force_emulation_prefix=3D1' is set). This instruction - * will #UD if it isn't available. - */ - __asm__ __volatile__(KVM_FEP "nop"); - if (fep_available) { /* Let userspace know we aren't done. */ GUEST_SYNC(0); @@ -388,12 +380,6 @@ static void guest_fep_gp_handler(struct ex_regs *regs) &em_wrmsr_start, &em_wrmsr_end); } =20 -static void guest_ud_handler(struct ex_regs *regs) -{ - fep_available =3D 0; - regs->rip +=3D KVM_FEP_LENGTH; -} - static void check_for_guest_assert(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -531,9 +517,11 @@ static void test_msr_filter_allow(void) { struct kvm_vcpu *vcpu; struct kvm_vm *vm; + uint64_t cmd; int rc; =20 vm =3D vm_create_with_one_vcpu(&vcpu, guest_code_filter_allow); + sync_global_to_guest(vm, fep_available); =20 rc =3D kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR); TEST_ASSERT(rc, "KVM_CAP_X86_USER_SPACE_MSR is available"); @@ -561,11 +549,11 @@ static void test_msr_filter_allow(void) run_guest_then_process_wrmsr(vcpu, MSR_NON_EXISTENT); run_guest_then_process_rdmsr(vcpu, MSR_NON_EXISTENT); =20 - vm_install_exception_handler(vm, UD_VECTOR, guest_ud_handler); vcpu_run(vcpu); - vm_install_exception_handler(vm, UD_VECTOR, NULL); + cmd =3D process_ucall(vcpu); =20 - if (process_ucall(vcpu) !=3D UCALL_DONE) { + if (fep_available) { + TEST_ASSERT_EQ(cmd, UCALL_SYNC); vm_install_exception_handler(vm, GP_VECTOR, guest_fep_gp_handler); =20 /* Process emulated rdmsr and wrmsr instructions. */ @@ -583,6 +571,7 @@ static void test_msr_filter_allow(void) /* Confirm the guest completed without issues. */ run_guest_then_process_ucall_done(vcpu); } else { + TEST_ASSERT_EQ(cmd, UCALL_DONE); printf("To run the instruction emulated tests set the module parameter '= kvm.force_emulation_prefix=3D1'\n"); } =20 @@ -804,6 +793,8 @@ static void test_user_exit_msr_flags(void) =20 int main(int argc, char *argv[]) { + fep_available =3D kvm_is_forced_emulation_enabled(); + test_msr_filter_allow(); =20 test_msr_filter_deny(); --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFABC4332F for ; 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Fri, 03 Nov 2023 17:03:17 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 3 Nov 2023 17:02:37 -0700 In-Reply-To: <20231104000239.367005-1-seanjc@google.com> Mime-Version: 1.0 References: <20231104000239.367005-1-seanjc@google.com> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog Message-ID: <20231104000239.367005-20-seanjc@google.com> Subject: [PATCH v6 19/20] KVM: selftests: Move KVM_FEP macro into common library header From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Kan Liang , Dapeng Mi , Jinrong Liang , Like Xu , Jim Mattson , Aaron Lewis Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the KVM_FEP definition, a.k.a. the KVM force emulation prefix, into processor.h so that it can be used for other tests besides the MSR filter test. Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/include/x86_64/processor.h | 3 +++ tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index 47612742968d..764e7c58a518 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -22,6 +22,9 @@ extern bool host_cpu_is_intel; extern bool host_cpu_is_amd; =20 +/* Forced emulation prefix, used to invoke the emulator unconditionally. */ +#define KVM_FEP "ud2; .byte 'k', 'v', 'm';" + #define NMI_VECTOR 0x02 =20 #define X86_EFLAGS_FIXED (1u << 1) diff --git a/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c b= /tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c index 9e12dbc47a72..ab3a8c4f0b86 100644 --- a/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c +++ b/tools/testing/selftests/kvm/x86_64/userspace_msr_exit_test.c @@ -12,8 +12,6 @@ #include "kvm_util.h" #include "vmx.h" =20 -/* Forced emulation prefix, used to invoke the emulator unconditionally. */ -#define KVM_FEP "ud2; .byte 'k', 'v', 'm';" static bool fep_available; =20 #define MSR_NON_EXISTENT 0x474f4f00 --=20 2.42.0.869.gea05f2083d-goog From nobody Wed Dec 31 10:32:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 634E4C4167B for ; Sat, 4 Nov 2023 00:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230525AbjKDAES (ORCPT ); Fri, 3 Nov 2023 20:04:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231765AbjKDADl (ORCPT ); Fri, 3 Nov 2023 20:03:41 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 074A91736 for ; Fri, 3 Nov 2023 17:03:19 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-da39d244087so3392665276.3 for ; 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charset="utf-8" Extend the PMC counters test to use forced emulation to verify that KVM emulates counter events for instructions retired and branches retired. Force emulation for only a subset of the measured code to test that KVM does the right thing when mixing perf events with emulated events. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 44 +++++++++++++------ 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index e6cf76d3499b..c66cf92cc9cc 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -21,6 +21,7 @@ =20 static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; +static bool is_forced_emulation_enabled; =20 static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, void *guest_code, @@ -34,6 +35,7 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct = kvm_vcpu **vcpu, vcpu_init_descriptor_tables(*vcpu); =20 sync_global_to_guest(vm, kvm_pmu_version); + sync_global_to_guest(vm, is_forced_emulation_enabled); =20 /* * Set PERF_CAPABILITIES before PMU version as KVM disallows enabling @@ -138,37 +140,50 @@ static void guest_assert_event_count(uint8_t idx, * If CLFUSH{,OPT} is supported, flush the cacheline containing (at least)= the * start of the loop to force LLC references and misses, i.e. to allow tes= ting * that those events actually count. + * + * If forced emulation is enabled (and specified), force emulation on a su= bset + * of the measured code to verify that KVM correctly emulates instructions= and + * branches retired events in conjunction with hardware also counting said + * events. */ -#define GUEST_MEASURE_EVENT(_msr, _value, clflush) \ +#define GUEST_MEASURE_EVENT(_msr, _value, clflush, FEP) \ do { \ __asm__ __volatile__("wrmsr\n\t" \ clflush "\n\t" \ "mfence\n\t" \ "1: mov $" __stringify(NUM_BRANCHES) ", %%ecx\n\t" \ - "loop .\n\t" \ - "mov %%edi, %%ecx\n\t" \ - "xor %%eax, %%eax\n\t" \ - "xor %%edx, %%edx\n\t" \ + FEP "loop .\n\t" \ + FEP "mov %%edi, %%ecx\n\t" \ + FEP "xor %%eax, %%eax\n\t" \ + FEP "xor %%edx, %%edx\n\t" \ "wrmsr\n\t" \ :: "a"((uint32_t)_value), "d"(_value >> 32), \ "c"(_msr), "D"(_msr) \ ); \ } while (0) =20 +#define GUEST_TEST_EVENT(_idx, _event, _pmc, _pmc_msr, _ctrl_msr, _value, = FEP) \ +do { \ + wrmsr(pmc_msr, 0); \ + \ + if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) \ + GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt 1f", FEP); \ + else if (this_cpu_has(X86_FEATURE_CLFLUSH)) \ + GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush 1f", FEP); \ + else \ + GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \ + \ + guest_assert_event_count(_idx, _event, _pmc, _pmc_msr); \ +} while (0) + static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_featur= e event, uint32_t pmc, uint32_t pmc_msr, uint32_t ctrl_msr, uint64_t ctrl_msr_value) { - wrmsr(pmc_msr, 0); + GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, ""); =20 - if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) - GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflushopt 1f"); - else if (this_cpu_has(X86_FEATURE_CLFLUSH)) - GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "clflush 1f"); - else - GUEST_MEASURE_EVENT(ctrl_msr, ctrl_msr_value, "nop"); - - guest_assert_event_count(idx, event, pmc, pmc_msr); + if (is_forced_emulation_enabled) + GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM= _FEP); } =20 #define X86_PMU_FEATURE_NULL \ @@ -544,6 +559,7 @@ int main(int argc, char *argv[]) =20 kvm_pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); kvm_has_perf_caps =3D kvm_cpu_has(X86_FEATURE_PDCM); + is_forced_emulation_enabled =3D kvm_is_forced_emulation_enabled(); =20 test_intel_counters(); =20 --=20 2.42.0.869.gea05f2083d-goog