From nobody Wed Dec 31 12:32:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF239C4332F for ; Fri, 3 Nov 2023 21:54:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230388AbjKCVyD (ORCPT ); Fri, 3 Nov 2023 17:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbjKCVx6 (ORCPT ); Fri, 3 Nov 2023 17:53:58 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7685BD55 for ; Fri, 3 Nov 2023 14:53:55 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A3Lnpn3020634; Fri, 3 Nov 2023 21:53:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=JNcU2EYYMa9vXzGbPpsfYbnWmwU4ywEE7/XEM88x3vI=; b=TuJ7oue001YpCBbGUeUHQHJVmeqrQTdEnWQUG5i8lLrGUtZceCyEKMuU9Se1MtHUP2gE 4N781EHgH09alWe6VU3K0eIm+GpYumK2Rzn2gT2VRllLyZZL/hKg7VioDFT/32P5GDIy WR3AiL+sP35N4pxFSBSuAOvVLd0HvR/9rvCmJFVO0XVGuEZ6L7uj/mFeV5vjmbEOV/XH URawht/9wVSJc4qzSOwai+zOCBhy8m201SDUf374xvArX6mD1Trwi73yO3dJR7Vhz2sL /VJd41jcEmqVl7JN8y3/otet+SvCg4fH3B2K3ilLSEGbNYaQ46TNjmBF9kmshA/4pw8z iA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u4yk0sbve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 03 Nov 2023 21:53:43 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A3Lrgl1003873 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Nov 2023 21:53:42 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 3 Nov 2023 14:53:37 -0700 From: Bibek Kumar Patro To: , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH 3/3] iommu/arm-smmu: re-enable context caching in smmu reset operation Date: Sat, 4 Nov 2023 03:21:24 +0530 Message-ID: <20231103215124.1095-4-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231103215124.1095-1-quic_bibekkum@quicinc.com> References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ka13ShKkXK6Ou-x76CJAWjncfLG9z9jS X-Proofpoint-GUID: Ka13ShKkXK6Ou-x76CJAWjncfLG9z9jS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-03_21,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311030185 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs through SoC specific reset ops, which is disabled in the default MMU-500 reset ops, but is expected for context banks using ACTLR register to retain the prefetch value during reset and runtime suspend. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 590b7c285299..f342b4778cf1 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -457,11 +457,29 @@ static int qcom_smmu_def_domain_type(struct device *d= ev) return match ? IOMMU_DOMAIN_IDENTITY : 0; } +#define ARM_MMU500_ACTLR_CPRE BIT(1) + +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) +{ + int i; + u32 reg; + + arm_mmu500_reset(smmu); + + for (i =3D 0; i < smmu->num_context_banks; ++i) { + reg =3D arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); + reg |=3D ARM_MMU500_ACTLR_CPRE; + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); + } + + return 0; +} + static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; - arm_mmu500_reset(smmu); + qcom_smmu500_reset(smmu); /* * To address performance degradation in non-real time clients, @@ -488,7 +506,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = =3D { .init_context =3D qcom_smmu_init_context, .cfg_probe =3D qcom_smmu_cfg_probe, .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, + .reset =3D qcom_smmu500_reset, .write_s2cr =3D qcom_smmu_write_s2cr, .tlb_sync =3D qcom_smmu_tlb_sync, }; @@ -507,7 +525,7 @@ static const struct arm_smmu_impl sm8550_smmu_500_impl = =3D { .init_context =3D qcom_smmu_init_context, .cfg_probe =3D qcom_smmu_cfg_probe, .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, + .reset =3D qcom_smmu500_reset, .write_s2cr =3D qcom_smmu_write_s2cr, .tlb_sync =3D qcom_smmu_tlb_sync, }; @@ -523,7 +541,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_i= mpl =3D { static const struct arm_smmu_impl qcom_adreno_smmu_500_impl =3D { .init_context =3D qcom_adreno_smmu_init_context, .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, + .reset =3D qcom_smmu500_reset, .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, .write_sctlr =3D qcom_adreno_smmu_write_sctlr, .tlb_sync =3D qcom_smmu_tlb_sync, -- 2.17.1