From nobody Wed Dec 31 12:27:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 058E6C4332F for ; Fri, 3 Nov 2023 20:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378286AbjKCUTT (ORCPT ); Fri, 3 Nov 2023 16:19:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378198AbjKCUSr (ORCPT ); Fri, 3 Nov 2023 16:18:47 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB744D63 for ; Fri, 3 Nov 2023 13:18:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699042725; x=1730578725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dJYH4bpZB4D6gpUDi338sRrXHssESnJCrAN+Nzo1Zug=; b=ABOzRS0k7Nlc0QOIvnwgCy7VbUlEY+DLOtUI4edBBXVFkviaJHW1mtRx wjxNaNLw5uXCv6s2M/KZPR94Q1/m4t1C0UvuUeFv475xB+2uUCUsq9ToE +/AEmXmGum9Z2a7Coq9Msg/2y87O/bvJbBaF0RXFgKOb6n2vvOvQtfwmX +P/Jn0EgS3UZJaRXiE1dds5Hk5Ahc3urJ2BUPAQkSomCXct4EQchEExGe PjTjzxKztVWft8AL6lbKoUW/CoBoE9HBLbe9KEVlH+goV95wlUCQ+muIG iGbkVf59S2CN51NCRA+YZmHE5inCzikFv/7w5Ykxk3W9NozBYKxVd1hnW Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1896102" X-IronPort-AV: E=Sophos;i="6.03,275,1694761200"; d="scan'208";a="1896102" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 13:18:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="832131191" X-IronPort-AV: E=Sophos;i="6.03,275,1694761200"; d="scan'208";a="832131191" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga004.fm.intel.com with ESMTP; 03 Nov 2023 13:18:40 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 3442F76D; Fri, 3 Nov 2023 22:18:34 +0200 (EET) From: Andy Shevchenko To: Jani Nikula , Andy Shevchenko , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter , Hans de Goede Subject: [PATCH v4 12/16] drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back Date: Fri, 3 Nov 2023 22:18:27 +0200 Message-Id: <20231103201831.1037416-13-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.40.0.1.gaa8946217a0b In-Reply-To: <20231103201831.1037416-1-andriy.shevchenko@linux.intel.com> References: <20231103201831.1037416-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's a dirty hack in the driver that pokes GPIO registers behind the driver's back. Moreoever it might be problematic as simultaneous I/O may hang the system, see the commit 40ecab551232 ("pinctrl: baytrail: Really serialize all register accesses") for the details. Taking all this into consideration replace the hack with proper GPIO APIs being used. Signed-off-by: Andy Shevchenko Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 98 ++++++-------------- 1 file changed, 28 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm= /i915/display/intel_dsi_vbt.c index 9847a92fdfc3..552bc6564d79 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -55,43 +55,6 @@ #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 #define MIPI_PORT_SHIFT 3 =20 -/* base offsets for gpio pads */ -#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 -#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 -#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 -#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 -#define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 -#define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 -#define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 -#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 -#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 -#define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 -#define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 -#define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 - -#define VLV_GPIO_PCONF0(base_offset) (base_offset) -#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) - -struct gpio_map { - u16 base_offset; - bool init; -}; - -static struct gpio_map vlv_gpio_table[] =3D { - { VLV_GPIO_NC_0_HV_DDI0_HPD }, - { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, - { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, - { VLV_GPIO_NC_3_PANEL0_VDDEN }, - { VLV_GPIO_NC_4_PANEL0_BKLTEN }, - { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, - { VLV_GPIO_NC_6_HV_DDI1_HPD }, - { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, - { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, - { VLV_GPIO_NC_9_PANEL1_VDDEN }, - { VLV_GPIO_NC_10_PANEL1_BKLTEN }, - { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, -}; - struct i2c_adapter_lookup { u16 slave_addr; struct intel_dsi *intel_dsi; @@ -268,52 +231,47 @@ static void soc_gpio_set_value(struct intel_connector= *connector, const char *co } } =20 +static void soc_opaque_gpio_set_value(struct intel_connector *connector, + const char *chip, const char *con_id, + u8 gpio_index, bool value) +{ + struct gpiod_lookup_table *lookup; + + lookup =3D kzalloc(struct_size(lookup, table, 2), GFP_KERNEL); + if (!lookup) + return; + + lookup->dev_id =3D "0000:00:02.0"; + lookup->table[0] =3D + GPIO_LOOKUP_IDX(chip, gpio_index, con_id, gpio_index, GPIO_ACTIVE_HIGH); + + gpiod_add_lookup_table(lookup); + + soc_gpio_set_value(connector, con_id, gpio_index, value); + + gpiod_remove_lookup_table(lookup); + kfree(lookup); +} + static void vlv_gpio_set_value(struct intel_connector *connector, u8 gpio_source, u8 gpio_index, bool value) { struct drm_i915_private *dev_priv =3D to_i915(connector->base.dev); - struct gpio_map *map; - u16 pconf0, padval; - u32 tmp; - u8 port; =20 - if (gpio_index >=3D ARRAY_SIZE(vlv_gpio_table)) { - drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", - gpio_index); - return; - } - - map =3D &vlv_gpio_table[gpio_index]; - - if (connector->panel.vbt.dsi.seq_version >=3D 3) { - /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ - port =3D IOSF_PORT_GPIO_NC; - } else { - if (gpio_source =3D=3D 0) { - port =3D IOSF_PORT_GPIO_NC; - } else if (gpio_source =3D=3D 1) { + /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ + if (connector->panel.vbt.dsi.seq_version < 3) { + if (gpio_source =3D=3D 1) { drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); return; - } else { + } + if (gpio_source > 1) { drm_dbg_kms(&dev_priv->drm, "unknown gpio source %u\n", gpio_source); return; } } =20 - pconf0 =3D VLV_GPIO_PCONF0(map->base_offset); - padval =3D VLV_GPIO_PAD_VAL(map->base_offset); - - vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); - if (!map->init) { - /* FIXME: remove constant below */ - vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); - map->init =3D true; - } - - tmp =3D 0x4 | value; - vlv_iosf_sb_write(dev_priv, port, padval, tmp); - vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); + soc_opaque_gpio_set_value(connector, "INT33FC:01", "Panel N", gpio_index,= value); } =20 static void chv_gpio_set_value(struct intel_connector *connector, --=20 2.40.0.1.gaa8946217a0b