From nobody Fri Sep 20 08:32:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19C3EC00A5A for ; Fri, 3 Nov 2023 10:26:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232332AbjKCK0B (ORCPT ); Fri, 3 Nov 2023 06:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbjKCKZ4 (ORCPT ); Fri, 3 Nov 2023 06:25:56 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC04AD6A; Fri, 3 Nov 2023 03:25:41 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0329466073DE; Fri, 3 Nov 2023 10:25:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699007139; bh=ydznuU/qU3/4n+XPC3QC8kIGBDwC8DDVTRqGgET/oCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Rkix/j9I+4gs44C7mjbgydNfyMKLtz3f4n246CHqkRX8x8QV1GpVdf8mlBZuIMzW/ AoPWLbtsK4Ggdi4WN6OugknS0bVlrRt9FuOuLUvrSKTmi46fEPXPiTzudYSJJdXwEQ FHo4HcLKrc3dPhw7FZ+iYfOvhgLXVzjmXVQiSmSgUg2t6vmDwKEmRIGIH+GEeJ5oVn GMUGzCEJjpwLq6f7/D84y18L60rvQVk30lhm75j8F/tFdKWJfcS3AYqFmaeA6SEMnF yrFfLhuqww6ePYlpbLTqZ8Ueuf0aDveqijdtPiJdEREv4XqMTXlV32SEcigUxwlnX2 wbms8ucuRy/+Q== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 1/3] clk: mediatek: clk-mux: Support custom parent indices for muxes Date: Fri, 3 Nov 2023 11:25:31 +0100 Message-ID: <20231103102533.69280-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> References: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for customized parent indices for MediaTek muxes: this is necessary for the case in which we want to exclude some clocks from a mux's parent clocks list, where the exclusions are not from the very bottom of the list but either in the middle or the beginning. Example: - MUX1 (all parents) - parent1; idx=3D0 - parent2; idx=3D1 - parent3; idx=3D2 - MUX1 (wanted parents) - parent1; idx=3D0 - parent3; idx=3D2 To achieve that add a `parent_index` array pointer to struct mtk_mux, then in .set_parent(), .get_parent() callbacks check if this array was populated and eventually get the index from that. Also, to avoid updating all clock drivers for all SoCs, rename the "main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has been reintroduced as being fully compatible with the older version. The new parent_index can be specified with the new `_INDEXED` variants of the MUX_GATE_CLR_SET_UPD_xxxx macros. Reviewed-by: Alexandre Mergnat Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Tested-by: Fei Shao --- drivers/clk/mediatek/clk-mux.c | 14 +++++++++++ drivers/clk/mediatek/clk-mux.h | 43 ++++++++++++++++++++++++++++++---- 2 files changed, 53 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index c93bc7f926e5..60990296450b 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -89,6 +89,17 @@ static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) regmap_read(mux->regmap, mux->data->mux_ofs, &val); val =3D (val >> mux->data->mux_shift) & mask; =20 + if (mux->data->parent_index) { + int i; + + for (i =3D 0; i < mux->data->num_parents; i++) + if (mux->data->parent_index[i] =3D=3D val) + return i; + + /* Not found: return an impossible index to generate error */ + return mux->data->num_parents + 1; + } + return val; } =20 @@ -104,6 +115,9 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct cl= k_hw *hw, u8 index) else __acquire(mux->lock); =20 + if (mux->data->parent_index) + index =3D mux->data->parent_index[index]; + regmap_read(mux->regmap, mux->data->mux_ofs, &orig); val =3D (orig & ~(mask << mux->data->mux_shift)) | (index << mux->data->mux_shift); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 7ecb963b0ec6..943ad1d7ce4b 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -21,6 +21,7 @@ struct mtk_mux { int id; const char *name; const char * const *parent_names; + const u8 *parent_index; unsigned int flags; =20 u32 mux_ofs; @@ -37,9 +38,10 @@ struct mtk_mux { signed char num_parents; }; =20 -#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ - _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ - _gate, _upd_ofs, _upd, _flags, _ops) { \ +#define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ + _num_parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd, _flags, _ops) { \ .id =3D _id, \ .name =3D _name, \ .mux_ofs =3D _mux_ofs, \ @@ -51,11 +53,28 @@ struct mtk_mux { .gate_shift =3D _gate, \ .upd_shift =3D _upd, \ .parent_names =3D _parents, \ - .num_parents =3D ARRAY_SIZE(_parents), \ + .parent_index =3D _paridx, \ + .num_parents =3D _num_parents, \ .flags =3D _flags, \ .ops =3D &_ops, \ } =20 +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ + _gate, _upd_ofs, _upd, _flags, _ops) \ + __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + NULL, ARRAY_SIZE(_parents), _mux_ofs, \ + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ + _gate, _upd_ofs, _upd, _flags, _ops) \ + +#define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd, _flags, _ops) \ + __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + _paridx, ARRAY_SIZE(_paridx), _mux_ofs, \ + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ + _gate, _upd_ofs, _upd, _flags, _ops) \ + extern const struct clk_ops mtk_mux_clr_set_upd_ops; extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; =20 @@ -67,6 +86,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; _gate, _upd_ofs, _upd, _flags, \ mtk_mux_gate_clr_set_upd_ops) =20 +#define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ + _paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, _flags) \ + GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ + _paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, _flags, \ + mtk_mux_gate_clr_set_upd_ops) + #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _gate, _upd_ofs, _upd) \ @@ -75,6 +102,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_op= s; _width, _gate, _upd_ofs, _upd, \ CLK_SET_RATE_PARENT) =20 +#define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd) \ + MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, \ + _parents, _paridx, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd, CLK_SET_RATE_PARENT) + #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ _upd_ofs, _upd) \ --=20 2.42.0 From nobody Fri Sep 20 08:32:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B224CC4332F for ; Fri, 3 Nov 2023 10:26:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346505AbjKCK0N (ORCPT ); Fri, 3 Nov 2023 06:26:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjKCKZ5 (ORCPT ); Fri, 3 Nov 2023 06:25:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39F09D4F; Fri, 3 Nov 2023 03:25:42 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1D7B366073E1; Fri, 3 Nov 2023 10:25:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699007141; bh=5p8awgj8e9mrJgUArKBpZscHWI/PcsajbEzfr8YryCs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k3hE/NbBI7SY0ZUoVlB6zmyDkR9PCWZPjNLjbiOLAN4mCBj5wSf4O4Ylws0F4mSPG WQMuwg43oQSs0I1gTUolf8XoJLaTZRDnAo/rXWpj6YmAxk3TBABba16IA7M3MA5+uU RqJpfKrRb3mjp8dlOg2ih8IUmclLdB+ChJI5Ux60SCSEFq7WjO3lPHbtpoS5zP95xp hm9H9WLFTC9bX3NYp6zmYAgOdnA1AIGjCuMG66gdhsOagN8QRsb/1JQOAOClwUxWQv TcE5c1fkkx2pn0Q+X5l8xaNMCyVmSciG2meqIXsVpOZhLy71B4Dm1HvIvtsXffCowV oq4leed1/rYtA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 2/3] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes Date: Fri, 3 Nov 2023 11:25:32 +0100 Message-ID: <20231103102533.69280-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> References: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Reviewed-by: Alexandre Mergnat Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 27 +++++++++++++++------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 5c426a1c94c7..8f713a3341a9 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -415,17 +415,28 @@ static const char * const pwrmcu_parents[] =3D { "mainpll_d4_d2" }; =20 +/* + * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using + * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate + * in dual output case, which would lead to corruption of functionality lo= ss. + */ static const char * const dp_parents[] =3D { "clk26m", - "tvdpll1_d2", "tvdpll2_d2", - "tvdpll1_d4", "tvdpll2_d4", - "tvdpll1_d8", "tvdpll2_d8", - "tvdpll1_d16", "tvdpll2_d16" }; +static const u8 dp_parents_idx[] =3D { 0, 2, 4, 6, 8 }; + +static const char * const edp_parents[] =3D { + "clk26m", + "tvdpll1_d2", + "tvdpll1_d4", + "tvdpll1_d8", + "tvdpll1_d16" +}; +static const u8 edp_parents_idx[] =3D { 0, 1, 3, 5, 7 }; =20 static const char * const disp_pwm_parents[] =3D { "clk26m", @@ -957,11 +968,11 @@ static const struct mtk_mux top_mtk_muxes[] =3D { MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu", pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", - dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp", + dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp", - dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp", + edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi", dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0", --=20 2.42.0 From nobody Fri Sep 20 08:32:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7172DC4167B for ; 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d=collabora.com; s=mail; t=1699007142; bh=8pDdd4hAMsC3mfwpObknhb9PNQhaA8a+i3uaZQiNyLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cbNLDN823fuVOuvF4orpZ1686iXAo2f6I+OGsoReLBQH8JuN5rXbaHZIlCJLPdLc7 smNU5S/iFo/MHx/2sv81wEEYx9Sap0odt73fO0WqV93Lmv8NZCoy8I4xyjKBVkyFJI ruyzK5xmYRqOk+L2fbdGb5Wl6uOV8xW4OkIVdci95ydCrUpO6o3c/MaB7U/Stzb6Df Xaz9KKBUzDxG0wXToIUxEq7j3U8ld5FmcSFJtOjJg5mQ3HSdFL5GanTKZBDgwO8mWz gWMgztqQ9JQPl/hD3u327Od4sWbTBO4D2dDFboLCGqwguWsXOubOC9pW66bMOt8Ouh g61vpuzLEadvQ== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, msp@baylibre.com, amergnat@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes Date: Fri, 3 Nov 2023 11:25:33 +0100 Message-ID: <20231103102533.69280-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> References: <20231103102533.69280-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Reviewed-by: Chen-Yu Tsai Reviewed-by: Fei Shao Tested-by: Fei Shao --- drivers/clk/mediatek/clk-mt8188-topckgen.c | 27 +++++++++++----------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/media= tek/clk-mt8188-topckgen.c index e330a4f9a0c3..f7ec599b20af 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -475,29 +475,28 @@ static const char * const sspm_parents[] =3D { "mainpll_d4_d2" }; =20 +/* + * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using + * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate + * in dual output case, which would lead to corruption of functionality lo= ss. + */ static const char * const dp_parents[] =3D { "clk26m", - "tvdpll1_d2", "tvdpll2_d2", - "tvdpll1_d4", "tvdpll2_d4", - "tvdpll1_d8", "tvdpll2_d8", - "tvdpll1_d16", "tvdpll2_d16" }; +static const u8 dp_parents_idx[] =3D { 0, 2, 4, 6, 8 }; =20 static const char * const edp_parents[] =3D { "clk26m", "tvdpll1_d2", - "tvdpll2_d2", "tvdpll1_d4", - "tvdpll2_d4", "tvdpll1_d8", - "tvdpll2_d8", - "tvdpll1_d16", - "tvdpll2_d16" + "tvdpll1_d16" }; +static const u8 edp_parents_idx[] =3D { 0, 1, 3, 5, 7 }; =20 static const char * const dpi_parents[] =3D { "clk26m", @@ -1038,10 +1037,12 @@ static const struct mtk_mux top_mtk_muxes[] =3D { MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm", sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3), /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", - dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp", - edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp", + dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, + 0, 4, 7, 0x08, 4), + MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp", + edp_parents, edp_parents_idx, 0x08C, 0x090, 0x094, + 8, 4, 15, 0x08, 5), MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi", dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6), MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0", --=20 2.42.0