From nobody Wed Dec 31 14:29:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D41C4167B for ; Thu, 2 Nov 2023 19:38:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377431AbjKBTiX (ORCPT ); Thu, 2 Nov 2023 15:38:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234815AbjKBTiL (ORCPT ); Thu, 2 Nov 2023 15:38:11 -0400 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03E221A7 for ; Thu, 2 Nov 2023 12:38:05 -0700 (PDT) Received: by mail-qv1-xf2d.google.com with SMTP id 6a1803df08f44-66d060aa2a4so7914246d6.2 for ; Thu, 02 Nov 2023 12:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hefring-com.20230601.gappssmtp.com; s=20230601; t=1698953884; x=1699558684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6aaUx3IM/nYfDKWStA9Ff2X3zBWfKwgpoaBzpBVRw5U=; b=s+3Wx9alGYL3B6GcYlddhun4+VOnzPxSWOLIyS4a5d+mbApD14DHl2S82/O5bKKFF2 LJrZPN+asfbs9NbxGqjaT2o1y0CDyHTqaLOtHpbZ7bhBTjIazanOUWyqQzxhDfRymnh2 uA5RbeKN/nxnYRYqr43b2SthVRGvOSySh05T14r1RmCHlvJWzo7W6n4rL8+lhF+JGXG5 WLJP6mbcupipsbwIZ96Ez4ctnk8GKEYnS8+64/jT9VKhOkKtASTxWt3H14b/YgypWCHx rgBB5+nDF2Vyw2QrQlA38MmVWNWqQPk1tyz8Ok+/c0HEAUrYxRoDqmZgiKbjYyPllP68 SRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698953884; x=1699558684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6aaUx3IM/nYfDKWStA9Ff2X3zBWfKwgpoaBzpBVRw5U=; b=wZ4kusjhhFBT2WDLYcvsdwKvWtyNfmySOTQlUxDaK40dawgidg04hhlyyeCTC9TxmK UYA7yTiuAyG9xuy8h/CNyvL0BfcOJP6X9TLPWdcglicwLVMJb6gJlHMbwejSsHlGGnL3 ptOxCwzuag0c8p74kITiBU+F4tro2mx65bILIRu7vdKazU1EtJR2ZUy8IFF2TNfV1iO2 DOTzE+8FK65GEDEeYWs2YxrKd5bN9F8kIpT5PtEepeHq7iuSdwn3y/YBhHCQ8uAk4Rh4 hHBNPvQ8pLMSf3tIOzrdqQZfOcm6nwNvrrxdn3ucFffUrxv48aQyLPS6oBvXNIQcfarw Jo7A== X-Gm-Message-State: AOJu0YzSzB7u+knQMeRGXHcHFIPb85haSwAKqON/ldt5oPyFL87gIq05 TDWxgVUIhS/kQfNHqTQOFgPy6A== X-Google-Smtp-Source: AGHT+IGl1n2G2oeUX/4FgvKTLXfhf+P6aEP1OM//x0r4Ln54rPG+Aie8qOEQgGDLVsNuD/9Gag0UxA== X-Received: by 2002:a05:6214:2688:b0:66d:9f40:4792 with SMTP id gm8-20020a056214268800b0066d9f404792mr26366649qvb.26.1698953884213; Thu, 02 Nov 2023 12:38:04 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:38:03 -0700 (PDT) From: Ben Wolsieffer To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Alain Volmat , Erwan Leray , Fabrice Gasnier , Ben Wolsieffer Subject: [PATCH v2 5/5] ARM: dts: stm32: add SPI support on STM32F746 Date: Thu, 2 Nov 2023 15:37:22 -0400 Message-ID: <20231102193722.3042245-6-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> References: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree nodes for the STM32F746 SPI controllers. Signed-off-by: Ben Wolsieffer --- arch/arm/boot/dts/st/stm32f746.dtsi | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm= 32f746.dtsi index 53a8e2dec9a4..14ba51f2a13d 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -274,6 +274,26 @@ gcan3: gcan@40003600 { clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; }; =20 + spi2: spi@40003800 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40003800 0x400>; + interrupts =3D <36>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>; + status =3D "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40003c00 0x400>; + interrupts =3D <51>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>; + status =3D "disabled"; + }; + usart2: serial@40004400 { compatible =3D "st,stm32f7-uart"; reg =3D <0x40004400 0x400>; @@ -491,6 +511,26 @@ sdio1: mmc@40012c00 { status =3D "disabled"; }; =20 + spi1: spi@40013000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40013000 0x400>; + interrupts =3D <35>; + clocks =3D <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>; + status =3D "disabled"; + }; + + spi4: spi@40013400 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40013400 0x400>; + interrupts =3D <84>; + clocks =3D <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>; + status =3D "disabled"; + }; + syscfg: syscon@40013800 { compatible =3D "st,stm32-syscfg", "syscon"; reg =3D <0x40013800 0x400>; @@ -554,6 +594,26 @@ pwm { }; }; =20 + spi5: spi@40015000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40015000 0x400>; + interrupts =3D <85>; + clocks =3D <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>; + status =3D "disabled"; + }; + + spi6: spi@40015400 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "st,stm32f7-spi"; + reg =3D <0x40015400 0x400>; + interrupts =3D <86>; + clocks =3D <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>; + status =3D "disabled"; + }; + ltdc: display-controller@40016800 { compatible =3D "st,stm32-ltdc"; reg =3D <0x40016800 0x200>; --=20 2.42.0