From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11EECC4167D for ; Thu, 2 Nov 2023 14:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376802AbjKBO1E (ORCPT ); Thu, 2 Nov 2023 10:27:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235289AbjKBO1A (ORCPT ); Thu, 2 Nov 2023 10:27:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06039194 for ; Thu, 2 Nov 2023 07:26:53 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 84BF26607090; Thu, 2 Nov 2023 14:26:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935212; bh=YtQIX3FzdJuXHKbLB+mWiM8MZF5dRqqjsu5pKi6GDpo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MDdZALRE8B7hJslAhU/2RIDb5x31cIH0sNSiNrdFukx3ZHZAlOZ9j/x7M/MpV52tw fOqLTV21Dih3ht0oUIjqlSCS3EOCwwZSr3qjBMKGPO1BsO/ilOFuWnXzoCWC1HinC3 bFcuRTy/UUPl5I2aUcAtpYeSbSMBkPoVdkEtZNvAdBBZSR5lpblPAZgtwuOROylx4o nZHioQRwF4i1AfsEngo4ZHKgv7ubTOFE8tMzxEEXCOqsvFpylzAX8ydr7P0Zo36qbZ i7ly919US5lxyLIRt2fElYz3iqoO+c7JbPuKBPPP8GDBvwD+xSnm3DTNpJwDtsYjY/ xwsYs+gU4mbmA== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 1/6] drm/panfrost: Perform hard reset to recover GPU if soft reset fails Date: Thu, 2 Nov 2023 15:26:38 +0100 Message-ID: <20231102142643.75288-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Even though soft reset should ideally never fail, during development of some power management features I managed to get some bits wrong: this resulted in GPU soft reset failures, where the GPU was never able to recover, not even after suspend/resume cycles, meaning that the only way to get functionality back was to reboot the machine. Perform a hard reset after a soft reset failure to be able to recover the GPU during runtime (so, without any machine reboot). Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 14 ++++++++++---- drivers/gpu/drm/panfrost/panfrost_regs.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panf= rost/panfrost_gpu.c index fad75b6e543e..7e9e2cf26e4d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -60,14 +60,20 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfd= ev) =20 gpu_write(pfdev, GPU_INT_MASK, 0); gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); - gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); =20 + gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); - if (ret) { - dev_err(pfdev->dev, "gpu soft reset timed out\n"); - return ret; + dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); + + gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); + ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, + val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); + if (ret) { + dev_err(pfdev->dev, "gpu hard reset timed out\n"); + return ret; + } } =20 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/pan= frost/panfrost_regs.h index 55ec807550b3..c25743b05c55 100644 --- a/drivers/gpu/drm/panfrost/panfrost_regs.h +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h @@ -44,6 +44,7 @@ GPU_IRQ_MULTIPLE_FAULT) #define GPU_CMD 0x30 #define GPU_CMD_SOFT_RESET 0x01 +#define GPU_CMD_HARD_RESET 0x02 #define GPU_CMD_PERFCNT_CLEAR 0x03 #define GPU_CMD_PERFCNT_SAMPLE 0x04 #define GPU_CMD_CYCLE_COUNT_START 0x05 --=20 2.42.0 From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F6BFC41535 for ; Thu, 2 Nov 2023 14:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376816AbjKBO1G (ORCPT ); Thu, 2 Nov 2023 10:27:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235358AbjKBO1A (ORCPT ); Thu, 2 Nov 2023 10:27:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E8D91A1 for ; Thu, 2 Nov 2023 07:26:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8CBE7660716E; Thu, 2 Nov 2023 14:26:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935213; bh=0UapFtlwwc/wpDFrrChMTi6BxCWRS7nEWTprLucLiIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=id3kNstyDYcKb/QUOjDDknsO3GV8HjIOxMLvwtHZiJsGslypvZERsaeqYZnAaZRs3 pioH67/s4u7nsbtZD47fblpN4FDtidk0LsiUb1rw1nmd7+h/9l4h4xm1mdheJ5Cl69 0zytdQF35GRUZ6CoO9zHt4oImwfOY0oaGRaP+ir63yKigufYjNT02hT6w7ZiBzUH9q tEaoetZhjDotYiqm2RHuPgMoq0oM2iDK1O0/RbfJwL50qEEgnI6JML3mZUVZS/1Kmq pjdF3qklYVqLQk1zHtXhoArgyR4FtZPRJNnElXO7AQE06L4PN+4IGeNsPJCsoJBtOW so6Fer0ayHP+A== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 2/6] drm/panfrost: Tighten polling for soft reset and power on Date: Thu, 2 Nov 2023 15:26:39 +0100 Message-ID: <20231102142643.75288-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In many cases, soft reset takes more than 1 microsecond, but definitely less than 10; moreover in the poweron flow, tilers, shaders and l2 will become ready (each) in less than 10 microseconds as well. Even in the cases (at least on my platforms, rarely) in which those take more than 10 microseconds, it's very unlikely to see both soft reset and poweron to take more than 70 microseconds. Shorten the polling delay to 10 microseconds to consistently reduce the runtime resume time of the GPU. As an indicative example, measurements taken on a MediaTek MT8195 SoC Average runtime resume time in nanoseconds before this commit: GDM, user selection up/down: 88435ns GDM, Text Entry (typing user/password): 91489ns GNOME Desktop, idling, GKRELLM running: 73200ns After this commit: GDM: user selection up/down: 26690ns GDM: Text Entry (typing user/password): 27917ns GNOME Desktop, idling, GKRELLM running: 25304ns Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panf= rost/panfrost_gpu.c index 7e9e2cf26e4d..e264e8c2252d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -63,7 +63,7 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) =20 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, - val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); + val, val & GPU_IRQ_RESET_COMPLETED, 10, 10000); if (ret) { dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); =20 @@ -403,7 +403,7 @@ void panfrost_gpu_power_on(struct panfrost_device *pfde= v) gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, val, val =3D=3D (pfdev->features.l2_present & core_mask), - 100, 20000); + 10, 20000); if (ret) dev_err(pfdev->dev, "error powering up gpu L2"); =20 @@ -411,13 +411,13 @@ void panfrost_gpu_power_on(struct panfrost_device *pf= dev) pfdev->features.shader_present & core_mask); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, val, val =3D=3D (pfdev->features.shader_present & core_mask), - 100, 20000); + 10, 20000); if (ret) dev_err(pfdev->dev, "error powering up gpu shader"); =20 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO, - val, val =3D=3D pfdev->features.tiler_present, 100, 1000); + val, val =3D=3D pfdev->features.tiler_present, 10, 1000); if (ret) dev_err(pfdev->dev, "error powering up gpu tiler"); } --=20 2.42.0 From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3C72C4167D for ; Thu, 2 Nov 2023 14:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235340AbjKBO1J (ORCPT ); Thu, 2 Nov 2023 10:27:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376810AbjKBO1C (ORCPT ); Thu, 2 Nov 2023 10:27:02 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC061A6 for ; Thu, 2 Nov 2023 07:26:55 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9461A66071A3; Thu, 2 Nov 2023 14:26:53 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935214; bh=/LtYZX88iauWNQZJUo4rCxgbBpDr9xze3AUhEtbVTX4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lvCYDqjfsnlTfsTUF/eGRTtWeN06O3QFIIgwOJE09mRbW8MjPHG1/i43A+8/nblLF p+E3VMrHJD5qpmnaxqxCumtS1z2BrlDmtmX8sk/GycpwBkjj+DglrTVqL4sFFaVcIA mDY8v7I6SxgubAArRmtIzOscjqMEmow1sr9XbJfDrmYhrw5bd/8a25/isvw4Vd+EB2 PnGNLBcJVqguD8Dtf+wt87G6W3LOzTvN+WdZgVQ0+DSpDYcbGjeqlj7xJZzGvIhT/D yi2c43PAITxkqG1psxvhQyXW1jUSq2TUp4v7ohJYSBW0qvrUY40AqbmX11RD9UlA1A sJI57ISmuQnLQ== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 3/6] drm/panfrost: Implement ability to turn on/off GPU clocks in suspend Date: Thu, 2 Nov 2023 15:26:40 +0100 Message-ID: <20231102142643.75288-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the GPU is being internally powered off for runtime suspend and turned back on for runtime resume through commands sent to it, but note that the GPU doesn't need to be clocked during the poweroff state, hence it is possible to save some power on selected platforms. Add suspend and resume handlers for full system sleep and then add a new panfrost_gpu_pm enumeration and a pm_features variable in the panfrost_compatible structure: BIT(GPU_PM_CLK_DIS) will be used to enable this power saving technique only on SoCs that are able to safely use it. Note that this was implemented only for the system sleep case and not for runtime PM because testing on one of my MediaTek platforms showed issues when turning on and off clocks aggressively (in PM runtime) resulting in a full system lockup. Doing this only for full system sleep never showed issues during my testing by suspending and resuming the system continuously for more than 100 cycles. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- Note: Even after fixing the panfrost_power_off() function, I'm still getting issues with turning off the clocks at .runtime_suspend() but this time, instead of getting a GPU lockup, the entire SoC will deadlock bringing down the entire system with it (so it's even worst!) :-) drivers/gpu/drm/panfrost/panfrost_device.c | 61 ++++++++++++++++++++-- drivers/gpu/drm/panfrost/panfrost_device.h | 11 ++++ 2 files changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index 28f7046e1b1a..2022ed76a620 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -403,7 +403,7 @@ void panfrost_device_reset(struct panfrost_device *pfde= v) panfrost_job_enable_interrupts(pfdev); } =20 -static int panfrost_device_resume(struct device *dev) +static int panfrost_device_runtime_resume(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); =20 @@ -413,7 +413,7 @@ static int panfrost_device_resume(struct device *dev) return 0; } =20 -static int panfrost_device_suspend(struct device *dev) +static int panfrost_device_runtime_suspend(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); =20 @@ -426,5 +426,58 @@ static int panfrost_device_suspend(struct device *dev) return 0; } =20 -EXPORT_GPL_RUNTIME_DEV_PM_OPS(panfrost_pm_ops, panfrost_device_suspend, - panfrost_device_resume, NULL); +static int panfrost_device_resume(struct device *dev) +{ + struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { + ret =3D clk_enable(pfdev->clock); + if (ret) + return ret; + + if (pfdev->bus_clock) { + ret =3D clk_enable(pfdev->bus_clock); + if (ret) + goto err_bus_clk; + } + } + + ret =3D pm_runtime_force_resume(dev); + if (ret) + goto err_resume; + + return 0; + +err_resume: + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS) && pfdev->bus_clock) + clk_disable(pfdev->bus_clock); +err_bus_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) + clk_disable(pfdev->clock); + return ret; +} + +static int panfrost_device_suspend(struct device *dev) +{ + struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_suspend(dev); + if (ret) + return ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { + clk_disable(pfdev->clock); + + if (pfdev->bus_clock) + clk_disable(pfdev->bus_clock); + } + + return 0; +} + +EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) =3D { + RUNTIME_PM_OPS(panfrost_device_runtime_suspend, panfrost_device_runtime_r= esume, NULL) + SYSTEM_SLEEP_PM_OPS(panfrost_device_suspend, panfrost_device_resume) +}; diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index 1ef38f60d5dc..d7f179eb8ea3 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -25,6 +25,14 @@ struct panfrost_perfcnt; #define NUM_JOB_SLOTS 3 #define MAX_PM_DOMAINS 5 =20 +/** + * enum panfrost_gpu_pm - Supported kernel power management features + * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend + */ +enum panfrost_gpu_pm { + GPU_PM_CLK_DIS, +}; + struct panfrost_features { u16 id; u16 revision; @@ -75,6 +83,9 @@ struct panfrost_compatible { =20 /* Vendor implementation quirks callback */ void (*vendor_quirk)(struct panfrost_device *pfdev); + + /* Allowed PM features */ + u8 pm_features; }; =20 struct panfrost_device { --=20 2.42.0 From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A34C4332F for ; Thu, 2 Nov 2023 14:27:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235358AbjKBO1Q (ORCPT ); Thu, 2 Nov 2023 10:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376819AbjKBO1F (ORCPT ); Thu, 2 Nov 2023 10:27:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F60D187 for ; Thu, 2 Nov 2023 07:26:56 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9BAF466071C9; Thu, 2 Nov 2023 14:26:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935215; bh=nx8LZ5aZaZWmWIuhLZAit8ghPn7x7/L0ncMUkbIZjgQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PMgQ9tnHFhp1yKgV6pn/NrC94LTt4p5qBqRZP5sEUPj6lAi/ozfcY+qg53ZszDXDA /3rSKevUzVz+wrE+dZ5NmofgBKgUhXwnrsaSUFZ3rHZ71MbbBHws778kvKrJ/Fn5Ai F2Y/DgS/BZcojQLvZnLhFBcc8fmtbTQdonpdcL9/n6tYlpGC6OiJh3QUsDX+DL/KuP 51IoH4sa70l81OP0zElQRaIj5TRsXg+RpqYns+w8F56iuowRSjMbVdbKS32kzYPB6P EBigNWc/hQdsTIyz2smZ2f/sBfb1Eqgcb7y4Xk9jME7NfYoT0pk7UvsPVUbQKtecqC QjzmENZSB0mvg== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 4/6] drm/panfrost: Set clocks on/off during system sleep on MediaTek SoCs Date: Thu, 2 Nov 2023 15:26:41 +0100 Message-ID: <20231102142643.75288-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the MediaTek SoCs supported by Panfrost can switch the clocks off and on during system sleep to save some power without any user experience penalty. Measurements taken on multiple MediaTek SoCs show that adding this will not prolong the time that is required to resume the system in any meaningful way. As an example, for MT8195 - a "before" with only runtime PM operations (so, without turning on/off GPU clocks), and an "after" executing both the system sleep .resume() handler and .runtime_resume() (so the time refers to T_Resume + T_Runtime_Resume): Average Panfrost-only system sleep resume time, before: ~28000ns Average Panfrost-only system sleep resume time, after: ~33500ns Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 7cabf4e3d1f2..82f3c5fe9c58 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -734,6 +734,7 @@ static const struct panfrost_compatible mediatek_mt8183= _b_data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; @@ -742,6 +743,7 @@ static const struct panfrost_compatible mediatek_mt8186= _data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names =3D mediatek_mt8186_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; @@ -752,6 +754,7 @@ static const struct panfrost_compatible mediatek_mt8192= _data =3D { .supply_names =3D mediatek_mt8192_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names =3D mediatek_mt8192_pm_domains, + .pm_features =3D BIT(GPU_PM_CLK_DIS), }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.42.0 From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 064B7C4332F for ; Thu, 2 Nov 2023 14:27:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376861AbjKBO1V (ORCPT ); Thu, 2 Nov 2023 10:27:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376815AbjKBO1F (ORCPT ); Thu, 2 Nov 2023 10:27:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B96EA198 for ; Thu, 2 Nov 2023 07:26:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A047166071A9; Thu, 2 Nov 2023 14:26:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935216; bh=3dUd841wLvR/syQt4DasoXOByTVGgSmSqikDkfeYRv4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QgYvBWJLWs05RlEnORo1TJ541DBm/lIqdxky3UZXiB9beCz2/sWxF13bVJfF3MvYq SL4CGRyEoNLaTatGFsB+XbB/uvbO5wU0sXuwk/apYugYXba0sVlY1bGk/vhObyZWMr kXK2pgQ7m+NQ8TeGJgmYkj4noIZuN70fD8wfsHwmT/fOoZb5pDkm7vMm6lysznLZQ2 UE5sAIOPMPF5EABsVG1K0e7940ME9TSoIzHdcOpMWvOiT8kg9BQRwAtnAnEQEnz+of 5MCwKqnAEp/K/+k63jVOpIcQCZ+w41qBIuJjyGjbbRn/C/MQZTAUsJMTWyQp/FxQST LaOzlGkwrC1Ug== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 5/6] drm/panfrost: Implement ability to turn on/off regulators in suspend Date: Thu, 2 Nov 2023 15:26:42 +0100 Message-ID: <20231102142643.75288-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some platforms/SoCs can power off the GPU entirely by completely cutting off power, greatly enhancing battery time during system suspend: add a new pm_feature GPU_PM_VREG_OFF to allow turning off the GPU regulators during full suspend only on selected platforms. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_device.c | 19 ++++++++++++++++++- drivers/gpu/drm/panfrost/panfrost_device.h | 2 ++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index 2022ed76a620..51b22eb0971d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -431,10 +431,21 @@ static int panfrost_device_resume(struct device *dev) struct panfrost_device *pfdev =3D dev_get_drvdata(dev); int ret; =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) { + unsigned long freq =3D pfdev->pfdevfreq.fast_rate; + struct dev_pm_opp *opp; + + opp =3D dev_pm_opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + dev_pm_opp_put(opp); + dev_pm_opp_set_opp(dev, opp); + } + if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) { ret =3D clk_enable(pfdev->clock); if (ret) - return ret; + goto err_clk; =20 if (pfdev->bus_clock) { ret =3D clk_enable(pfdev->bus_clock); @@ -455,6 +466,9 @@ static int panfrost_device_resume(struct device *dev) err_bus_clk: if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) clk_disable(pfdev->clock); +err_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) + dev_pm_opp_set_opp(dev, NULL); return ret; } =20 @@ -474,6 +488,9 @@ static int panfrost_device_suspend(struct device *dev) clk_disable(pfdev->bus_clock); } =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) + dev_pm_opp_set_opp(dev, NULL); + return 0; } =20 diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index d7f179eb8ea3..0fc558db6bfd 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -28,9 +28,11 @@ struct panfrost_perfcnt; /** * enum panfrost_gpu_pm - Supported kernel power management features * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend + * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend */ enum panfrost_gpu_pm { GPU_PM_CLK_DIS, + GPU_PM_VREG_OFF, }; =20 struct panfrost_features { --=20 2.42.0 From nobody Wed Dec 31 13:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46C72C4167B for ; Thu, 2 Nov 2023 14:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376855AbjKBO1U (ORCPT ); Thu, 2 Nov 2023 10:27:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376829AbjKBO1F (ORCPT ); Thu, 2 Nov 2023 10:27:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B97D619F for ; Thu, 2 Nov 2023 07:26:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A44E466072EF; Thu, 2 Nov 2023 14:26:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1698935217; bh=L5OWGShxX3MAgjaEB+LbUFsMRGhPWkp6u6Ba4OZca4U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JYDSlsNvDIwZLm6W5E2xUHL2zehdH/PcUa/huAehUQr3Q+TQILITNrexes/qLdQkQ hBeovSOTEEpTvQnigwj96Tv91jdw5TaAKxvK8Uz5b7dFgJfR7QmxxU7mp9x4OMKNMn wtSAXXro5G9mjxz8mKQhDlwzRjQa+eqadVSl2mPNrtAFLawK7G3MrxMK0/MvMJHY32 HiTVq6yqPCvV9LhBSPJMbbkeLOq4T8FjcoYQJMtTyVO1lpqyP3REBUw2R77FXHGv+v oZL0gj7JJjlsaj720cy5UWKI7No/a4A6evEvZXyPCTmuAXN8SUiSIh6O9E3rAvPytI ajw6CRoFkkOzQ== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, wenst@chromium.org, AngeloGioacchino Del Regno , kernel@collabora.com Subject: [PATCH v2 6/6] drm/panfrost: Set regulators on/off during system sleep on MediaTek SoCs Date: Thu, 2 Nov 2023 15:26:43 +0100 Message-ID: <20231102142643.75288-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> References: <20231102142643.75288-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the MediaTek SoCs supported by Panfrost can completely cut power to the GPU during full system sleep without any user-noticeable delay in the resume operation, as shown by measurements taken on multiple MediaTek SoCs. As an example, for MT8195 - a "before" with only runtime PM operations (so, without turning on/off regulators), and an "after" executing both the system sleep .resume() handler and .runtime_resume() (so the time refers to T_Resume + T_Runtime_Resume): Average Panfrost-only system sleep resume time, before: ~33500ns Average Panfrost-only system sleep resume time, after: ~336200ns Keep in mind that this additional ~308200 nanoseconds delay happens only in resume from a full system suspend, and not in runtime PM operations, hence it is acceptable. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_drv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 82f3c5fe9c58..f63382d9ab04 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -734,7 +734,7 @@ static const struct panfrost_compatible mediatek_mt8183= _b_data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names =3D mediatek_mt8183_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const char * const mediatek_mt8186_pm_domains[] =3D { "core0", "cor= e1" }; @@ -743,7 +743,7 @@ static const struct panfrost_compatible mediatek_mt8186= _data =3D { .supply_names =3D mediatek_mt8183_b_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names =3D mediatek_mt8186_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; @@ -754,7 +754,7 @@ static const struct panfrost_compatible mediatek_mt8192= _data =3D { .supply_names =3D mediatek_mt8192_supplies, .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names =3D mediatek_mt8192_pm_domains, - .pm_features =3D BIT(GPU_PM_CLK_DIS), + .pm_features =3D BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.42.0