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[34.85.177.129]) by smtp.gmail.com with ESMTPSA id f2-20020a0ccc82000000b0066d1d2242desm937757qvl.120.2023.10.31.16.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 16:23:08 -0700 (PDT) From: Paz Zcharya X-Google-Original-From: Paz Zcharya To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Subrata Banik , Drew Davenport , Sean Paul , Manasi Navare , Paz Zcharya , Paz Zcharya , Andrzej Hajda , Ankit Nautiyal , Daniel Vetter , David Airlie , =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= , =?UTF-8?q?Jouni=20H=C3=B6gander?= , Khaled Almahallawy , Luca Coelho , Matt Roper , Mika Kahola , Stanislav Lisovskiy , Suraj Kandpal , Uma Shankar , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/i915/display: Only fail fastset on PSR2 Date: Tue, 31 Oct 2023 23:21:57 +0000 Message-ID: <20231031232245.1331194-1-pazz@google.com> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, i915 fails fastset if both the sink and the source support any version of PSR and regardless of the configuration setting of the driver (i.e., i915.enable_psr kernel argument). However, the implementation of PSR1 enable sequence is already seamless and works smoothly with fastset. Accordingly, do not fail fastset if PSR2 is not enabled. Signed-off-by: Paz Zcharya --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.h | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915= /display/intel_dp.c index e0e4cb529284..a1af96e31518 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct intel_enco= der *encoder, fastset =3D false; } =20 - if (CAN_PSR(intel_dp)) { - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute= PSR state\n", + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) { + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to PSR= 2\n", encoder->base.base.id, encoder->base.name); crtc_state->uapi.mode_changed =3D true; fastset =3D false; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i91= 5/display/intel_psr.c index 97d5eef10130..388bc3246db9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp *intel_d= p) } } =20 -static bool psr2_global_enabled(struct intel_dp *intel_dp) +bool psr2_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 =3D dp_to_i915(intel_dp); =20 diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i91= 5/display/intel_psr.h index 0b95e8aa615f..6f3c36389cd3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -21,6 +21,7 @@ struct intel_encoder; struct intel_plane; struct intel_plane_state; =20 +bool psr2_global_enabled(struct intel_dp *intel_dp); void intel_psr_init_dpcd(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); --=20 2.42.0.820.g83a721a137-goog