From nobody Wed Dec 31 17:59:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 035E3C4332F for ; Tue, 31 Oct 2023 20:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344911AbjJaUrm (ORCPT ); Tue, 31 Oct 2023 16:47:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234097AbjJaUrR (ORCPT ); Tue, 31 Oct 2023 16:47:17 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2257010A; Tue, 31 Oct 2023 13:47:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A77DDC0269; Tue, 31 Oct 2023 21:39:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1698784746; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=94/HYtm9FGvd4Dz1TUcprmc36le0K2PUtTaVtqso0A0=; b=pmPhAt7/Pmx02MqsAtw+PizNChGGvCQSsP0K0OzhcUJpbmcKyCN8TJPQ61Bwlbf7jUtFks L0tRaD2zRv+ryytcXWPZgNQL1XVDpuLHu5z7wIPQpSz5/cmXP+W9FFjV9WaUDS5pHNVn4Z DIUna+29/Ypu9OIRIjZl5hBkHfK9gR6ZuGhehenI9DDF3b4bMa5ry4M8l1fPaaN8KkvWFv npPQp4gXGWb6UnE9ZqZq28oGRzzvcEcE7nDOA162zTrpg9suYbeNVuMmXkJdCD02VjZT6y TqID3uKMKlw5MG6IKrhvuNgd8MWGLMYXvPf+Yb/+tUlpQtcA1Nnoon9qNaudDQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH 01/14] arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM Date: Tue, 31 Oct 2023 21:37:38 +0100 Message-ID: <20231031203836.3888404-2-frieder@fris.de> In-Reply-To: <20231031203836.3888404-1-frieder@fris.de> References: <20231031203836.3888404-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The Kontron Electronics BL i.MX8MM has oboard disply bridges for DSI->HDMI and DSI->LVDS conversion. The DSI interface is muxed by a GPIO-controlled switch to one of these two bridges. By default the HDMI bridge is enabled. The LVDS bridge can be selected by loading an additional (panel-specific) overlay. Signed-off-by: Frieder Schrempf --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index dcec57c20399e..f1326bf634a7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -25,6 +25,17 @@ osc_can: clock-osc-can { clock-output-names =3D "osc-can"; }; =20 + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_in_conn: endpoint { + remote-endpoint =3D <&bridge_out_conn>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -132,6 +143,93 @@ ethphy: ethernet-phy@0 { }; }; =20 +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + + dsi_mux_sel: dsi-mux-sel-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "dsi-mux-sel"; + }; + + dsi-mux-oe-hog { + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_LOW>; + output-high; + line-name =3D "dsi-mux-oe"; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + hdmi: hdmi@39 { + compatible =3D "adi,adv7535"; + reg =3D <0x39>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adv7535>; + + interrupt-parent =3D <&gpio4>; + interrupts =3D <16 IRQ_TYPE_LEVEL_LOW>; + + adi,dsi-lanes =3D <4>; + + a2vdd-supply =3D <®_vdd_1v8>; + avdd-supply =3D <®_vdd_1v8>; + dvdd-supply =3D <®_vdd_1v8>; + pvdd-supply =3D <®_vdd_1v8>; + v1p2-supply =3D <®_vdd_1v8>; + v3p3-supply =3D <®_vdd_3v3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + bridge_in_dsi_hdmi: endpoint { + remote-endpoint =3D <&dsi_out_bridge>; + }; + }; + + port@1 { + reg =3D <1>; + bridge_out_conn: endpoint { + remote-endpoint =3D <&hdmi_in_conn>; + }; + }; + }; + }; + + lvds: bridge@2c { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2c>; + enable-gpios =3D <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sn65dsi84>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + bridge_in_dsi_lvds: endpoint { + remote-endpoint =3D <&dsi_out_bridge>; + data-lanes =3D <1 2 3 4>; + }; + }; + }; + }; +}; + &i2c4 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; @@ -144,6 +242,30 @@ rx8900: rtc@32 { }; }; =20 +&lcdif { + status =3D "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency =3D <54000000>; + /* + * Let the driver calculate an appropriate clock rate based on the pixel + * clock instead of using the fixed value from imx8mm.dtsi. + */ + /delete-property/ samsung,pll-clock-frequency; + status =3D "okay"; + + ports { + port@1 { + reg =3D <1>; + + dsi_out_bridge: endpoint { + remote-endpoint =3D <&bridge_in_dsi_hdmi>; + }; + }; + }; +}; + &pwm2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pwm2>; @@ -207,6 +329,12 @@ &iomuxc { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_gpio>; =20 + pinctrl_adv7535: adv7535grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 + >; + }; + pinctrl_can: cangrp { fsl,pins =3D < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 @@ -277,6 +405,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; =20 + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins =3D < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -290,6 +432,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 >; }; =20 + pinctrl_sn65dsi84: sn65dsi84grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins =3D < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 --=20 2.42.0