From nobody Wed Dec 17 08:00:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF070C4332F for ; Tue, 31 Oct 2023 05:27:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229990AbjJaF1Q (ORCPT ); Tue, 31 Oct 2023 01:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbjJaF1N (ORCPT ); Tue, 31 Oct 2023 01:27:13 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28041F3; Mon, 30 Oct 2023 22:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1698730031; x=1730266031; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zSkOZ12TKc1wwVLKvzsXxeC5tl7G/J3ooSzJ/My7COk=; b=I0iwVpeq/sEYsS8YRv41Hy3+VDNQTIeFfh6zjjFb8AlmAlVDK751VBoY EUBNyWu2HqSbOdanj7yAOsJTD6iPfyB38LJ3MVNwrpzCJQxvvdlcfOgXK qxbMX4kOX0E7kgRydc8PW0402phC8f/9eVXefXrqjdBBDWFdpVXH5n5mM EtFDLZh+MmNVFy6o4aFBPiMSLEska4hiBs1N4n7XrQ0w08k6tDT0OP6Bo +1YABoPHvQyNbKkItz4XjQOKo+Hk1D8BUz4EdpdMb0BhLn39SBQUwRhWF iXXTFBAfbMwcNS5VxOHaYbv/v69+dfJsHxP7TM1g2g4vhET1lODJQjpzT A==; X-CSE-ConnectionGUID: PIbu8/OSQLmLuwlEm2kgKw== X-CSE-MsgGUID: 4ywV+5BdQyKhiYDhnoDz9A== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="11483952" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Oct 2023 22:27:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 30 Oct 2023 22:26:49 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 30 Oct 2023 22:26:45 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , Subject: [PATCH v4 1/4] dmaengine: sf-pdma: Support of_dma_controller_register() Date: Tue, 31 Oct 2023 10:57:50 +0530 Message-ID: <20231031052753.3430169-2-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031052753.3430169-1-shravan.chippa@microchip.com> References: <20231031052753.3430169-1-shravan.chippa@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Update sf-pdma driver to adopt generic DMA device tree bindings. It calls of_dma_controller_register() with sf-pdma specific of_dma_xlate to get the generic DMA device tree helper support and the DMA clients can look up the sf-pdma controller using standard APIs. Signed-off-by: Shravan Chippa --- drivers/dma/sf-pdma/sf-pdma.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index d1c6956af452..4c456bdef882 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include =20 #include "sf-pdma.h" @@ -490,6 +491,33 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma) } } =20 +static struct dma_chan *sf_pdma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct sf_pdma *pdma =3D ofdma->of_dma_data; + struct device *dev =3D pdma->dma_dev.dev; + struct sf_pdma_chan *chan; + struct dma_chan *c; + u32 channel_id; + + if (dma_spec->args_count !=3D 1) { + dev_err(dev, "Bad number of cells\n"); + return NULL; + } + + channel_id =3D dma_spec->args[0]; + + chan =3D &pdma->chans[channel_id]; + + c =3D dma_get_slave_channel(&chan->vchan.chan); + if (!c) { + dev_err(dev, "No more channels available\n"); + return NULL; + } + + return c; +} + static int sf_pdma_probe(struct platform_device *pdev) { struct sf_pdma *pdma; @@ -563,7 +591,20 @@ static int sf_pdma_probe(struct platform_device *pdev) return ret; } =20 + ret =3D of_dma_controller_register(pdev->dev.of_node, + sf_pdma_of_xlate, pdma); + if (ret < 0) { + dev_err(&pdev->dev, + "Can't register SiFive Platform OF_DMA. (%d)\n", ret); + goto err_unregister; + } + return 0; + +err_unregister: + dma_async_device_unregister(&pdma->dma_dev); + + return ret; } =20 static int sf_pdma_remove(struct platform_device *pdev) @@ -583,6 +624,9 @@ static int sf_pdma_remove(struct platform_device *pdev) tasklet_kill(&ch->err_tasklet); } =20 + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&pdma->dma_dev); =20 return 0; --=20 2.34.1 From nobody Wed Dec 17 08:00:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 628CAC4167D for ; Tue, 31 Oct 2023 05:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbjJaF1I (ORCPT ); Tue, 31 Oct 2023 01:27:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229990AbjJaF1E (ORCPT ); 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d="scan'208";a="10872649" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Oct 2023 22:27:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 30 Oct 2023 22:26:56 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 30 Oct 2023 22:26:51 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v4 2/4] dt-bindings: dma: sf-pdma: add new compatible name Date: Tue, 31 Oct 2023 10:57:51 +0530 Message-ID: <20231031052753.3430169-3-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031052753.3430169-1-shravan.chippa@microchip.com> References: <20231031052753.3430169-1-shravan.chippa@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Add new compatible name microchip,mpfs-pdma to support out of order dma transfers Reviewed-by: Conor Dooley Signed-off-by: Shravan Chippa --- .../devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.y= aml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index a1af0b906365..3b22183a1a37 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -29,6 +29,7 @@ properties: compatible: items: - enum: + - microchip,mpfs-pdma - sifive,fu540-c000-pdma - const: sifive,pdma0 description: --=20 2.34.1 From nobody Wed Dec 17 08:00:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF4E6C4332F for ; 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X-CSE-ConnectionGUID: r/YQwnBYQ0ihAZZkayWq2A== X-CSE-MsgGUID: wnCkYct9QTSxlNM17VuO5Q== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,265,1694761200"; d="scan'208";a="11147693" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Oct 2023 22:27:37 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 30 Oct 2023 22:27:03 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 30 Oct 2023 22:26:58 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , , Emil Renner Berthing Subject: [PATCH v4 3/4] dmaengine: sf-pdma: add mpfs-pdma compatible name Date: Tue, 31 Oct 2023 10:57:52 +0530 Message-ID: <20231031052753.3430169-4-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031052753.3430169-1-shravan.chippa@microchip.com> References: <20231031052753.3430169-1-shravan.chippa@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Sifive platform dma does not allow out-of-order transfers, Add a PolarFire SoC specific compatible and code to support for out-of-order dma transfers Reviewed-by: Emil Renner Berthing Signed-off-by: Shravan Chippa --- drivers/dma/sf-pdma/sf-pdma.c | 27 ++++++++++++++++++++++++--- drivers/dma/sf-pdma/sf-pdma.h | 8 +++++++- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index 4c456bdef882..82ab12c40743 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -25,6 +25,8 @@ =20 #include "sf-pdma.h" =20 +#define PDMA_QUIRK_NO_STRICT_ORDERING BIT(0) + #ifndef readq static inline unsigned long long readq(void __iomem *addr) { @@ -66,7 +68,7 @@ static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_= pdma_chan *chan) static void sf_pdma_fill_desc(struct sf_pdma_desc *desc, u64 dst, u64 src, u64 size) { - desc->xfer_type =3D PDMA_FULL_SPEED; + desc->xfer_type =3D desc->chan->pdma->transfer_type; desc->xfer_size =3D size; desc->dst_addr =3D dst; desc->src_addr =3D src; @@ -520,6 +522,7 @@ static struct dma_chan *sf_pdma_of_xlate(struct of_phan= dle_args *dma_spec, =20 static int sf_pdma_probe(struct platform_device *pdev) { + const struct sf_pdma_driver_platdata *ddata; struct sf_pdma *pdma; int ret, n_chans; const enum dma_slave_buswidth widths =3D @@ -545,6 +548,14 @@ static int sf_pdma_probe(struct platform_device *pdev) =20 pdma->n_chans =3D n_chans; =20 + pdma->transfer_type =3D PDMA_FULL_SPEED | PDMA_STRICT_ORDERING; + + ddata =3D device_get_match_data(&pdev->dev); + if (ddata) { + if (ddata->quirks & PDMA_QUIRK_NO_STRICT_ORDERING) + pdma->transfer_type &=3D ~PDMA_STRICT_ORDERING; + } + pdma->membase =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pdma->membase)) return PTR_ERR(pdma->membase); @@ -632,9 +643,19 @@ static int sf_pdma_remove(struct platform_device *pdev) return 0; } =20 +static const struct sf_pdma_driver_platdata mpfs_pdma =3D { + .quirks =3D PDMA_QUIRK_NO_STRICT_ORDERING, +}; + static const struct of_device_id sf_pdma_dt_ids[] =3D { - { .compatible =3D "sifive,fu540-c000-pdma" }, - { .compatible =3D "sifive,pdma0" }, + { + .compatible =3D "sifive,fu540-c000-pdma", + }, { + .compatible =3D "sifive,pdma0", + }, { + .compatible =3D "microchip,mpfs-pdma", + .data =3D &mpfs_pdma, + }, {}, }; MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids); diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h index 5c398a83b491..267e79a5e0a5 100644 --- a/drivers/dma/sf-pdma/sf-pdma.h +++ b/drivers/dma/sf-pdma/sf-pdma.h @@ -48,7 +48,8 @@ #define PDMA_ERR_STATUS_MASK GENMASK(31, 31) =20 /* Transfer Type */ -#define PDMA_FULL_SPEED 0xFF000008 +#define PDMA_FULL_SPEED 0xFF000000 +#define PDMA_STRICT_ORDERING BIT(3) =20 /* Error Recovery */ #define MAX_RETRY 1 @@ -112,8 +113,13 @@ struct sf_pdma { struct dma_device dma_dev; void __iomem *membase; void __iomem *mappedbase; + u32 transfer_type; u32 n_chans; struct sf_pdma_chan chans[]; }; =20 +struct sf_pdma_driver_platdata { + u32 quirks; +}; + #endif /* _SF_PDMA_H */ --=20 2.34.1 From nobody Wed Dec 17 08:00:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B3E0C4167B for ; Tue, 31 Oct 2023 05:27:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231871AbjJaF1x (ORCPT ); Tue, 31 Oct 2023 01:27:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230458AbjJaF1t (ORCPT ); Tue, 31 Oct 2023 01:27:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEF13127; Mon, 30 Oct 2023 22:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; 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Mon, 30 Oct 2023 22:27:10 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 30 Oct 2023 22:27:05 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v4 4/4] riscv: dts: microchip: add specific compatible for mpfs' pdma Date: Tue, 31 Oct 2023 10:57:53 +0530 Message-ID: <20231031052753.3430169-5-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031052753.3430169-1-shravan.chippa@microchip.com> References: <20231031052753.3430169-1-shravan.chippa@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Add specific compatible for PolarFire SoC for The SiFive PDMA driver Reviewed-by: Conor Dooley Signed-off-by: Shravan Chippa --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 104504352e99..f43486e9a090 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -221,7 +221,7 @@ plic: interrupt-controller@c000000 { }; =20 pdma: dma-controller@3000000 { - compatible =3D "sifive,fu540-c000-pdma", "sifive,pdma0"; + compatible =3D "microchip,mpfs-pdma", "sifive,pdma0"; reg =3D <0x0 0x3000000 0x0 0x8000>; interrupt-parent =3D <&plic>; interrupts =3D <5 6>, <7 8>, <9 10>, <11 12>; --=20 2.34.1