From nobody Wed Dec 31 17:56:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C36CC4167D for ; Tue, 31 Oct 2023 02:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234770AbjJaCzY (ORCPT ); Mon, 30 Oct 2023 22:55:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231175AbjJaCzV (ORCPT ); Mon, 30 Oct 2023 22:55:21 -0400 Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AD69CC; Mon, 30 Oct 2023 19:55:17 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R251e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045176;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0VvFgpU9_1698720913; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VvFgpU9_1698720913) by smtp.aliyun-inc.com; Tue, 31 Oct 2023 10:55:14 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v4 1/2] dmaengine: idxd: Protect int_handle field in hw descriptor Date: Tue, 31 Oct 2023 10:55:10 +0800 Message-Id: <20231031025511.1516342-2-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231031025511.1516342-1-guanjun@linux.alibaba.com> References: <20231031025511.1516342-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guanjun The int_handle field in hw descriptor should also be protected by wmb() before possibly triggering a DMA read. Fixes: ec0d64231615 (dmaengine: idxd: embed irq_entry in idxd_wq struct) Signed-off-by: Guanjun Reviewed-by: Dave Jiang Reviewed-by: Fenghua Yu --- drivers/dma/idxd/submit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c index c01db23e3333..3f922518e3a5 100644 --- a/drivers/dma/idxd/submit.c +++ b/drivers/dma/idxd/submit.c @@ -182,13 +182,6 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_d= esc *desc) =20 portal =3D idxd_wq_portal_addr(wq); =20 - /* - * The wmb() flushes writes to coherent DMA data before - * possibly triggering a DMA read. The wmb() is necessary - * even on UP because the recipient is a device. - */ - wmb(); - /* * Pending the descriptor to the lockless list for the irq_entry * that we designated the descriptor to. @@ -199,6 +192,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_d= esc *desc) llist_add(&desc->llnode, &ie->pending_llist); } =20 + /* + * The wmb() flushes writes to coherent DMA data before + * possibly triggering a DMA read. The wmb() is necessary + * even on UP because the recipient is a device. + */ + wmb(); + if (wq_dedicated(wq)) { iosubmit_cmds512(portal, desc->hw, 1); } else { --=20 2.39.3 From nobody Wed Dec 31 17:56:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95CB7C4167B for ; Tue, 31 Oct 2023 02:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234843AbjJaCz0 (ORCPT ); Mon, 30 Oct 2023 22:55:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231825AbjJaCzV (ORCPT ); Mon, 30 Oct 2023 22:55:21 -0400 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 090A3DA; Mon, 30 Oct 2023 19:55:18 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R691e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0VvFgpUV_1698720914; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VvFgpUV_1698720914) by smtp.aliyun-inc.com; Tue, 31 Oct 2023 10:55:15 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v4 2/2] dmaengine: idxd: Fix incorrect descriptions for GRPCFG register Date: Tue, 31 Oct 2023 10:55:11 +0800 Message-Id: <20231031025511.1516342-3-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231031025511.1516342-1-guanjun@linux.alibaba.com> References: <20231031025511.1516342-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guanjun Fix incorrect descriptions for the GRPCFG register which has three sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG). No functional changes Signed-off-by: Guanjun Reviewed-by: Dave Jiang Reviewed-by: Fenghua Yu --- drivers/dma/idxd/registers.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..315c004f58e4 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,14 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to acc= ess. + * The GRPCFG register block is divided into three sub-registers, which + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move + * to the register block that contains the three sub-registers. + * Each register block is 64bits. And the ofs gives us the offset + * within the GRPWQCFG register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) --=20 2.39.3