From nobody Wed Dec 31 20:03:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9280EC4332F for ; Tue, 31 Oct 2023 02:20:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234767AbjJaCUg (ORCPT ); Mon, 30 Oct 2023 22:20:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231228AbjJaCU2 (ORCPT ); Mon, 30 Oct 2023 22:20:28 -0400 Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F8FDE9; Mon, 30 Oct 2023 19:20:25 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R131e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0VvFn-Ut_1698718821; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VvFn-Ut_1698718821) by smtp.aliyun-inc.com; Tue, 31 Oct 2023 10:20:21 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v2 2/2] dmaengine: idxd: Fix incorrect descriptions for GRPCFG register Date: Tue, 31 Oct 2023 10:20:17 +0800 Message-Id: <20231031022017.1515471-3-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231031022017.1515471-1-guanjun@linux.alibaba.com> References: <20231031022017.1515471-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guanjun Fix incorrect descriptions for the GRPCFG register which has three sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG). No functional changes Signed-off-by: Guanjun Reviewed-by: Dave Jiang --- drivers/dma/idxd/registers.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..133bd0c170ae 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,15 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to acc= ess. + * The GRPCFG register block is divided into three sub-registers, which + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group + * allows us to move to the register group that's for that contains the + * three sub-registers. + * Each register is 64bits. And the ofs in GRPWQCFG gives us the offset + * within the GRPCFG register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) --=20 2.39.3