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Lin" , , , , , Moudy Ho Subject: [PATCH v8 3/3] arm64: dts: mediatek: mt8195: add MDP3 nodes Date: Mon, 30 Oct 2023 17:48:40 +0800 Message-ID: <20231030094840.2479-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030094840.2479-1-moudy.ho@mediatek.com> References: <20231030094840.2479-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.986800-8.000000 X-TMASE-MatchedRID: k8Cd32tj8sGuhCBFl/b63kfhraIl1XgxkUtSee+57IFAtKM3hDDAfGb6 PphVtfZgTPeZkapFnH8kAzbREWz9my2w9y+uUSpWCz1WR8KHe4B3Bf9JIqsoeKkp8F/qKdS/o8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtQE1HOv+iFzIMkXusMQAzBhzBiOOd3fxS6r0Fmkrc7v02LO YqWklQDw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.986800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B5F2130F639A1769BDD3928828755A48F0A1E309AAB00ABE8BCA52BD8A0571712000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 392 +++++++++++++++++++++++ 1 file changed, 392 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index a360fb785bb6..602620dbcc8d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1961,6 +1961,115 @@ #clock-cells =3D <1>; }; =20 + dma-controller@14001000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes =3D <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells =3D <1>; + }; + + display@14002000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_FG>; + }; + + display@14003000 { + compatible =3D "mediatek,mt8195-mdp3-stitch"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_STITCH>; + }; + + display@14004000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_HDR>; + }; + + display@14005000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14006000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RSZ>; + }; + + display@14007000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; + + display@14008000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14008000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_OVL>; + }; + + display@1400a000 { + compatible =3D "mediatek,mt8195-mdp3-padding"; + reg =3D <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_PADDING>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400b000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TCC>; + }; + + dma-controller@1400c000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + #dma-cells =3D <1>; + }; + mutex@1400f000 { compatible =3D "mediatek,mt8195-vpp-mutex"; reg =3D <0 0x1400f000 0 0x1000>; @@ -2108,6 +2217,289 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; =20 + display@14f06000 { + compatible =3D "mediatek,mt8195-mdp3-split"; + reg =3D <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f07000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + }; + + dma-controller@14f08000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f09000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f0a000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + display@14f0b000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + }; + + display@14f0c000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + }; + + display@14f0d000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + }; + + display@14f0e000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + }; + + display@14f0f000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + }; + + display@14f10000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + }; + + display@14f11000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f11000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f12000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f12000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f13000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f13000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f14000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + }; + + display@14f15000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; + }; + + display@14f16000 { + compatible =3D "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; + }; + + display@14f17000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + }; + + display@14f18000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + }; + + display@14f19000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + }; + + display@14f1a000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1b000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1c000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1c000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1d000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + interrupts =3D ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1e000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1e000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1f000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14f1f000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; + }; + + display@14f20000 { + compatible =3D "mediatek,mt8195-mdp3-padding"; + reg =3D <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f21000 { + compatible =3D "mediatek,mt8195-mdp3-padding"; + reg =3D <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f22000 { + compatible =3D "mediatek,mt8195-mdp3-padding"; + reg =3D <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + dma-controller@14f23000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f24000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f25000 { + compatible =3D "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.18.0