From nobody Wed Dec 31 22:07:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AD08C4332F for ; Mon, 30 Oct 2023 07:24:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232038AbjJ3HY6 (ORCPT ); Mon, 30 Oct 2023 03:24:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231898AbjJ3HYp (ORCPT ); Mon, 30 Oct 2023 03:24:45 -0400 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F8A4DA for ; Mon, 30 Oct 2023 00:24:43 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1698650681; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VdRmvtayK3v7BctwV3dFsg7DY1HPt865jjTnPuCP2sQ=; b=pDpRB6l3Quf6ybG+onRldnpSvB+dCBObKHswAeimDoAZMtcUTokGbt4/JPd3W2PbLhwDWR wNchHBOJXJVRNn58YmNFpQSlkoyVeS3m8jA+eg0cHGFWUHaew/gcEXrBArekB3MNmZMsHw 50wL202vUwtCX/1h83buXZwu0yxSP5lYFE9Oyy7ZDOCNwffnX2fs+kawlwWYgQbYPqdHnC 7bBN27Og8F6GPx6ffXESqOxkZVjxS67NAO9fm2Ao/jrYi/BxBaiym5MmyAMWsqfwzNhjay yYT6Sp6guDFSZeBrjcZ99VwlPH/dGj7IWI3hxAQItHkP/ihuOO27gKSFSa/YGA== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Bjorn Andersson , Chris Morgan , Jagan Teki , Linus Walleij , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 3/7] drm/panel: nv3052c: Allow specifying registers per panel Date: Mon, 30 Oct 2023 18:23:34 +1100 Message-ID: <20231030072337.2341539-5-contact@jookia.org> In-Reply-To: <20231030072337.2341539-2-contact@jookia.org> References: <20231030072337.2341539-2-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Panel initialization registers are per-display and not tied to the controller itself. Different panels will specify their own registers. Attach the sequences to the panel info struct so future panels can specify their own sequences. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 24 ++++++++++++------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 90dea21f9856..b0114b5e8554 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -20,11 +20,18 @@ #include #include =20 +struct nv3052c_reg { + u8 cmd; + u8 val; +}; + struct nv3052c_panel_info { const struct drm_display_mode *display_modes; unsigned int num_modes; u16 width_mm, height_mm; u32 bus_format, bus_flags; + const struct nv3052c_reg *panel_regs; + unsigned int panel_regs_len; }; =20 struct nv3052c { @@ -36,12 +43,7 @@ struct nv3052c { struct gpio_desc *reset_gpio; }; =20 -struct nv3052c_reg { - u8 cmd; - u8 val; -}; - -static const struct nv3052c_reg nv3052c_panel_regs[] =3D { +static const struct nv3052c_reg ltk035c5444t_panel_regs[] =3D { // EXTC Command set enable, select page 1 { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, // Mostly unknown registers @@ -244,6 +246,8 @@ static inline struct nv3052c *to_nv3052c(struct drm_pan= el *panel) static int nv3052c_prepare(struct drm_panel *panel) { struct nv3052c *priv =3D to_nv3052c(panel); + const struct nv3052c_reg *panel_regs =3D priv->panel_info->panel_regs; + unsigned int panel_regs_len =3D priv->panel_info->panel_regs_len; struct mipi_dbi *dbi =3D &priv->dbi; unsigned int i; int err; @@ -260,9 +264,9 @@ static int nv3052c_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(priv->reset_gpio, 0); usleep_range(5000, 20000); =20 - for (i =3D 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) { - err =3D mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd, - nv3052c_panel_regs[i].val); + for (i =3D 0; i < panel_regs_len; i++) { + err =3D mipi_dbi_command(dbi, panel_regs[i].cmd, + panel_regs[i].val); =20 if (err) { dev_err(priv->dev, "Unable to set register: %d\n", err); @@ -463,6 +467,8 @@ static const struct nv3052c_panel_info ltk035c5444t_pan= el_info =3D { .height_mm =3D 64, .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D ltk035c5444t_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(ltk035c5444t_panel_regs), }; =20 static const struct spi_device_id nv3052c_ids[] =3D { --=20 2.42.0