From nobody Wed Dec 31 21:35:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC0EEC4332F for ; Sun, 29 Oct 2023 17:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230272AbjJ2Rss (ORCPT ); Sun, 29 Oct 2023 13:48:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbjJ2Rsp (ORCPT ); Sun, 29 Oct 2023 13:48:45 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564E0B4; Sun, 29 Oct 2023 10:48:43 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39TArdWt026126; Sun, 29 Oct 2023 10:48:27 -0700 DKIM-Signature: v=1; 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charset="utf-8" From: Elad Nachman Add ac5 dts files to the list of maintained Marvell Armada dts files Signed-off-by: Elad Nachman Reviewed-by: Andrew Lunn --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index bdc4638b2df5..199225588567 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2323,6 +2323,7 @@ F: arch/arm/boot/dts/marvell/armada* F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ +F: arch/arm64/boot/dts/marvell/ac5* F: arch/arm64/boot/dts/marvell/armada* F: arch/arm64/boot/dts/marvell/cn913* F: drivers/clk/mvebu/ --=20 2.25.1 From nobody Wed Dec 31 21:35:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1CE9C4167D for ; Sun, 29 Oct 2023 17:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbjJ2Rs6 (ORCPT ); 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Sun, 29 Oct 2023 10:48:31 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 29 Oct 2023 10:48:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 29 Oct 2023 10:48:29 -0700 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 4DA0C3F70A0; Sun, 29 Oct 2023 10:48:26 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , , , CC: , Subject: [PATCH v4 2/3] dt-bindings: arm64: dts: add dt-bindings for Marvell COM Express boards Date: Sun, 29 Oct 2023 19:48:13 +0200 Message-ID: <20231029174814.559583-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231029174814.559583-1-enachman@marvell.com> References: <20231029174814.559583-1-enachman@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: R5h-RK8kAZFutVQB-Qu0HCsCwG0c6VI3 X-Proofpoint-GUID: R5h-RK8kAZFutVQB-Qu0HCsCwG0c6VI3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-29_06,2023-10-27_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Elad Nachman Add dt bindings for: CN9130 COM Express CPU module CN9131 COM Express CPU module AC5X RD COM Express Type 7 carrier board. AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module. Signed-off-by: Elad Nachman --- .../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++++++++++++++ .../bindings/arm/marvell/marvell,ac5.yaml | 14 ++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yam= l b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml index 52d78521e412..7e0ac5110eef 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml @@ -60,4 +60,19 @@ properties: - const: marvell,armada-ap807-quad - const: marvell,armada-ap807 =20 + - description: Armada CN9130 SoC without external CP as COM Express = CPU module + items: + - const: marvell,cn9130-cpu-module + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + + - description: Armada CN9131 SoC with one external CP as COM Express= CPU module + items: + - const: marvell,cn9131-cpu-module + - const: marvell,cn9131 + - const: marvell,cn9130 + - const: marvell,armada-ap807-quad + - const: marvell,armada-ap807 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml= b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml index 8960fb8b2b2f..734e1716a3e9 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml @@ -27,6 +27,20 @@ properties: - const: marvell,ac5x - const: marvell,ac5 =20 + - description: Alleycat5X (98DX35xx) Reference Design as COM Express= Carrier + items: + - enum: + - marvell,rd-ac5x-carrier + - const: marvell,ac5x + + - description: + Alleycat5X (98DX35xx) Reference Design as COM Express Carrier p= lus + Armada CN9131 COM Express CPU module + items: + - enum: + - marvell,rd-ac5x-carrier-with-cn9131 + - const: marvell,ac5x + additionalProperties: true =20 ... --=20 2.25.1 From nobody Wed Dec 31 21:35:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 004BAC41535 for ; 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Sun, 29 Oct 2023 10:48:30 -0700 (PDT) From: Elad Nachman To: , , , , , , , , , , , CC: , Subject: [PATCH v4 3/3] arm64: dts: cn913x: add device trees for COM Express boards Date: Sun, 29 Oct 2023 19:48:14 +0200 Message-ID: <20231029174814.559583-4-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231029174814.559583-1-enachman@marvell.com> References: <20231029174814.559583-1-enachman@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: VVkDGiGjzkRIDcMOl4KsinWrNWFnd54F X-Proofpoint-GUID: VVkDGiGjzkRIDcMOl4KsinWrNWFnd54F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-29_06,2023-10-27_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Elad Nachman Add support for CN9130 and CN9131 COM Express Type 7 CPU module boards by Marvell. Define these COM Express CPU modules as dtsi and provide a dtsi file for a carrier board (Marvell AC5X RD COM Express type 7 carrier board). This Carrier board only utilizes the PCIe link, hence no special device / driver support is provided by this dtsi file. Finally, provide a dts file for the com express carrier and CPU module combination. These COM Express boards differ from the existing CN913x DB boards by the type of ethernet connection (RGMII), the type of voltage regulators (not i2c expander based) and the USB phy (not UTMI based). Note - PHY + RGMII connector is OOB on CPU module. CN9131 COM Express board is basically CN9130 COM Express board with an additional CP115 I/O co-processor, which in this case provides an additional USB host controller on the board. Signed-off-by: Elad Nachman --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../marvell/ac5x-rd-carrier-with-cn9131.dts | 20 ++++ .../boot/dts/marvell/ac5x-rd-carrier.dtsi | 15 +++ .../dts/marvell/cn9130-db-comexpress.dtsi | 101 ++++++++++++++++ .../dts/marvell/cn9131-db-comexpress.dtsi | 113 ++++++++++++++++++ 5 files changed, 250 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131= .dts create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/mar= vell/Makefile index 79ac09b58a89..88c0f357a778 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5x-rd-carrier-with-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5-98dx35xx-rd.dtb diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts b/= arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts new file mode 100644 index 000000000000..9ca2725184e2 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * Utilizing the CN913x COM Express CPU module board. + * This specific board only maintains a PCIe link with the CPU CPU module + * module, which does not require any special DTS definitions. + */ + +#include "cn9131-db-comexpress.dtsi" +#include "ac5x-rd-carrier.dtsi" + +/ { + model =3D "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with C= N9131 CPU module"; + compatible =3D "marvell,rd-ac5x-carrier-with-cn9131", "marvell,rd-ac5x-ca= rrier", + "marvell,cn9131", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/= boot/dts/marvell/ac5x-rd-carrier.dtsi new file mode 100644 index 000000000000..6d976d268deb --- /dev/null +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * This specific board only maintains a PCIe link with the CPU CPU module + * module, which does not require any special DTS definitions. + */ + +/ { + model =3D "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board"; + compatible =3D "marvell,rd-ac5x-carrier", "marvell,cn9131", "marvell,cn91= 30", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/a= rm64/boot/dts/marvell/cn9130-db-comexpress.dtsi new file mode 100644 index 000000000000..1180066a3cf2 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9130-DB Com Express CPU module board. + */ + +#include "cn9130-db.dtsi" + +/ { + model =3D "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; + compatible =3D "marvell,cn9130-cpu-module", "marvell,cn9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x2 0x00000000>; + }; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt =3D <1800000>; + states =3D <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status =3D "disabled"; +}; + +&cp0_reg_sd_vccq { + status =3D "disabled"; +}; + +&cp0_sdhci0 { + status =3D "disabled"; +}; + +&cp0_eth0 { + status =3D "disabled"; +}; + +&cp0_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +&cp0_eth2 { + status =3D "disabled"; +}; + +&cp0_mdio { + status =3D "okay"; + pinctrl-0 =3D <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status =3D "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status =3D "disabled"; +}; + +&cp0_spi1 { + status =3D "okay"; +}; + +&cp0_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy0>; + phy-names =3D "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy1>; + phy-names =3D "usb"; + /delete-property/ phys; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/a= rm64/boot/dts/marvell/cn9131-db-comexpress.dtsi new file mode 100644 index 000000000000..0d2d2a119253 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the CN9131-DB Com Express CPU module board. + */ + +#include "cn9131-db.dtsi" + +/ { + model =3D "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board"; + compatible =3D "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn= 9130", + "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x2 0x00000000>; + }; + +}; + +&ap0_reg_sd_vccq { + regulator-max-microvolt =3D <1800000>; + states =3D <1800000 0x1 1800000 0x0>; + /delete-property/ gpios; +}; + +&cp0_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_usb3_vbus1 { + /delete-property/ gpio; +}; + +&cp1_reg_usb3_vbus0 { + /delete-property/ gpio; +}; + +&cp0_reg_sd_vcc { + status =3D "disabled"; +}; + +&cp0_reg_sd_vccq { + status =3D "disabled"; +}; + +&cp0_sdhci0 { + status =3D "disabled"; +}; + +&cp0_eth0 { + status =3D "disabled"; +}; + +&cp0_eth1 { + status =3D "okay"; + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; +}; + +&cp0_eth2 { + status =3D "disabled"; +}; + +&cp0_mdio { + status =3D "okay"; + pinctrl-0 =3D <&cp0_ge_mdio_pins>; + phy0: ethernet-phy@0 { + status =3D "okay"; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "ge"; + }; + }; +}; + +&cp0_sdhci0 { + status =3D "disabled"; +}; + +&cp0_spi1 { + status =3D "okay"; +}; + +&cp0_usb3_0 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy0>; + phy-names =3D "usb"; + /delete-property/ phys; +}; + +&cp0_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp0_usb3_0_phy1>; + phy-names =3D "usb"; + /delete-property/ phys; +}; + +&cp1_usb3_1 { + status =3D "okay"; + usb-phy =3D <&cp1_usb3_0_phy0>; + /* Generic PHY, providing serdes lanes */ + phys =3D <&cp1_comphy3 1>; + phy-names =3D "usb"; +}; --=20 2.25.1