From nobody Tue Dec 16 21:51:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD735C4167B for ; Sun, 29 Oct 2023 08:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbjJ2IBF (ORCPT ); Sun, 29 Oct 2023 04:01:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229805AbjJ2IA7 (ORCPT ); Sun, 29 Oct 2023 04:00:59 -0400 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9E3BC9; Sun, 29 Oct 2023 01:00:56 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R881e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045176;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0Vv31XWv_1698566451; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0Vv31XWv_1698566451) by smtp.aliyun-inc.com; Sun, 29 Oct 2023 16:00:52 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v1 1/2] dmaengine: idxd: Protect int_handle field in hw descriptor Date: Sun, 29 Oct 2023 16:00:48 +0800 Message-Id: <20231029080049.1482701-2-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231029080049.1482701-1-guanjun@linux.alibaba.com> References: <20231029080049.1482701-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guanjun The int_handle field in hw descriptor should also be protected by wmb() before possibly triggering a DMA read. Signed-off-by: Guanjun Reviewed-by: Dave Jiang Reviewed-by: Fenghua Yu --- drivers/dma/idxd/submit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c index c01db23e3333..3f922518e3a5 100644 --- a/drivers/dma/idxd/submit.c +++ b/drivers/dma/idxd/submit.c @@ -182,13 +182,6 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_d= esc *desc) =20 portal =3D idxd_wq_portal_addr(wq); =20 - /* - * The wmb() flushes writes to coherent DMA data before - * possibly triggering a DMA read. The wmb() is necessary - * even on UP because the recipient is a device. - */ - wmb(); - /* * Pending the descriptor to the lockless list for the irq_entry * that we designated the descriptor to. @@ -199,6 +192,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_d= esc *desc) llist_add(&desc->llnode, &ie->pending_llist); } =20 + /* + * The wmb() flushes writes to coherent DMA data before + * possibly triggering a DMA read. The wmb() is necessary + * even on UP because the recipient is a device. + */ + wmb(); + if (wq_dedicated(wq)) { iosubmit_cmds512(portal, desc->hw, 1); } else { --=20 2.39.3 From nobody Tue Dec 16 21:51:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCB2BC4167D for ; Sun, 29 Oct 2023 08:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230090AbjJ2IBK (ORCPT ); Sun, 29 Oct 2023 04:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbjJ2IBC (ORCPT ); Sun, 29 Oct 2023 04:01:02 -0400 Received: from out30-130.freemail.mail.aliyun.com (out30-130.freemail.mail.aliyun.com [115.124.30.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A772F3; Sun, 29 Oct 2023 01:00:58 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R121e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0Vv31XX4_1698566453; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0Vv31XX4_1698566453) by smtp.aliyun-inc.com; Sun, 29 Oct 2023 16:00:53 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de Subject: [PATCH v1 2/2] dmaengine: idxd: Fix the incorrect descriptions Date: Sun, 29 Oct 2023 16:00:49 +0800 Message-Id: <20231029080049.1482701-3-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231029080049.1482701-1-guanjun@linux.alibaba.com> References: <20231029080049.1482701-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guanjun Fix the incorrect descriptions for the GRPCFG register. No functional changes Signed-off-by: Guanjun Reviewed-by: Dave Jiang --- drivers/dma/idxd/registers.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..385a162a55f2 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,15 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to acc= ess. + * The GRPCFG register block is divided into three different types, that + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group + * allows us to move to the register group that's for that particular wq, + * engine or group flag. + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number + * of register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) --=20 2.39.3