From nobody Thu Dec 18 12:17:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC3ACC4167B for ; Sat, 28 Oct 2023 23:14:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbjJ1XOD (ORCPT ); Sat, 28 Oct 2023 19:14:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229907AbjJ1XNu (ORCPT ); Sat, 28 Oct 2023 19:13:50 -0400 Received: from mail-oo1-xc31.google.com (mail-oo1-xc31.google.com [IPv6:2607:f8b0:4864:20::c31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57BAECF for ; Sat, 28 Oct 2023 16:13:48 -0700 (PDT) Received: by mail-oo1-xc31.google.com with SMTP id 006d021491bc7-5842ea6f4d5so2056534eaf.2 for ; Sat, 28 Oct 2023 16:13:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698534827; x=1699139627; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=56YUmquglDtdI2AgsFp8Dfqen0eRNcOUaE781b7rud8=; b=ltVGMWN501Ht3FyBhCMSAqOhTivfwTdhkwxCzbmDH56Uw4Wu9iSpbYjdgTnTyalDrh 4hLbUQOqIyiM3ffGlkR6nHhxy4y7KNqaFEX96gaoV5GliS2T2CPJGYdaqqotWD2tbptT /Aq9ofZi1dhTGuq42OVU8sExodm3w9xVfwtFFpmaFUOU59wx+uuEoBtCC7v+1Hw9wuF7 s6svYum0TR5sC3ESGxkUb0WEBbzP3o6jsxJdGCNiT4MNDbEEU3Yp/C6KRLLqbdrgOG0i M2xHGfAvMVhqNoEOPuPQoIgfArpnwGKXr0ChZc09GWA/rVmHR5EXGFpSP2hE/jemWYGj w/4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698534827; x=1699139627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=56YUmquglDtdI2AgsFp8Dfqen0eRNcOUaE781b7rud8=; b=pnxOXzXx7DQ45p2PZrmATTIP1qdXT+5kcY6R16b7NIA80mHkOQdTm10nhkOXAo+abP h6gEy+PWuBC7IVlTN98tk1WbbuQ5barXGsQudJOqmSchwua8nCd+9RljDDXzOsAlPf0C y2uxQT3v9vkPgoQ73gJfph4qCpCKqN6wwG42yFOSYE7xV0f+gXHp4h+UNm8stRaesWSu fLzDdrPASNmTHHYjPSjsZT1CDtw8Ir+o8qGCbHE6o0oFMBZyX1qJVtsZs5dFmQFKDEsF clTPh81bOKe+k1HOKqI0MrrGcWBL2ChbAHeT9ziixrkN8fYgJj4kAlsP7aKS5I9d/1tY JiRQ== X-Gm-Message-State: AOJu0YxoPnM+sMcDPEhIoZJbJaFLyx3g7FLXORRP8ClsbFUmSTHX7ZwZ RrOs03z/uw8REkcuLpFxhlByoA== X-Google-Smtp-Source: AGHT+IGq5Mcxzf3tN07mJTIgv1Wxotaz2Uaine2ZZiRfV+MdLhpoDUKwMV8rRW6x4wnAP4zHnD4SGA== X-Received: by 2002:a05:6358:903:b0:168:dc03:5b90 with SMTP id r3-20020a056358090300b00168dc035b90mr9086199rwi.23.1698534827455; Sat, 28 Oct 2023 16:13:47 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id u17-20020a17090341d100b001b8622c1ad2sm3679345ple.130.2023.10.28.16.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 16:13:46 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , Alexandre Ghiti , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Andrew Jones , Lad Prabhakar , Samuel Holland Subject: [PATCH v2 04/11] riscv: Improve flush_tlb_kernel_range() Date: Sat, 28 Oct 2023 16:12:02 -0700 Message-ID: <20231028231339.3116618-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231028231339.3116618-1-samuel.holland@sifive.com> References: <20231028231339.3116618-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Ghiti This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Tested-by: Lad Prabhakar # On RZ/= Five SMARC [Samuel: Use cpu_online_mask and merge if statements] Signed-off-by: Samuel Holland --- Changes in v2: - Rebase on Alexandre's "riscv: tlb flush improvements" series v5 arch/riscv/include/asm/tlbflush.h | 11 +++++----- arch/riscv/mm/tlbflush.c | 34 ++++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlb= flush.h index 170a49c531c6..8f3418c5f172 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -40,6 +40,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned lo= ng start, void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +void flush_tlb_kernel_range(unsigned long start, unsigned long end); #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -56,15 +57,15 @@ static inline void flush_tlb_range(struct vm_area_struc= t *vma, local_flush_tlb_all(); } =20 -#define flush_tlb_mm(mm) flush_tlb_all() -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() -#endif /* !CONFIG_SMP || !CONFIG_MMU */ - /* Flush a range of kernel pages */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - flush_tlb_all(); + local_flush_tlb_all(); } =20 +#define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() +#endif /* !CONFIG_SMP || !CONFIG_MMU */ + #endif /* _ASM_RISCV_TLBFLUSH_H */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index e46fefc70927..e6659d7368b3 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -97,20 +97,27 @@ static void __flush_tlb_range(struct mm_struct *mm, uns= igned long start, unsigned long size, unsigned long stride) { struct flush_tlb_range_data ftd; - struct cpumask *cmask =3D mm_cpumask(mm); + const struct cpumask *cmask; unsigned long asid =3D FLUSH_TLB_NO_ASID; - unsigned int cpuid; bool broadcast; =20 - if (cpumask_empty(cmask)) - return; + if (mm) { + unsigned int cpuid; + + cmask =3D mm_cpumask(mm); + if (cpumask_empty(cmask)) + return; =20 - cpuid =3D get_cpu(); - /* check if the tlbflush needs to be sent to other CPUs */ - broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + cpuid =3D get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; =20 - if (static_branch_unlikely(&use_asid_allocator)) - asid =3D atomic_long_read(&mm->context.id) & asid_mask; + if (static_branch_unlikely(&use_asid_allocator)) + asid =3D atomic_long_read(&mm->context.id) & asid_mask; + } else { + cmask =3D cpu_online_mask; + broadcast =3D true; + } =20 if (broadcast) { if (riscv_use_ipi_for_rfence()) { @@ -128,7 +135,8 @@ static void __flush_tlb_range(struct mm_struct *mm, uns= igned long start, local_flush_tlb_range_asid(start, size, stride, asid); } =20 - put_cpu(); + if (mm) + put_cpu(); } =20 void flush_tlb_mm(struct mm_struct *mm) @@ -179,6 +187,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsig= ned long start, =20 __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); } + +void flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + __flush_tlb_range(NULL, start, end - start, PAGE_SIZE); +} + #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) --=20 2.42.0