From nobody Wed Dec 17 11:32:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9954BC25B48 for ; Thu, 26 Oct 2023 08:39:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230283AbjJZIju (ORCPT ); Thu, 26 Oct 2023 04:39:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229642AbjJZIjs (ORCPT ); Thu, 26 Oct 2023 04:39:48 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCB77129 for ; Thu, 26 Oct 2023 01:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1698309541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=4hmV/EFlvcbIT7jtmv0BQdZphzQ0SPFV6htEyJkBU3k=; b=Se9CU5K+YjlGS/y4Gu76di2/RFDAbSltUXqcIRzo4kUAHh6X2n9poyXebKNCSK0DvUTu5G AWLQHXluVzk37ajrGOHSqffD3tRe8exzlq7CDdGCojWYMQqd114doxiEFj2mx+cGGgC2Ew 9zhM36Pl+VbBJ2cLSIdNBVLFrp0kKZs= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-364-ShnXCKhYNSa7jwU_ETqM7w-1; Thu, 26 Oct 2023 04:38:55 -0400 X-MC-Unique: ShnXCKhYNSa7jwU_ETqM7w-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 32EFB811E88; Thu, 26 Oct 2023 08:38:55 +0000 (UTC) Received: from p1.luc.cera.cz (unknown [10.45.225.62]) by smtp.corp.redhat.com (Postfix) with ESMTP id 748D75027; Thu, 26 Oct 2023 08:38:53 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Jesse Brandeburg , Tony Nguyen , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , intel-wired-lan@lists.osuosl.org, linux-kernel@vger.kernel.org, Jacob Keller , Wojciech Drewek Subject: [PATCH iwl-next] i40e: Remove queue tracking fields from i40e_adminq_ring Date: Thu, 26 Oct 2023 10:38:52 +0200 Message-ID: <20231026083852.2623216-1-ivecera@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fields 'head', 'tail', 'len', 'bah' and 'bal' in i40e_adminq_ring are used to store register offsets. These offsets are initialized and remains constant so there is no need to store them in the i40e_adminq_ring structure. Remove these fields from i40e_adminq_ring and use register offset constants instead. Remove i40e_adminq_init_regs() that originally stores these constants into these fields. Finally improve i40e_check_asq_alive() that assumes that non-zero value of hw->aq.asq.len indicates fully initialized AdminQ send queue. Replace it by check for non-zero value of field hw->aq.asq.count that is non-zero when the sending queue is initialized and is zeroed during shutdown of the queue. Signed-off-by: Ivan Vecera Reviewed-by: Przemek Kitszel Reviewed-by: Wojciech Drewek Tested-by: Pucha Himasekhar Reddy (A Co= ntingent worker at Intel) --- drivers/net/ethernet/intel/i40e/i40e_adminq.c | 86 +++++++------------ drivers/net/ethernet/intel/i40e/i40e_adminq.h | 7 -- drivers/net/ethernet/intel/i40e/i40e_common.c | 8 +- drivers/net/ethernet/intel/i40e/i40e_main.c | 8 +- 4 files changed, 39 insertions(+), 70 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/et= hernet/intel/i40e/i40e_adminq.c index 896c43905309..f73f5930fc58 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c +++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c @@ -8,27 +8,6 @@ =20 static void i40e_resume_aq(struct i40e_hw *hw); =20 -/** - * i40e_adminq_init_regs - Initialize AdminQ registers - * @hw: pointer to the hardware structure - * - * This assumes the alloc_asq and alloc_arq functions have already been c= alled - **/ -static void i40e_adminq_init_regs(struct i40e_hw *hw) -{ - /* set head and tail registers in our local struct */ - hw->aq.asq.tail =3D I40E_PF_ATQT; - hw->aq.asq.head =3D I40E_PF_ATQH; - hw->aq.asq.len =3D I40E_PF_ATQLEN; - hw->aq.asq.bal =3D I40E_PF_ATQBAL; - hw->aq.asq.bah =3D I40E_PF_ATQBAH; - hw->aq.arq.tail =3D I40E_PF_ARQT; - hw->aq.arq.head =3D I40E_PF_ARQH; - hw->aq.arq.len =3D I40E_PF_ARQLEN; - hw->aq.arq.bal =3D I40E_PF_ARQBAL; - hw->aq.arq.bah =3D I40E_PF_ARQBAH; -} - /** * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings * @hw: pointer to the hardware structure @@ -254,17 +233,17 @@ static int i40e_config_asq_regs(struct i40e_hw *hw) u32 reg =3D 0; =20 /* Clear Head and Tail */ - wr32(hw, hw->aq.asq.head, 0); - wr32(hw, hw->aq.asq.tail, 0); + wr32(hw, I40E_PF_ATQH, 0); + wr32(hw, I40E_PF_ATQT, 0); =20 /* set starting point */ - wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | + wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK)); - wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); - wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.desc_buf.pa)); =20 /* Check one register to verify that config was applied */ - reg =3D rd32(hw, hw->aq.asq.bal); + reg =3D rd32(hw, I40E_PF_ATQBAL); if (reg !=3D lower_32_bits(hw->aq.asq.desc_buf.pa)) ret_code =3D -EIO; =20 @@ -283,20 +262,20 @@ static int i40e_config_arq_regs(struct i40e_hw *hw) u32 reg =3D 0; =20 /* Clear Head and Tail */ - wr32(hw, hw->aq.arq.head, 0); - wr32(hw, hw->aq.arq.tail, 0); + wr32(hw, I40E_PF_ARQH, 0); + wr32(hw, I40E_PF_ARQT, 0); =20 /* set starting point */ - wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | + wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | I40E_PF_ARQLEN_ARQENABLE_MASK)); - wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); - wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.desc_buf.pa)); =20 /* Update tail in the HW to post pre-allocated buffers */ - wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); + wr32(hw, I40E_PF_ARQT, hw->aq.num_arq_entries - 1); =20 /* Check one register to verify that config was applied */ - reg =3D rd32(hw, hw->aq.arq.bal); + reg =3D rd32(hw, I40E_PF_ARQBAL); if (reg !=3D lower_32_bits(hw->aq.arq.desc_buf.pa)) ret_code =3D -EIO; =20 @@ -439,11 +418,11 @@ static int i40e_shutdown_asq(struct i40e_hw *hw) } =20 /* Stop firmware AdminQ processing */ - wr32(hw, hw->aq.asq.head, 0); - wr32(hw, hw->aq.asq.tail, 0); - wr32(hw, hw->aq.asq.len, 0); - wr32(hw, hw->aq.asq.bal, 0); - wr32(hw, hw->aq.asq.bah, 0); + wr32(hw, I40E_PF_ATQH, 0); + wr32(hw, I40E_PF_ATQT, 0); + wr32(hw, I40E_PF_ATQLEN, 0); + wr32(hw, I40E_PF_ATQBAL, 0); + wr32(hw, I40E_PF_ATQBAH, 0); =20 hw->aq.asq.count =3D 0; /* to indicate uninitialized queue */ =20 @@ -473,11 +452,11 @@ static int i40e_shutdown_arq(struct i40e_hw *hw) } =20 /* Stop firmware AdminQ processing */ - wr32(hw, hw->aq.arq.head, 0); - wr32(hw, hw->aq.arq.tail, 0); - wr32(hw, hw->aq.arq.len, 0); - wr32(hw, hw->aq.arq.bal, 0); - wr32(hw, hw->aq.arq.bah, 0); + wr32(hw, I40E_PF_ARQH, 0); + wr32(hw, I40E_PF_ARQT, 0); + wr32(hw, I40E_PF_ARQLEN, 0); + wr32(hw, I40E_PF_ARQBAL, 0); + wr32(hw, I40E_PF_ARQBAH, 0); =20 hw->aq.arq.count =3D 0; /* to indicate uninitialized queue */ =20 @@ -608,9 +587,6 @@ int i40e_init_adminq(struct i40e_hw *hw) goto init_adminq_exit; } =20 - /* Set up register offsets */ - i40e_adminq_init_regs(hw); - /* setup ASQ command write back timeout */ hw->aq.asq_cmd_timeout =3D I40E_ASQ_CMD_TIMEOUT; =20 @@ -720,9 +696,9 @@ static u16 i40e_clean_asq(struct i40e_hw *hw) =20 desc =3D I40E_ADMINQ_DESC(*asq, ntc); details =3D I40E_ADMINQ_DETAILS(*asq, ntc); - while (rd32(hw, hw->aq.asq.head) !=3D ntc) { + while (rd32(hw, I40E_PF_ATQH) !=3D ntc) { i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, - "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); + "ntc %d head %d.\n", ntc, rd32(hw, I40E_PF_ATQH)); =20 if (details->callback) { I40E_ADMINQ_CALLBACK cb_func =3D @@ -756,7 +732,7 @@ static bool i40e_asq_done(struct i40e_hw *hw) /* AQ designers suggest use of head for better * timing reliability than DD bit */ - return rd32(hw, hw->aq.asq.head) =3D=3D hw->aq.asq.next_to_use; + return rd32(hw, I40E_PF_ATQH) =3D=3D hw->aq.asq.next_to_use; =20 } =20 @@ -797,7 +773,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, =20 hw->aq.asq_last_status =3D I40E_AQ_RC_OK; =20 - val =3D rd32(hw, hw->aq.asq.head); + val =3D rd32(hw, I40E_PF_ATQH); if (val >=3D hw->aq.num_asq_entries) { i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: head overrun at %d\n", val); @@ -889,7 +865,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, if (hw->aq.asq.next_to_use =3D=3D hw->aq.asq.count) hw->aq.asq.next_to_use =3D 0; if (!details->postpone) - wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); + wr32(hw, I40E_PF_ATQT, hw->aq.asq.next_to_use); =20 /* if cmd_details are not defined or async flag is not set, * we need to wait for desc write back @@ -949,7 +925,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, /* update the error if time out occurred */ if ((!cmd_completed) && (!details->async && !details->postpone)) { - if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { + if (rd32(hw, I40E_PF_ATQLEN) & I40E_GL_ATQLEN_ATQCRIT_MASK) { i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: AQ Critical error.\n"); status =3D -EIO; @@ -1103,7 +1079,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw, } =20 /* set next_to_use to head */ - ntu =3D rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; + ntu =3D rd32(hw, I40E_PF_ARQH) & I40E_PF_ARQH_ARQH_MASK; if (ntu =3D=3D ntc) { /* nothing to do - shouldn't need to update ring's values */ ret_code =3D -EALREADY; @@ -1151,7 +1127,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw, desc->params.external.addr_low =3D cpu_to_le32(lower_32_bits(bi->pa)); =20 /* set tail =3D the last cleaned desc index. */ - wr32(hw, hw->aq.arq.tail, ntc); + wr32(hw, I40E_PF_ARQT, ntc); /* ntc is updated to tail + 1 */ ntc++; if (ntc =3D=3D hw->aq.num_arq_entries) diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.h b/drivers/net/et= hernet/intel/i40e/i40e_adminq.h index 80125bea80a2..ee86d2c53079 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_adminq.h +++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.h @@ -29,13 +29,6 @@ struct i40e_adminq_ring { /* used for interrupt processing */ u16 next_to_use; u16 next_to_clean; - - /* used for queue tracking */ - u32 head; - u32 tail; - u32 len; - u32 bah; - u32 bal; }; =20 /* ASQ transaction details */ diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/et= hernet/intel/i40e/i40e_common.c index e171f4814e21..bd52b73cf61f 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c @@ -195,11 +195,11 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debu= g_mask mask, void *desc, **/ bool i40e_check_asq_alive(struct i40e_hw *hw) { - if (hw->aq.asq.len) - return !!(rd32(hw, hw->aq.asq.len) & - I40E_PF_ATQLEN_ATQENABLE_MASK); - else + /* Check if the queue is initialized */ + if (!hw->aq.asq.count) return false; + + return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK); } =20 /** diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethe= rnet/intel/i40e/i40e_main.c index 69dafdecb243..91563512b2bd 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -10141,7 +10141,7 @@ static void i40e_clean_adminq_subtask(struct i40e_p= f *pf) return; =20 /* check for error indications */ - val =3D rd32(&pf->hw, pf->hw.aq.arq.len); + val =3D rd32(&pf->hw, I40E_PF_ARQLEN); i40e_trace(state_arq, pf, val); oldval =3D val; if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { @@ -10161,9 +10161,9 @@ static void i40e_clean_adminq_subtask(struct i40e_p= f *pf) val &=3D ~I40E_PF_ARQLEN_ARQCRIT_MASK; } if (oldval !=3D val) - wr32(&pf->hw, pf->hw.aq.arq.len, val); + wr32(&pf->hw, I40E_PF_ARQLEN, val); =20 - val =3D rd32(&pf->hw, pf->hw.aq.asq.len); + val =3D rd32(&pf->hw, I40E_PF_ATQLEN); i40e_trace(state_asq, pf, val); oldval =3D val; if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { @@ -10182,7 +10182,7 @@ static void i40e_clean_adminq_subtask(struct i40e_p= f *pf) val &=3D ~I40E_PF_ATQLEN_ATQCRIT_MASK; } if (oldval !=3D val) - wr32(&pf->hw, pf->hw.aq.asq.len, val); + wr32(&pf->hw, I40E_PF_ATQLEN, val); =20 event.buf_len =3D I40E_MAX_AQ_BUF_SIZE; event.msg_buf =3D kzalloc(event.buf_len, GFP_KERNEL); --=20 2.41.0