From nobody Wed Dec 17 11:30:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55229C25B6B for ; Thu, 26 Oct 2023 12:47:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229647AbjJZMra (ORCPT ); Thu, 26 Oct 2023 08:47:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbjJZMrN (ORCPT ); Thu, 26 Oct 2023 08:47:13 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8A92170B; Thu, 26 Oct 2023 05:47:02 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 906F6C433C9; Thu, 26 Oct 2023 12:46:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324422; bh=A70TzKLxYRaHLeYspVh0azJqD+i/OcfkNzjW58SbjyM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kZ70SXmQxP1spA+aWMsD7rQcICfRpZhnJBLX5IYBI9lzr7OaAvtYqzzOkMX/pBG95 epobNsV3+QMHVifXPgK1zLT3De7/KX9LkMGe5T+iGIYKjV4ZlZoymG5iS76N7ZmLX+ acG+KRQVT4Zy6MFQ5FnL9niLAUgTCOBPOX8wLCXEvQtWieO6LjNOK50ysDSrii19Jj kTpZOogP2zILMiBUrEh1R/GgiqWCBUCOYmMjlxMIDAD5ucaWYHTCbtcwUnewV7u5R1 bSEjmQPBo7xZJq0zrxBYDFa2CNH3LrdmldKLkxU4qy4rO4D+4DrrOY4leML1cR3YGD 6mFh3jwqoLynQ== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:23 +0100 Subject: [PATCH 09/21] arm64/cpufeature: Hook new identification registers up to cpufeature MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231026-arm64-2023-dpisa-v1-9-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=7897; i=broonie@kernel.org; h=from:subject:message-id; bh=A70TzKLxYRaHLeYspVh0azJqD+i/OcfkNzjW58SbjyM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+bOBPImzncrwOiJOMmRrPjsUx4R3OuZK4fkWNw RZPFvHuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmwAKCRAk1otyXVSH0IBNB/ 9RsKTxUkLn4gA8r+7NVYEZwuH8kSlA+ENtpVXHHcWz/tY7tu/CzGM06prol7B0wBIK63tT44AczUde hWw6+HAmuCgbv1gApzeASsb9rEyHAGbwhFiNYkR5wAffLwDnUcPbzOJr8nZ2PYd/Ntjhe1gf6re/DP sagT2nV8rk8ubphl0jUUcu+ZecO+eVgS36kgIGTr8rYS4v8tE9szfqjiBHW2tcVVIGpdYxZS+TkJFl pgBRM3PjRLSYpwPs6ae1advdq6X49I6dFPqHfGLnZO3s+uhif9djahiR2U421RP+To0GiqPXjXbbjA 2GIji7GGMBJ4606tuDhLmYEVkb4ueg X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 2023 architecture extensions have defined several new ID registers, hook them up to the cpufeature code so we can add feature checks and hwcaps based on their contents. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpu.h | 3 +++ arch/arm64/kernel/cpufeature.c | 28 ++++++++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 3 +++ 3 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index e749838b9c5d..60db584ded55 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -53,14 +53,17 @@ struct cpuinfo_arm64 { u64 reg_id_aa64isar0; u64 reg_id_aa64isar1; u64 reg_id_aa64isar2; + u64 reg_id_aa64isar3; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; u64 reg_id_aa64mmfr2; u64 reg_id_aa64mmfr3; u64 reg_id_aa64pfr0; u64 reg_id_aa64pfr1; + u64 reg_id_aa64pfr2; u64 reg_id_aa64zfr0; u64 reg_id_aa64smfr0; + u64 reg_id_aa64fpfr0; =20 struct cpuinfo_32bit aarch32; =20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e638..c1658d893e0e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -234,6 +234,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64isar3[] =3D { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1= _CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1= _CSV2_SHIFT, 4, 0), @@ -267,6 +271,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64pfr2[] =3D { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] =3D { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), @@ -317,6 +325,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] =3D { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_= ECV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_F= GT_SHIFT, 4, 0), @@ -712,10 +724,12 @@ static const struct __ftr_reg_entry { &id_aa64pfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, &id_aa64pfr1_override), + ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, &id_aa64zfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, &id_aa64smfr0_override), + ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), @@ -727,6 +741,7 @@ static const struct __ftr_reg_entry { &id_aa64isar1_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, &id_aa64isar2_override), + ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -1026,14 +1041,17 @@ void __init init_cpu_features(struct cpuinfo_arm64 = *info) init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); + init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); + init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); + init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); =20 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) init_32bit_cpu_features(&info->aarch32); @@ -1263,6 +1281,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64isar1, boot->reg_id_aa64isar1); taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, info->reg_id_aa64isar2, boot->reg_id_aa64isar2); + taint |=3D check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, + info->reg_id_aa64isar3, boot->reg_id_aa64isar3); =20 /* * Differing PARange support is fine as long as all peripherals and @@ -1282,6 +1302,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); + taint |=3D check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, + info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); =20 taint |=3D check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); @@ -1289,6 +1311,9 @@ void update_cpu_features(int cpu, taint |=3D check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); =20 + taint |=3D check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, + info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); + if (IS_ENABLED(CONFIG_ARM64_SVE) && id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { info->reg_zcr =3D read_zcr_features(); @@ -1399,8 +1424,10 @@ u64 __read_sysreg_by_encoding(u32 sys_id) =20 read_sysreg_case(SYS_ID_AA64PFR0_EL1); read_sysreg_case(SYS_ID_AA64PFR1_EL1); + read_sysreg_case(SYS_ID_AA64PFR2_EL1); read_sysreg_case(SYS_ID_AA64ZFR0_EL1); read_sysreg_case(SYS_ID_AA64SMFR0_EL1); + read_sysreg_case(SYS_ID_AA64FPFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR1_EL1); read_sysreg_case(SYS_ID_AA64MMFR0_EL1); @@ -1410,6 +1437,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64ISAR0_EL1); read_sysreg_case(SYS_ID_AA64ISAR1_EL1); read_sysreg_case(SYS_ID_AA64ISAR2_EL1); + read_sysreg_case(SYS_ID_AA64ISAR3_EL1); =20 read_sysreg_case(SYS_CNTFRQ_EL0); read_sysreg_case(SYS_CTR_EL0); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 98fda8500535..e153c6d2b3fd 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -445,14 +445,17 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 = *info) info->reg_id_aa64isar0 =3D read_cpuid(ID_AA64ISAR0_EL1); info->reg_id_aa64isar1 =3D read_cpuid(ID_AA64ISAR1_EL1); info->reg_id_aa64isar2 =3D read_cpuid(ID_AA64ISAR2_EL1); + info->reg_id_aa64isar3 =3D read_cpuid(ID_AA64ISAR3_EL1); info->reg_id_aa64mmfr0 =3D read_cpuid(ID_AA64MMFR0_EL1); info->reg_id_aa64mmfr1 =3D read_cpuid(ID_AA64MMFR1_EL1); info->reg_id_aa64mmfr2 =3D read_cpuid(ID_AA64MMFR2_EL1); info->reg_id_aa64mmfr3 =3D read_cpuid(ID_AA64MMFR3_EL1); info->reg_id_aa64pfr0 =3D read_cpuid(ID_AA64PFR0_EL1); info->reg_id_aa64pfr1 =3D read_cpuid(ID_AA64PFR1_EL1); + info->reg_id_aa64pfr2 =3D read_cpuid(ID_AA64PFR2_EL1); info->reg_id_aa64zfr0 =3D read_cpuid(ID_AA64ZFR0_EL1); info->reg_id_aa64smfr0 =3D read_cpuid(ID_AA64SMFR0_EL1); + info->reg_id_aa64fpfr0 =3D read_cpuid(ID_AA64FPFR0_EL1); =20 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) info->reg_gmid =3D read_cpuid(GMID_EL1); --=20 2.30.2