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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 01/21] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Thu, 26 Oct 2023 01:53:24 +0530 Message-Id: <20231025202344.581132-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, move these functions to common location. Signed-off-by: Sunil V L Acked-by: Bjorn Helgaas Acked-by: Catalin Marinas --- arch/arm64/kernel/pci.c | 191 ---------------------------------------- drivers/pci/pci-acpi.c | 182 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 191 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index f872c57e9909..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,28 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ =20 -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif =20 /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -61,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); =20 #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg =3D bus->sysdata; - struct acpi_device *adev =3D to_acpi_device(cfg->parent); - struct acpi_pci_root *root =3D acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg =3D bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev =3D NULL; - else - adev =3D to_acpi_device(cfg->parent); - - bus_dev =3D &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status =3D acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev =3D &root->device->dev; - struct resource *bus_res =3D &root->secondary; - u16 seg =3D root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev =3D acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg =3D pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info =3D pci_acpi_generic_release_info; - root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; - root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host =3D pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index a05350a4e49c..58497b25d2ab 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1518,3 +1519,184 @@ static int __init acpi_pci_init(void) return 0; } arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) + +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg =3D bus->sysdata; + struct acpi_device *adev =3D to_acpi_device(cfg->parent); + struct acpi_pci_root *root =3D acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg =3D bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev =3D NULL; + else + adev =3D to_acpi_device(cfg->parent); + + bus_dev =3D &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status =3D acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev =3D &root->device->dev; + struct resource *bus_res =3D &root->secondary; + u16 seg =3D root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret =3D pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev =3D acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg =3D pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri =3D container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri =3D kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops =3D kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg =3D pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info =3D pci_acpi_generic_release_info; + root_ops->prepare_resources =3D pci_acpi_root_prepare_resources; + root_ops->pci_ops =3D (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus =3D acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host =3D pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +#endif --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F09B3C25B6E for ; Wed, 25 Oct 2023 20:24:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234757AbjJYUYc (ORCPT ); Wed, 25 Oct 2023 16:24:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233221AbjJYUYW (ORCPT ); Wed, 25 Oct 2023 16:24:22 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5B35191 for ; Wed, 25 Oct 2023 13:24:20 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6bee11456baso134839b3a.1 for ; Wed, 25 Oct 2023 13:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265460; x=1698870260; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=il/rbbBih8ETNOL/0gi7mQnwMr9PQruIC4HVqlbsTs0=; b=cpHqw6Ko3XBXaXjWZ2O0xRulHJ+115MQRPzNMFsfrt14xH96seITodu0Y+SWsiWCST 6pWhR+UxbgdBdR/SOzQK8vOATWnQNus0CEKcmfVGjM7OxS6eUc0z89y9fk6cvTTkd1Tn K7V1x8mXwsramj8XqH18q1J7VNYAtiXbZyuUmYXDQaQqGCay9MNIosNf7VHAQvKxNa0H 4JN0iJKu/M1CM4BSURbHiCnxs4wbvNeNy2gikGl8PNMtUTh5tdCtEqYGKp/O8Nimm/7A T2SGIeS8++loU1mgwGUdu+A8eGtwf+zITm7nOeYPxn5Oyhhyzaf09opZ+ry0h+t3rumK uVag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265460; x=1698870260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=il/rbbBih8ETNOL/0gi7mQnwMr9PQruIC4HVqlbsTs0=; b=hwrK3KueteIQb1SMpN/2/kbS06eEfxXubi7xtwKguG5t/qUeQdVy8br2NTun2tjCq4 Tw5hsU6xU3tgQlSiCxr9t6XKaWFE2rc1xFpRyjL9H2yZVxL3qtx1ihFuj/VWcpE2w4ft KaE35M5IoJO5sPESkgBZGNXiiehd+twLvM3UifSrXiB0m3v4p88A10zBSLgMiBB1uFUl BxNgzOZxMHCi/RomXS5ds3mE27eyhMYEGX0XWPYwj3zihv8vNtLguejr08oaWG6uLxRN Llt+P2EVGMNYjEezvlRAsqx0FjamynTnkuXiZLSSD04mirAhFlnBahj5n4FyD6uAsjEd G9GA== X-Gm-Message-State: AOJu0Yy2c0YZftoiJvY1i9f4t8s6Tusidub7lZSxAt1nL1KTEBEtu3cn 3/SZapdEANeW9enN2rvZxMOVDw== X-Google-Smtp-Source: AGHT+IHAnCPM/Z122/pk/4UjZRlnQX59HcM6kQVsLk17lGf/hhEOulm69KFX9/lCmDwSpdfrn7JfVw== X-Received: by 2002:a05:6a00:9392:b0:693:4143:5145 with SMTP id ka18-20020a056a00939200b0069341435145mr15121152pfb.31.1698265460080; Wed, 25 Oct 2023 13:24:20 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:19 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 02/21] RISC-V: ACPI: Implement PCI related functionality Date: Thu, 26 Oct 2023 01:53:25 +0530 Message-Id: <20231025202344.581132-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ arch/riscv/kernel/acpi.c | 31 ++++++++++++++----------------- drivers/pci/pci-acpi.c | 2 +- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c3c3f3562082..8c105a151e12 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION @@ -152,6 +153,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..41aa77c8484b 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address p= hys, acpi_size size) #ifdef CONFIG_PCI =20 /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; -} + struct pci_bus *b =3D pci_find_bus(domain, bus); =20 -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devf= n, - int reg, int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->read(b, devfn, reg, len, val); } =20 -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return -1; -} + struct pci_bus *b =3D pci_find_bus(domain, bus); =20 -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - return NULL; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->write(b, devfn, reg, len, val); } + #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 58497b25d2ab..c8c3369fd69f 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1520,7 +1520,7 @@ static int __init acpi_pci_init(void) } arch_initcall(acpi_pci_init); =20 -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) =20 /* * Try to assign the IRQ number when probing a new device --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BAF6C25B6E for ; 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Wed, 25 Oct 2023 13:24:25 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:25 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 03/21] ACPI: Kconfig: Introduce new option to support deferred GSI probe Date: Thu, 26 Oct 2023 01:53:26 +0530 Message-Id: <20231025202344.581132-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On some architectures like RISC-V, the interrupt controllers for Global System Interrupts (GSI) are not probed early during boot. So, the device drivers which need to register their GSI, need to be deferred until the actual interrupt controller driver is probed. To reduce the impact of such change, add a new CONFIG option which can be set only by the architecture which needs deferred GSI probing. Signed-off-by: Sunil V L --- drivers/acpi/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index cee82b473dc5..4399e793f1d2 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -51,6 +51,9 @@ config ARCH_MIGHT_HAVE_ACPI_PDC config ACPI_GENERIC_GSI bool =20 +config ARCH_ACPI_DEFERRED_GSI + bool + config ACPI_SYSTEM_POWER_STATES_SUPPORT bool =20 --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 843D5C07545 for ; Wed, 25 Oct 2023 20:24:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234949AbjJYUYq (ORCPT ); Wed, 25 Oct 2023 16:24:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234863AbjJYUYe (ORCPT ); Wed, 25 Oct 2023 16:24:34 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445D818D for ; Wed, 25 Oct 2023 13:24:32 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6b5e6301a19so144286b3a.0 for ; Wed, 25 Oct 2023 13:24:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265472; x=1698870272; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6XsFHpyMSXpsQo/vHxUfuExbd7P0HKVdbzIKlbRfdpg=; b=IFtzf0U28RD+GSQFbYyzqFLKa6bFdIIzW112ahFh3jc6XjWupq1EfHGncUr3/acJN2 xKkmXVXxG7yatZXJkIhLGItwrgVD0Shu6ZTXXUD3qqhwkOdQUdlLTtpvF94vrXozoQ// 7vYVru2vVcy5/m8p39WgVLXSfjDQTxXvsOry+mE87DCmz6tmOiX2VGR6bUCogS+y03ht aDoqwfgMZbvOU9gvHx6lvPJie+sezYV/17tHuqIsG3LsWt1nW3LjOC1fi2ZJGbIytPdX Nf49mk5iCdvFgyh9zAOJEnJxrAbxkpp8H3h/bPzVJ1EM9s+nVXXbBH8rkanHNFu/0ibM he6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265472; x=1698870272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6XsFHpyMSXpsQo/vHxUfuExbd7P0HKVdbzIKlbRfdpg=; b=GtfR46GqqZepzR6aTAWWvC9KITGdO740yqFct+9O/uDRVXK34kh5LxVaJ6S+VSmxv6 beZsL1xNqglOTJkcEzQ0G7swE1AI0TtDgVzrFe0NmsZOIKXiPMRDXty3sOoY1R/irfAQ mjVF3YwvSatm5kavE++R/4jm4N8eICUeVB5KuWPagnGQFQEs6NJKKTxFYUXHOJCwZdHk U0YuGqSBhkZ3JRP3+UqSB/ku2W0Gt3AB1CjMga4mgqr685UCCsB0RAMi3YhTj7wSu54J mjwG+X/FZqwkb77iSVgFTHmjs2rOOueZ81Hb235xH+o+tRdh8hVsHAf8Ikbp+RATHz/w PsVA== X-Gm-Message-State: AOJu0Yxpryu3QZH5sGM14LLJ9mxtu75R53QNj2zg6cIZZ1Vp00muMhZR pz6cfuHyHiY7VXeMmac2qs4azg== X-Google-Smtp-Source: AGHT+IG17/2PVfDmNtmjstcH9/wp6PkDje8IYgLOfv4MBT6NCYwfFeoyShSprXc6RSlzfPVHtacKoA== X-Received: by 2002:a05:6a00:2d86:b0:68a:59c6:c0a6 with SMTP id fb6-20020a056a002d8600b0068a59c6c0a6mr18973480pfb.24.1698265471729; Wed, 25 Oct 2023 13:24:31 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:31 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 04/21] ACPI: irq: Add support for deferred probe in acpi_register_gsi() Date: Thu, 26 Oct 2023 01:53:27 +0530 Message-Id: <20231025202344.581132-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The chip which provides the GSI support may not be initialized at the time of acpi_register_gsi(). Return -EPROBE_DEFER to support deferred probing similar to acpi_irq_get(). Signed-off-by: Sunil V L --- drivers/acpi/irq.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 1687483ff319..c06cfc9725cb 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -51,19 +51,23 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); * @polarity: polarity of the GSI to be mapped * * Returns: a valid linux IRQ number on success + * -EPROBE_DEFER if irqdomain is not available. * -EINVAL on failure */ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { + struct irq_domain *domain; struct irq_fwspec fwspec; unsigned int irq; =20 fwspec.fwnode =3D acpi_get_gsi_domain_id(gsi); - if (WARN_ON(!fwspec.fwnode)) { - pr_warn("GSI: No registered irqchip, giving up\n"); - return -EINVAL; - } + if (!fwspec.fwnode) + return -EPROBE_DEFER; + + domain =3D irq_find_matching_fwnode(fwspec.fwnode, DOMAIN_BUS_ANY); + if (!domain) + return -EPROBE_DEFER; =20 fwspec.param[0] =3D gsi; fwspec.param[1] =3D acpi_dev_get_irq_type(trigger, polarity); --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A74DEC07545 for ; Wed, 25 Oct 2023 20:24:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343695AbjJYUY7 (ORCPT ); Wed, 25 Oct 2023 16:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234833AbjJYUYl (ORCPT ); Wed, 25 Oct 2023 16:24:41 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B7BF183 for ; Wed, 25 Oct 2023 13:24:38 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6bd73395bceso116562b3a.0 for ; Wed, 25 Oct 2023 13:24:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265477; x=1698870277; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J8S/JDCmwBJX/s4tcuif01AJjqTYAtUjVSzvHHCYv3Q=; b=nNqvGjA6QPmPkU0pIK+PisNTyVgj2VgA4U5e51WIi1UAtB68oOcDrAFNkopUNesM5k x5L/8RGmTh7GA0rwpMIDrGTAfFijRQogXgvaxhxfntL7XlcCcztZsFKcL45pLMhuRGcP HDaG3Z2kIzvvvvrPWQh+rvSak5AwjfkNG5+O6B6BLQxWc+MTHPvMxYWttNwgWppF25vJ glcd/sy1FvIwxr7bfe//85NgZBsIJ+qhTJAByTugflLc9l77og8LLV94aKgAb/i72lJx V4qVcEQj5eXnFn3BigSXcUMY7LN3Zr7E5hveMCoS84pk0QvbHq4XbsyfXz85Gezfp/m6 Tuvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265477; x=1698870277; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J8S/JDCmwBJX/s4tcuif01AJjqTYAtUjVSzvHHCYv3Q=; b=E40DiD5HY6sbrwxKjOcn/Q+x3z9itz1WhMPaMn7IJSuSLrzx8rAw37lyFCMmtEpTXX XJd8l2yM/QOIt9qzd12FN9ayUE/5UNk8h480s3ILGVynyEOZd12L7JGFpbzqhoky/g0I 8wl85HHfhm5j9lSJL7MIRXi4uqtIOkhuEdOMs89xX7hlz5GhqSOVDddSDfSEz7WWCF38 8zi5anjRDt68sEcRwO+wTrJ2OquiaW6IJdwxed0KH4+W+cMsVFwPEvt5oh85l5a09XWO drSagMXrtUkNV+O06I1HivJxS/1TMirnJp0nWxvY0JZxZXGekBAk/CT7hT5LRXdk/78Q iGQQ== X-Gm-Message-State: AOJu0Yx6ZNcZ+B7UkFHRp/G/W9oQngOiy9jcO10VJQsR5iIyz1OkIYbR 3d9Z44wcexo2cpQqrUeHF+CqMQ== X-Google-Smtp-Source: AGHT+IGn0Ntg16V2ATutjBKN8vUehxORe09c59/GsjNsvnPR9Qebb6VfuMhALgVB74e2gHGUr8GJNA== X-Received: by 2002:a05:6a00:1396:b0:68f:b015:ea99 with SMTP id t22-20020a056a00139600b0068fb015ea99mr913751pfg.10.1698265477463; Wed, 25 Oct 2023 13:24:37 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:37 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 05/21] pnp.h: Return -EPROBE_DEFER for disabled IRQ resource in pnp_irq() Date: Thu, 26 Oct 2023 01:53:28 +0530 Message-Id: <20231025202344.581132-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To support deferred PNP driver probe, pnp_irq() must return -EPROBE_DEFER so that the device driver can do deferred probe if the interrupt controller is not probed early. Signed-off-by: Sunil V L --- include/linux/pnp.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/pnp.h b/include/linux/pnp.h index c2a7cfbca713..21cf833789fb 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -147,12 +147,18 @@ static inline resource_size_t pnp_mem_len(struct pnp_= dev *dev, } =20 =20 -static inline resource_size_t pnp_irq(struct pnp_dev *dev, unsigned int ba= r) +static inline int pnp_irq(struct pnp_dev *dev, unsigned int bar) { struct resource *res =3D pnp_get_resource(dev, IORESOURCE_IRQ, bar); =20 - if (pnp_resource_valid(res)) + if (pnp_resource_valid(res)) { +#if IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI) + if (!pnp_resource_enabled(res)) + return -EPROBE_DEFER; +#endif + return res->start; + } return -1; } =20 --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF19C25B6B for ; Wed, 25 Oct 2023 20:25:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234969AbjJYUZC (ORCPT ); Wed, 25 Oct 2023 16:25:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234693AbjJYUYs (ORCPT ); Wed, 25 Oct 2023 16:24:48 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6834D4A for ; Wed, 25 Oct 2023 13:24:43 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-577fff1cae6so96832a12.1 for ; Wed, 25 Oct 2023 13:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265483; x=1698870283; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GmA5kOKekb5h3Uw1k+e0LhCWijGnTH8utnJ5szxpch8=; b=auVS/K/Jk7vgky4MjvSPyw3256thHNswIFM0+CHRJfw8cZMbSsKDL7aCq9OiRUFHIn vhqWb1Ba0aPYiVgfisYHsfrxFFdjBfLbOs15MAzbLhPHxuRqT5s81JCMSPHp7u4BnRry 2ZPfCe8yqF4CGCh/KyUFfF2HFzYkNOEEm7i8nBl2N857thL2U0IW97wJcK88BIZUrGVV OYTNiUslB8+H3xiH1zs8mwP083VVwgO4yBf3eLBh2Fzc2+Waue+65NOTaD2v8RT8lmcd FXE3K1JffCz/cOrAvDcRniAps0d0N0MF3sseo29l7YXpoM1uetpW//TUo52Ge7kHw90C KoUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265483; x=1698870283; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GmA5kOKekb5h3Uw1k+e0LhCWijGnTH8utnJ5szxpch8=; b=cwsUJ8u2ud2so69Osh17GWsyDu6kpqlDiwv1/v8oJBweNBamMKFdO/BetxhXEzMtxs i3l2LJXseL8f6lE555Jr/mhkXGJCWr+2pIOi8qUe9swqEExov8DAvYUZTs7h9MbNPTY4 llN/ODRwkkLrAfJ1bT7LeWeHyYlX2QijlfFQyXgT2DkvSs2qrXtJiIgMhlVqgCNk5HXZ q3rsEVQifVeesoekcOne0DMKwQLwqeHPHorJdo4x+IdL7/T1Ds3r9v9b+qY8JL6jn7Ej Fi4ppm9DFrzQxTPRt+RbPAld0t59MnKGCMhdYLmBSnsTVVEZRm1DDdi8y6+1rbHmsJfT u4vA== X-Gm-Message-State: AOJu0Yxa2D5CnPV1isv2BzvZUccVQnAYBO3jioWd46Bixg1PYZhuGgnn tDZ+EIt6INmUrO/AfInKteaHFQ== X-Google-Smtp-Source: AGHT+IEWaGrpkEpDFbneFUdLQrgY3wxCJPmh6tSJaEBSJOipB/ao+CEA+asAJLO3X3etojz+m4Eg/g== X-Received: by 2002:a05:6a21:999c:b0:17a:f4b6:bf89 with SMTP id ve28-20020a056a21999c00b0017af4b6bf89mr713082pzb.31.1698265483317; Wed, 25 Oct 2023 13:24:43 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:42 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 06/21] RISC-V: Kconfig: Select deferred GSI probe for ACPI systems Date: Thu, 26 Oct 2023 01:53:29 +0530 Message-Id: <20231025202344.581132-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On RISC-V platforms, apart from root interrupt controllers (which provide local interrupts and IPI), other interrupt controllers in the hierarchy are probed late. Enable this select this CONFIG option for RISC-V platforms so that device drivers which connect to deferred interrupt controllers can take appropriate action. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8c105a151e12..b62441aefa6a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,7 @@ config 32BIT =20 config RISCV def_bool y + select ARCH_ACPI_DEFERRED_GSI if ACPI select ACPI_GENERIC_GSI if ACPI select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B500C0032E for ; Wed, 25 Oct 2023 20:25:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343840AbjJYUZN (ORCPT ); Wed, 25 Oct 2023 16:25:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235001AbjJYUYz (ORCPT ); Wed, 25 Oct 2023 16:24:55 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D890610DE for ; Wed, 25 Oct 2023 13:24:49 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6b36e1fcee9so129349b3a.3 for ; Wed, 25 Oct 2023 13:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265489; x=1698870289; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2bjA2IFkbvQ+cjwZ90V9r6vmNOzBSbezE1qJqMO1A+c=; b=eJujG6QRF1LoqNfAqafA4JP/kq7hTbjci2TIo9bHxvPUlxqdX/zQcNl0n6qfWEyjut 5CtQ2sPrekj/5bfbgo8qQK9MGC8/B0e5NtB5BDxQbRXVnc4aIb/tweaYpQf6JKA/BIJb rucTEkR+rs0lOGJoWuWG7sgy2LZLnlxlmgrSClK2IHBzB+v2H9jFLHJpbXASppyFAVcK kj0G3gqmO40Aqlxj8Z4LKnqmiq/z8GKI6UQkv1Y1w5a8dJoXoly0r4CGsRZy4dYotPjo IyYFZIytQmcY2z3HDtKnJYF2xaGF509bS6t9YxW/zPkRmcEtCrGGA/Ol7rBIFQjWmuIe EFsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265489; x=1698870289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2bjA2IFkbvQ+cjwZ90V9r6vmNOzBSbezE1qJqMO1A+c=; b=ah0pN2JjhKYBWYUVgm6p7dZsSdzZSwi6zk36OvPbKje6hJhnS9cXt7QBPCNYaqzHwV yw5K9ZKKHTI72AAEa7E1E1eTZ7iPp+iV8UGdtRzn5eCFwFBe5qsePr5okY1drDvgbAn5 zwERAhKVHlCZjQ9rcFa0FTRnHzEkjqPahhV2/QxSshetF4CI/82Z40+AM/CNQZEykIjQ N6GyJ/27oeZ0BZBuzcDbLbyPtPgKadrbtxbPxvoVrZS9FPjCkRhKiAxpGMoNtWQUTbwL pgJc19T1qxdWyefD/wclKXb8k3pjY5suMCvzzMOHfUU4e3uNsMXSjnE7xycOLbrtTIwm VfYg== X-Gm-Message-State: AOJu0YwE7RfxY1nGxHp4ChyvKjEak0QCejjzZlQpvkyaxkkz5Mdx9pBz b8X6glkQdmpBABiQWnKilgwlIQ== X-Google-Smtp-Source: AGHT+IG0SpgdyiZkoMurZXPLkoY/g9K3mifAR/RprvidWByJ+cvRjgFm+eLWR/dX/aORh+7WvaUdiA== X-Received: by 2002:a05:6a21:33a4:b0:17b:3cd6:b1bc with SMTP id yy36-20020a056a2133a400b0017b3cd6b1bcmr8121322pzb.14.1698265489371; Wed, 25 Oct 2023 13:24:49 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:48 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 07/21] serial: 8250_pnp: Add support for deferred probe Date: Thu, 26 Oct 2023 01:53:30 +0530 Message-Id: <20231025202344.581132-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With pnp_irq() able to return error code, enhance the serial pnp driver to support deferred probing. Return -EPROBE_DEFER when pnp_irq() returns the same so that the driver probe is deferred. Signed-off-by: Sunil V L --- drivers/tty/serial/8250/8250_pnp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8= 250_pnp.c index 1974bbadc975..dcb3daf7c816 100644 --- a/drivers/tty/serial/8250/8250_pnp.c +++ b/drivers/tty/serial/8250/8250_pnp.c @@ -8,6 +8,7 @@ * * Ported to the Linux PnP Layer - (C) Adam Belay. */ +#include #include #include #include @@ -443,8 +444,21 @@ serial_pnp_probe(struct pnp_dev *dev, const struct pnp= _device_id *dev_id) } =20 memset(&uart, 0, sizeof(uart)); - if (pnp_irq_valid(dev, 0)) - uart.port.irq =3D pnp_irq(dev, 0); + if (pnp_irq_valid(dev, 0)) { + ret =3D pnp_irq(dev, 0); + if (ret =3D=3D -EPROBE_DEFER) { + struct resource r; + + ret =3D acpi_irq_get(ACPI_HANDLE(&dev->dev), 0, &r); + if (!ret) + uart.port.irq =3D r.start; + else + return ret; + } else { + uart.port.irq =3D ret; + } + } + if ((flags & CIR_PORT) && pnp_port_valid(dev, 2)) { uart.port.iobase =3D pnp_port_start(dev, 2); uart.port.iotype =3D UPIO_PORT; --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49A64C25B6F for ; Wed, 25 Oct 2023 20:25:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343911AbjJYUZ2 (ORCPT ); Wed, 25 Oct 2023 16:25:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232076AbjJYUZD (ORCPT ); Wed, 25 Oct 2023 16:25:03 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4412A18C for ; Wed, 25 Oct 2023 13:24:55 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6934202b8bdso143110b3a.1 for ; Wed, 25 Oct 2023 13:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265495; x=1698870295; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jdOBYbLR+bXetJ+YmrkOyswglZ/H3DLDZKjYZYq4pUE=; b=HmX0WIx5ZKR8Cg3REtV8WvU+4A28I3jLrhYLezQY+rp0mQhBER7xMb/ToHKODSjlj7 9aLYkV02gUF/2XnEVo1AwnEOt58O6rZquL0s3P53ziGLqlbYyPbjdycjDYoUW1stjWvr rKgGnj5V3bcFCfmCjdxyPLXDN0xB2fxplJUE3DqCkdHc3mzjVEKH0kXwgsDTy4hYAqP9 P/WBTpzN7E0ZoKTHRR2UA05tUxCkaAIkx+j19OSo9SBppQIUcY9JUwadvgwhh3sG76gl R7B0oJcJMu5lOEj+1NQvmnD88vwGK+ehl5SxiF0Ecwg7iRYw96TElPdqUlCsZbN/v6ch 4ANw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265495; x=1698870295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jdOBYbLR+bXetJ+YmrkOyswglZ/H3DLDZKjYZYq4pUE=; b=iMGDDsoXNGhnZeG2fsx/YLaNIJTlg0RbtjScz2mDdl3dj7st7zFwiKwqjNRqgQlh6F LETtDfU2NYs6FU3YxEn6StbIX5zz0MXnIX5TOI9Nr8cCeIk2rWEYU1WdApgPx6EjdjBE Jtsb+Iz2s/ETiZ8z56c3+s7m4+5+sEHcoKvS0624HyiueS80+ZoHnlketLQg8hkh7aSp 27o7QnmOdG9mRUi6VLU+/ZxOl+fIJ6db3PHA/9IVl3ib4wI8TYmzGeHjbrM2ETjFKoWK 9elMPtQKQJE8Q67mSiEmmlVyheAYAy0mWko1KUXF0bfoNmBw3xJXrychMnNbNmbdSKC8 aCpQ== X-Gm-Message-State: AOJu0Yw1yt0QiGh4TFulGFjkHKFj4FSds1EyLvCEjYnKdCJzg73shsvp RJAOWJEkTZIrvq59zwSKHbes1g== X-Google-Smtp-Source: AGHT+IGOtWmx7Z9hH5AFpr5sZFQnzIJZNuxwJNKWTB6+enKWMWr67WgjO7Vy6dwjrSM8D50mINvLmA== X-Received: by 2002:aa7:888b:0:b0:6bd:9281:9446 with SMTP id z11-20020aa7888b000000b006bd92819446mr19185035pfe.10.1698265495348; Wed, 25 Oct 2023 13:24:55 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:24:54 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 08/21] ACPI: pci_irq: Avoid warning for deferred probe in acpi_pci_irq_enable() Date: Thu, 26 Oct 2023 01:53:31 +0530 Message-Id: <20231025202344.581132-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When the architecture like RISC-V supports deferred GSI interrupt controller probe, acpi_register_gsi() can return -EPROBE_DEFER which is a valid use case to delay the dependent driver probe. So, avoid printing the warning for the deferred probe case. Signed-off-by: Sunil V L --- drivers/acpi/pci_irq.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c index ff30ceca2203..f7d0822da08f 100644 --- a/drivers/acpi/pci_irq.c +++ b/drivers/acpi/pci_irq.c @@ -452,8 +452,11 @@ int acpi_pci_irq_enable(struct pci_dev *dev) =20 rc =3D acpi_register_gsi(&dev->dev, gsi, triggering, polarity); if (rc < 0) { - dev_warn(&dev->dev, "PCI INT %c: failed to register GSI\n", - pin_name(pin)); + if (rc !=3D -EPROBE_DEFER) { + dev_warn(&dev->dev, "PCI INT %c: failed to register GSI\n", + pin_name(pin)); + } + kfree(entry); return rc; } --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0466C07545 for ; Wed, 25 Oct 2023 20:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234062AbjJYUZg (ORCPT ); Wed, 25 Oct 2023 16:25:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235053AbjJYUZL (ORCPT ); Wed, 25 Oct 2023 16:25:11 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C307210C9 for ; Wed, 25 Oct 2023 13:25:01 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6bee11456baso135447b3a.1 for ; Wed, 25 Oct 2023 13:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265501; x=1698870301; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rTitWHvbkwllUIYzM7TBpB/hreitIS32ztyb9Cf5EZw=; b=D4SzcIRpEAoSD2gyJoIcTnEFFf04Mx+Q2l/0KvosZJ+xD5NZqpKoeWIC00Ga/ET5mR XzouaS+YX2WSYqspovVJ39D8YRYcVLoZmxvWK7FY8ie+mj8CqUjn3y0FtiqM5S44KKJ/ dPSs87lGFRQ3HzhUYV1v2Ot/J3bTveLemiD+zQdMM6OAQNhLUSehw41nmX3ExU858j07 cxnFTuknGDvi6F6cb+xHfRvRs7wZGoDt082OQwrmtJpULryJakb7wwV62wjmhFaUtPKr zmXN/X1sRC26AjtzYihpKXdyp6uMRdGz6xWntJchH71/9cInvwIZtV5Htn2VNNkaK60V 9s/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265501; x=1698870301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rTitWHvbkwllUIYzM7TBpB/hreitIS32ztyb9Cf5EZw=; b=wyDGbTa7pkKW7nrbuI56nPM2Ucm09u3t48sXrcfu+43VKr0oFzz0rv0gNAZpKXA6eM LJ8NNG6GnadMWOGum1WnzhKhGhHD6b3fgu22MqSZY+wFODGfz0GoVFtlDlcKKnYkh9tq mP4iL+cH5Eo6Feh7I+4LtqM3Jg1pTHOwX78FyxNejyCOLfd/Gk8uU2nWIcoPKYHSrPAi oxp9Xu8fNewit+y3GJZMMilVHcH+DsB4w4AGRAA2xaiB27Sfy4XsjbWfVD2E6XZD9Pga 0U5o8fM4eMqMNatF7d6JnWVfDIZmov4wooQBQSAD/57Yz1XTi1mGPRDBXnFZQ1zvxNs8 Ikkg== X-Gm-Message-State: AOJu0Yzqq4In/6ubEf7KHYKE59PiSIXG06yVRX56EWDD0TsixutoLiw/ TY9XmVPHQ8JNq1uk4KtlqbV+Vw== X-Google-Smtp-Source: AGHT+IFxa1VnMrjTGhwV07IKwl5LjRCiwN2wledHcfI6/uXGW7IWW0Iy/XFASuJINb+BuyvT7MzlLA== X-Received: by 2002:a05:6a20:244d:b0:17a:d560:5d13 with SMTP id t13-20020a056a20244d00b0017ad5605d13mr7578124pzc.22.1698265501053; Wed, 25 Oct 2023 13:25:01 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:00 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 09/21] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Date: Thu, 26 Oct 2023 01:53:32 +0530 Message-Id: <20231025202344.581132-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Unlike OF framework, the irqchip probe using IRQCHIP_ACPI_DECLARE has no order defined. Depending on the driver Makefile is not a good idea. So, usually it is worked around by mandating only root interrupt controller probed using IRQCHIP_ACPI_DECLARE and other interrupt controllers are probed via cascade mechanism. However, this is also not a clean solution because if there are multiple root controllers (ex: RINTC in RISC-V which is per CPU) which need to be probed first, then the cascade will happen for every root controller. So, introduce a architecture specific weak function to order the probing of the interrupt controllers which can be implemented by different architectures as per their interrupt controller hierarchy. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 3 +++ include/linux/acpi.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 691d4b7686ee..87f4baebd497 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2685,6 +2685,8 @@ static int __init acpi_match_madt(union acpi_subtable= _headers *header, return 0; } =20 +void __weak arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int = nr) { } + int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int= nr) { int count =3D 0; @@ -2693,6 +2695,7 @@ int __init __acpi_probe_device_table(struct acpi_prob= e_entry *ap_head, int nr) return 0; =20 mutex_lock(&acpi_probe_mutex); + arch_sort_irqchip_probe(ap_head, nr); for (ape =3D ap_head; nr; ape++, nr--) { if (ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) { acpi_probe_count =3D 0; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index afd94c9b8b8a..4ad256a0039c 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1338,6 +1338,8 @@ struct acpi_probe_entry { kernel_ulong_t driver_data; }; =20 +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr); + #define ACPI_DECLARE_PROBE_ENTRY(table, name, table_id, subtable, \ valid, data, fn) \ static const struct acpi_probe_entry __acpi_probe_##name \ --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96699C07545 for ; Wed, 25 Oct 2023 20:25:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbjJYUZv (ORCPT ); Wed, 25 Oct 2023 16:25:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235017AbjJYUZX (ORCPT ); Wed, 25 Oct 2023 16:25:23 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29473186 for ; Wed, 25 Oct 2023 13:25:08 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-68fb85afef4so141132b3a.1 for ; Wed, 25 Oct 2023 13:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265507; x=1698870307; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DxzCTJ+m1lwBq+RMy/cftySc6UneYPqTwJF8JhbniDw=; b=ZPLmnXDKPZLMM7hvckqFB2ntxJxslVmafoVfCnIBGcAkzqfeTNJuG9pmeNldNV76HJ 0HpfULSlA8evJEUByNoND/DmGd3FIeaXHbNI1pxyaqpjdaY4X3tF7H0XvCO9qvP1Drng cbIwFP8L62WWzSzWSKl4P/oK3fD1+t28RoGlCUrH1AlKHXUUbBdVGphLg2lo73kpxRv4 xITjhtKRagCg+enUe+XhHCl23XZovrVZ9wWYR7+bzcUc8nXi7UrjAhUm2JqsVuCKnIAA R2qdeVwXrTTqZ+XRyU3kDZDy0ksm1dhBzVS0snoB8lC2C9/KjyPCnDY29sZPMsD3qGZw pqbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265507; x=1698870307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DxzCTJ+m1lwBq+RMy/cftySc6UneYPqTwJF8JhbniDw=; b=QLZz//XgQ/mbzPsxrGFc6Y8VU6F34QmZCtBkeN98otIg6/DI5xt74TtO677sk2lzqf YP2ThUpQ1bENtuF/Rh48NfNx7vJaUTys+WRYpevgrPidkxRn0GtarII7taYD2QRm3KGv 4fHb7CVwPwV8uxZ6bTyJai9FrkpezifN+FUohm78rDJiguDTVFSkGeoAAarnqv6zXrhj cHK4UJtgMWPGH+wYGMW5OgvcQ4Ru3oc/fMKOoiix9J1b0SDNFbvHGcQ89+PscxpMb/dR vCv/cPF31nFDZWoYRifzOHT/1V3++GH7QFakJj9OEFqTZyBbjZDxNg4sh6TCRXFw81/l Mm0Q== X-Gm-Message-State: AOJu0YzbImcLIbjEkXY/uFbW0Lr/RHMK0x9EvAk9Gs5cYl5F6Ey2OdAi TSx+VzF9DlQoa3X/2rJmW8b8vA== X-Google-Smtp-Source: AGHT+IFKGK+9x6obxjzCs3/eR+3q/3iIQzNNW6EXTTk1GAvemcOrYvQgO6IFBiNDzQzfVY0iJ8I2bw== X-Received: by 2002:a05:6a00:2d91:b0:690:d4fa:d43d with SMTP id fb17-20020a056a002d9100b00690d4fad43dmr14404404pfb.6.1698265506987; Wed, 25 Oct 2023 13:25:06 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:06 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 10/21] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries Date: Thu, 26 Oct 2023 01:53:33 +0530 Message-Id: <20231025202344.581132-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ACPI MADT entries for interrupt controllers don't have a way to describe the hierarchy. However, the hierarchy is known to the architecture and on RISC-V platforms, the MADT sub table types are ordered in the incremental order from the root controller which is RINTC. So, add architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy as below. RINTC->IMSIC->APLIC->PLIC Signed-off-by: Sunil V L --- drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/irq.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b3b126e0b94..f80b3da230e9 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o +obj-y +=3D rhct.o irq.o diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c new file mode 100644 index 000000000000..36e0525b3235 --- /dev/null +++ b/drivers/acpi/riscv/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include + +static int irqchip_cmp_func(const void *in0, const void *in1) +{ + struct acpi_probe_entry *elem0 =3D (struct acpi_probe_entry *)in0; + struct acpi_probe_entry *elem1 =3D (struct acpi_probe_entry *)in1; + + return (elem0->type > elem1->type) - (elem0->type < elem1->type); +} + +/* + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any + * order, this arch function will reorder the probe functions as per the + * required order for the architecture. + */ +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) +{ + struct acpi_probe_entry *ape =3D ap_head; + + if (nr =3D=3D 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) + return; + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); +} --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A57E9C07545 for ; Wed, 25 Oct 2023 20:26:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234984AbjJYU0C (ORCPT ); Wed, 25 Oct 2023 16:26:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343904AbjJYUZ2 (ORCPT ); Wed, 25 Oct 2023 16:25:28 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1ACB10F1 for ; Wed, 25 Oct 2023 13:25:13 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6b77ab73c6fso101444b3a.1 for ; Wed, 25 Oct 2023 13:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265513; x=1698870313; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ksJT9a6E7b+AgWOW+0QqZAQKxEPs+GfkSTk4Wygp/9k=; b=JPtX39ivNbt4Wu54KHQbjp1dzqEbHENSrbcvDK7ihL8aouRjgAM1qBg0f08HtA9Epz uqxhuOgJssIxhOx5Hdtxi2qNqGoiGAOTpJHtqhzM8/RCoJrrOyAWwNbj7WgPxnxdhNJ/ QUCcaLA6nIsojuBhfGSIcOAOGAS30PqwI+9t1tNo9RNydJmC8xkKN3pJEfZCXMfEY6XK XXfnvzgLivw+nwMJOq+PVT3Azu/kavUkoHQdT5Fpb7im21YBKGATma9lx07I7CqEHUUh g8ix8mJPToO7AYfDx1nMKi5QnmRiTuIVnEkjuyp+JOi8/WevGG0hM3Q0gsPDw916+c6y jUGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265513; x=1698870313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ksJT9a6E7b+AgWOW+0QqZAQKxEPs+GfkSTk4Wygp/9k=; b=NdXvqpD0In62gq/E5SpCyYors+XhjO0WxIFRTpDQlEu1nH7wllYuPeOXZ1ca27FJsR UX1QKHwHdKOCm4f0PR/NlDSakV6x0aRnkoyymN55ic6bMYwECSD6GlSONAppFGcx+A6x inl2xATiIUeLXArxNY/kEE9xbJvyYUbaezVvRsvGO+cXmj/yLrD0UEIxd604k/OX7c0B jn/RNVk7RjCdUT/jnj/hIwqdQBexEGAjrqSmkHfRjE+y7kDLQp9wYmocZgZz22GwAMFO o8dxhW7QcSmP7nzx5+xC0AW8V+D5bMtQl8jkVhPXLi0GtTkd0TmejS8VmQkAU4TpkA2t eG6w== X-Gm-Message-State: AOJu0Ywl6mZRFSeaOB9sxSwotwCMcqkcTGn/byHgdiUwsNlCd5u2ctgA ufosK/i7cb5RcFihf25Ya47M+P8xar0lVLgWfLtYig== X-Google-Smtp-Source: AGHT+IEV/ROdZJJDw08iKQqN+bmgqdHT2tEV8SRCTGnJc4fD81is4j8SLEFb3dBe1vSckHTdkPvdfA== X-Received: by 2002:a05:6a00:478c:b0:6b4:64ac:eab2 with SMTP id dh12-20020a056a00478c00b006b464aceab2mr801836pfb.1.1698265512788; Wed, 25 Oct 2023 13:25:12 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:12 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 11/21] PCI: MSI: Add helper function to set system wide MSI support Date: Thu, 26 Oct 2023 01:53:34 +0530 Message-Id: <20231025202344.581132-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like pci_no_msi() used to disable MSI support, add a function to enable system wide MSI support. Signed-off-by: Sunil V L --- drivers/pci/msi/msi.c | 5 +++++ drivers/pci/pci.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index ef1d8857a51b..e76ccb8b5f0b 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -913,3 +913,8 @@ void pci_no_msi(void) { pci_msi_enable =3D 0; } + +void pci_set_msi(void) +{ + pci_msi_enable =3D 1; +} diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 39a8932dc340..2f876c29f75c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -167,8 +167,10 @@ extern unsigned int pci_pm_d3hot_delay; =20 #ifdef CONFIG_PCI_MSI void pci_no_msi(void); +void pci_set_msi(void); #else static inline void pci_no_msi(void) { } +static inline void pci_set_msi(void) { } #endif =20 void pci_realloc_get_opt(char *); --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D67C25B6B for ; Wed, 25 Oct 2023 20:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343895AbjJYU0P (ORCPT ); Wed, 25 Oct 2023 16:26:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235045AbjJYUZm (ORCPT ); Wed, 25 Oct 2023 16:25:42 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C9C119AA for ; Wed, 25 Oct 2023 13:25:19 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6934202b8bdso143407b3a.1 for ; Wed, 25 Oct 2023 13:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265519; x=1698870319; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5kojFGf2ZSJMlibBdobzZmgsjyx4Ywkx3WkwDcrmlX4=; b=bc4o5R2uRaA6wRDr326evH2qCIY9KhXBqmOap9Rh/as79Qpcg2Qicy4H+VVxFUknNu k4xMf/iXntL0KNo4tITE354JEJ95D9q2fdE+TV7dvjkBac+pd2TI2xoPHFgeP5bmWlsy u5bWElwny2aXk+K/OT1ttCkjs8jSk4H36BTZQrgZQ77cvpSmHm+va+WOAchlKFhdBxMa d4aK1Bu9VaQt6GGDiueX/nis1P4GNpLukPI6x6P7cKWUz8xPut3EL/m9G1kNkWIniLXN ylixWR1+htq/nm9vivn5WMHaHVBkEPwLuqJQfdIuoI6+ko3baX8+AqmTB0gvpHsd9pi1 Ddow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265519; x=1698870319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5kojFGf2ZSJMlibBdobzZmgsjyx4Ywkx3WkwDcrmlX4=; b=lcCEJqDxIl6KnhksGhxSK83EYjP2tWgE9IdDQXHvDpH+Mr83SGU0a2KvRxTRzoeIZZ axipK66zTxcyVdORLMrT1WEcVfbtr0e543Q3FHytXz/zA2obJgLd8puZTeanysNz8PFd pojSstXe2rOz3pptWO35ICzN3RjJDixSheej57MPCBVTxI26JJoa3NTpwEsOiNUeBcNM M1D8DkJOY1hfzoS+4VQWmrb6jyc1807CC3Sspmi+IpShjR7Pcapill9xGjTTZ6aTPtoI voCQXrat3dnwIZBSlCPZOcxglZDy5dfeKYK3VHcIn/iB+zSChTbPmOwYWaGUKEc8rG6n nOiA== X-Gm-Message-State: AOJu0Yw/ih4WIjh2c2DCf+07MbscapLe6NK61whGB9B7CXtjFlQ91l7M c6ArrNh+nmbh51yDMbSgBClzYw== X-Google-Smtp-Source: AGHT+IEA5VCpygjnJt29h1aUuFMuVqz64Qf8m3MJ6i95Ryf0OFy3qLoON8TOXsusky9X3JJetvXkcA== X-Received: by 2002:aa7:888b:0:b0:6bd:9281:9446 with SMTP id z11-20020aa7888b000000b006bd92819446mr19186279pfe.10.1698265518840; Wed, 25 Oct 2023 13:25:18 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:18 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 12/21] PCI: pci-acpi.c: Return correct value from pcibios_alloc_irq() Date: Thu, 26 Oct 2023 01:53:35 +0530 Message-Id: <20231025202344.581132-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Return the correct value from pcibios_alloc_irq(). Signed-off-by: Sunil V L --- drivers/pci/pci-acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index c8c3369fd69f..80dc0b290544 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1528,7 +1528,7 @@ arch_initcall(acpi_pci_init); int pcibios_alloc_irq(struct pci_dev *dev) { if (!acpi_disabled) - acpi_pci_irq_enable(dev); + return acpi_pci_irq_enable(dev); =20 return 0; } --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC9C2C25B6B for ; Wed, 25 Oct 2023 20:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234924AbjJYU01 (ORCPT ); Wed, 25 Oct 2023 16:26:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234970AbjJYUZv (ORCPT ); Wed, 25 Oct 2023 16:25:51 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FD2ED43 for ; Wed, 25 Oct 2023 13:25:25 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-692c02adeefso117658b3a.3 for ; Wed, 25 Oct 2023 13:25:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265524; x=1698870324; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; b=URUZqepln5skTYSBf/XT3SADJoAEDzSaiOx1t4S5Kaj1Z9nHFrKpThnmJKlj3XEX0L IruYc0nrtO3VBVP86UYKHGbmR36Jp+VyUooEVVczi8a73Qa0NN+HCbfDt1A2O+al89Cb MiG+Ne/KCKu/AJYAUteb3WzIASWYmKzO3BKgL1q6CD56xfXQYZwbokP5Y8CHsPzphUma Jx/Gn8EFKQhlz4gYPUnlElEZ9MtN0uNCZt3U8X4QpLAJNKaQyT6blomRDoBfGoOxbQEk mQsfRZN1iN2AUc1eVJ58AfiZHUyGu0K5OshsmcUXAMrl4BnbPl7oNW6+1LU+tqw/47Si EfFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265524; x=1698870324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; b=YDd5A6SxVG7ckZtFbjDSCLewyylo2qQZVWtSuUGd05TVl8X1eh6bW1giLZwgv//rpV Mnfk7P1s6/fdc07xEii0pbSTIvZ3mxqK1pgP7sIAxKTazzgru09hRyXjJDdb13SmQB8V 7cIrFjXgfaO6ldk3JFR+l/fLx/UYKdb8MP4/YOcl0FRaMKi/9EyUXVNFDJ2T5lc22ONH myV13akCe1yfOuRcIyCNsyxDFi2JWtS3/9t4U5j+4G4iFuxzsi/xkIdeeyUFILjYNks5 jIBXPl8K4Ubs9i9+kQn3nnSwVB9wgBFXItg7xhVW1dOzptZ/ieVYHHvpI7YGP13WS93x YajQ== X-Gm-Message-State: AOJu0YwVtoCBB/tNgQkDYHKLphvjlehh/aC55A1w+FqNb4uDB7baEpdN BnujD+q6AlPOt5GlOHNQDRRM4Q== X-Google-Smtp-Source: AGHT+IFPlOatmRNqoaJdN/uiIc4rgGDuO2Pill7cAMn3lrtLqGzsWF+Wh7Mt4TtUqA866AzT4RiQHQ== X-Received: by 2002:a05:6a00:2d9d:b0:6be:3fbc:763f with SMTP id fb29-20020a056a002d9d00b006be3fbc763fmr15860929pfb.13.1698265524617; Wed, 25 Oct 2023 13:25:24 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:24 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 13/21] irqchip: riscv-intc: Add ACPI support for AIA Date: Thu, 26 Oct 2023 01:53:36 +0530 Message-Id: <20231025202344.581132-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RINTC subtype structure in MADT also has information about other interrupt controllers like MMIO. So, save those information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 19 ++++++ drivers/irqchip/irq-riscv-intc.c | 102 ++++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..ef102b6fa86e 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,8 +12,27 @@ =20 #include =20 +#ifdef CONFIG_ACPI + +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + +int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); +int acpi_get_plic_context(u8 id, u32 idx, int *context_id); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); + +#endif + void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); +int acpi_imsic_probe(struct fwnode_handle *parent); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index bab536bbaf2c..f3aaecde12dd 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -18,6 +18,7 @@ #include #include #include +#include "../pci/pci.h" =20 static struct irq_domain *intc_domain; =20 @@ -195,13 +196,100 @@ IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_= init); =20 #ifdef CONFIG_ACPI =20 +struct rintc_data { + u32 ext_intc_id; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +int acpi_get_intc_index_hartid(u32 index, unsigned long *hartid) +{ + if (index >=3D nr_rintc) + return -1; + + *hartid =3D rintc_acpi_data[index]->hart_id; + return 0; +} + +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) { + if (idx =3D=3D j) { + *hartid =3D rintc_acpi_data[i]->hart_id; + return 0; + } + j++; + } + } + + return -1; +} + +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) + j++; + } + + *nr_contexts =3D j; +} + +int acpi_get_plic_context(u8 id, u32 idx, int *context_id) +{ + int i, j =3D 0; + + for (i =3D 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) =3D=3D id) { + if (idx =3D=3D j) { + *context_id =3D IDC_CONTEXT_ID(rintc_acpi_data[i]->ext_intc_id); + return 0; + } + + j++; + } + } + + return -1; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >=3D nr_rintc) + return -1; + + res->start =3D rintc_acpi_data[index]->imsic_addr; + res->end =3D res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags =3D IORESOURCE_MEM; + return 0; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { struct fwnode_handle *fn; struct acpi_madt_rintc *rintc; + int rc; =20 rintc =3D (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] =3D kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KE= RNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id =3D rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id =3D rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr =3D rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size =3D rintc->imsic_size; + nr_rintc++; =20 /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -218,7 +306,19 @@ static int __init riscv_intc_acpi_init(union acpi_subt= able_headers *header, return -ENOMEM; } =20 - return riscv_intc_init_common(fn); + rc =3D riscv_intc_init_common(fn); + if (rc) { + irq_domain_free_fwnode(fn); + return rc; + } + + /* + * MSI controller (IMSIC) in RISC-V is optional. So, unless + * IMSIC is discovered, set system wide MSI support as + * unsupported. Once IMSIC is probed, MSI support will be set. + */ + pci_no_msi(); + return 0; } =20 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B291C25B6F for ; Wed, 25 Oct 2023 20:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235035AbjJYU0h (ORCPT ); Wed, 25 Oct 2023 16:26:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbjJYU0A (ORCPT ); Wed, 25 Oct 2023 16:26:00 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13B391997 for ; Wed, 25 Oct 2023 13:25:31 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6b7f0170d7bso126893b3a.2 for ; Wed, 25 Oct 2023 13:25:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265530; x=1698870330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=59OuHyNaU3fGic7bU/ykRVEj1ISi+51hzxPyHqKgiHU=; b=WSI2LI3UouX3dGKglRC9cxWXwuqUkPEpmYoPiraER50IRbz4R4f4O5Y0mUDu7HgOdv 8bB2ySYNLz5HOQlWjpdjnHMZT42JINSI6cI6mB/y1trSz+o5zezzc5X8ZHH0gbdudnXa FYiCckhkPrUqAGHIm2UVerq6ChCVJyH7D4P2+4kc6LpYBaFs8gapeufDYDDYmTo9WjUY /ETanl4aevBbCk8hxpzPltpZZY7jAVUfJyW4dIdeeI8NEp0zRb8kg4Ew1I7Pe9eACSI0 PgXLUtPk+TuhwedPuuM1Ny9Pc4l9aRhUW5RqrlK6GP1IaEJY0AsM3JCwlL3hOtTkxu7P rL1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265530; x=1698870330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=59OuHyNaU3fGic7bU/ykRVEj1ISi+51hzxPyHqKgiHU=; b=B5FHzTmvZRDC/6eNVpSN/9gv+mZeKQ6zLD+iXLE3WXvpMF/2VBbDIlN1FSE7jhkv/X H+8ZzM5Me3QQzLo6Tght99zQ94spp1JgDlxANYBaJ8XFoK8qQ2vBNwiUAiG3jPtosesd i84FUFd/iJ7ImXTEkrrS42Lntxi+92zSX6Wc+SFq/EMyDAfy9+RUgezzkYZxeBBfIpwu aYzAhZ5YG3xpvJsmH8BQtCaE0lWk/dT8hWXkP00699YpnbZxfYGdfj3WYi1LYs8aN8lp W1JuWXRez2lMAB4t+k8b3uw8y9vRpPukp4OSLUTgwEvFbbKX+EepCfG2pI6px5xolZq6 4kiQ== X-Gm-Message-State: AOJu0YwKFmgfFOVHbgOkYjtu0/rVf8pUbOvleT5lbJhRIW3kUh3YwKxg 49mG0KLpkN3iEpwxDqLKBsuOxg== X-Google-Smtp-Source: AGHT+IHWtyasGWBG2ncOVxTr7Ff9cRNuMnmYDG5JFQmxxsN156cqaz/hByE4OSnzTGpWfiTZSkxNMg== X-Received: by 2002:a05:6a21:3b44:b0:169:7d6f:9f22 with SMTP id zy4-20020a056a213b4400b001697d6f9f22mr6291614pzb.54.1698265530438; Wed, 25 Oct 2023 13:25:30 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:29 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 14/21] irqchip: riscv-imsic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:37 +0530 Message-Id: <20231025202344.581132-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, PCI scan happens early during boot and PCI subsystem expects MSI controller is already setup. Hence, in case of ACPI, both IPI and MSI features are initialized early itself. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-imsic-early.c | 52 ++++++++- drivers/irqchip/irq-riscv-imsic-platform.c | 51 +++++--- drivers/irqchip/irq-riscv-imsic-state.c | 128 ++++++++++----------- drivers/irqchip/irq-riscv-imsic-state.h | 2 +- include/linux/irqchip/riscv-imsic.h | 10 ++ 5 files changed, 160 insertions(+), 83 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index 23f689ff5807..8ce864a7e4dd 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -5,16 +5,20 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #include =20 +#include "../pci/pci.h" #include "irq-riscv-imsic-state.h" =20 static int imsic_parent_irq; @@ -216,7 +220,7 @@ static int __init imsic_early_dt_init(struct device_nod= e *node, struct fwnode_handle *fwnode =3D &node->fwnode; =20 /* Setup IMSIC state */ - rc =3D imsic_setup_state(fwnode); + rc =3D imsic_setup_state(fwnode, NULL); if (rc) { pr_err("%pfwP: failed to setup state (error %d)\n", fwnode, rc); @@ -233,3 +237,49 @@ static int __init imsic_early_dt_init(struct device_no= de *node, return 0; } IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI + +static struct fwnode_handle *imsic_acpi_fwnode; + +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} + +static int __init imsic_early_acpi_init(union acpi_subtable_headers *heade= r, + const unsigned long end) +{ + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)header; + int rc; + + imsic_acpi_fwnode =3D irq_domain_alloc_named_fwnode("imsic"); + if (!imsic_acpi_fwnode) { + pr_err("unable to allocate IMSIC FW node\n"); + return -ENOMEM; + } + + /* Setup IMSIC state */ + rc =3D imsic_setup_state(imsic_acpi_fwnode, (void *)imsic); + if (rc) { + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, r= c); + return rc; + } + + /* Do early setup of IMSIC state and IPIs */ + rc =3D imsic_early_probe(imsic_acpi_fwnode); + if (rc) + return rc; + + rc =3D imsic_platform_acpi_probe(imsic_acpi_fwnode); + if (!rc) { + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode); + pci_set_msi(); + } + + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL, + 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index cdb659401199..f905340d24e6 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -308,43 +309,47 @@ static int imsic_irq_domains_init(struct fwnode_handl= e *fwnode) return 0; } =20 -static int imsic_platform_probe(struct platform_device *pdev) +static int imsic_platform_probe_common(struct fwnode_handle *fwnode) { - struct device *dev =3D &pdev->dev; struct imsic_global_config *global; int rc; =20 if (!imsic) { - dev_err(dev, "early driver not probed\n"); + pr_err("%pfwP: early driver not probed\n", fwnode); return -ENODEV; } =20 if (imsic->base_domain) { - dev_err(dev, "irq domain already created\n"); + pr_err("%pfwP: irq domain already created\n", fwnode); return -ENODEV; } =20 global =3D &imsic->global; =20 /* Initialize IRQ and MSI domains */ - rc =3D imsic_irq_domains_init(dev->fwnode); + rc =3D imsic_irq_domains_init(fwnode); if (rc) { - dev_err(dev, "failed to initialize IRQ and MSI domains\n"); + pr_err("%pfwP: failed to initialize IRQ and MSI domains\n", fwnode); return rc; } =20 - dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", - global->hart_index_bits, global->guest_index_bits); - dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", - global->group_index_bits, global->group_index_shift); - dev_info(dev, " per-CPU IDs %d at base PPN %pa\n", - global->nr_ids, &global->base_addr); - dev_info(dev, " total %d interrupts available\n", - imsic->nr_hwirqs); + pr_info("%pfwP: hart-index-bits: %d, guest-index-bits: %d\n", fwnode, + global->hart_index_bits, global->guest_index_bits); + pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", fwnode, + global->group_index_bits, global->group_index_shift); + pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", fwnode, + global->nr_ids, &global->base_addr); + pr_info("%pfwP: total %d interrupts available\n", fwnode, + imsic->nr_hwirqs); =20 return 0; } =20 +static int imsic_platform_dt_probe(struct platform_device *pdev) +{ + return imsic_platform_probe_common(pdev->dev.fwnode); +} + static const struct of_device_id imsic_platform_match[] =3D { { .compatible =3D "riscv,imsics" }, {} @@ -355,6 +360,22 @@ static struct platform_driver imsic_platform_driver = =3D { .name =3D "riscv-imsic", .of_match_table =3D imsic_platform_match, }, - .probe =3D imsic_platform_probe, + .probe =3D imsic_platform_dt_probe, }; builtin_platform_driver(imsic_platform_driver); + +#ifdef CONFIG_ACPI + +/* + * On ACPI based systems, PCI enumeration happens early during boot in + * acpi_scan_init(). PCI enumeration expects MSI domain setup before + * it calls pci_set_msi_domain(). Hence, unlike in DT where + * imsic-platform drive probe happens late during boot, ACPI based + * systems need to setup the MSI domain early. + */ +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode) +{ + return imsic_platform_probe_common(fwnode); +} + +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index 54465e47851c..b842c499df0a 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -5,6 +5,7 @@ */ =20 #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -593,12 +594,8 @@ static int __init imsic_get_parent_hartid(struct fwnod= e_handle *fwnode, int rc; struct of_phandle_args parent; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_intc_index_hartid(index, hartid); =20 rc =3D of_irq_parse_one(to_of_node(fwnode), index, &parent); if (rc) @@ -617,12 +614,8 @@ static int __init imsic_get_parent_hartid(struct fwnod= e_handle *fwnode, static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_imsic_mmio_info(index, res); =20 return of_address_to_resource(to_of_node(fwnode), index, res); } @@ -630,20 +623,15 @@ static int __init imsic_get_mmio_resource(struct fwno= de_handle *fwnode, static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, - u32 *nr_mmios) + u32 *nr_mmios, + void *opaque) { + struct acpi_madt_imsic *imsic =3D (struct acpi_madt_imsic *)opaque; unsigned long hartid; struct resource res; int rc; u32 i; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(fwnode)) - return -EINVAL; - *nr_parent_irqs =3D 0; *nr_mmios =3D 0; =20 @@ -656,58 +644,66 @@ static int __init imsic_parse_fwnode(struct fwnode_ha= ndle *fwnode, return -EINVAL; } =20 - /* Find number of guest index bits in MSI address */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,guest-index-bits", - &global->guest_index_bits); - if (rc) - global->guest_index_bits =3D 0; + if (is_of_node(fwnode)) { + /* Find number of guest index bits in MSI address */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits =3D 0; =20 - /* Find number of HART index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,hart-index-bits", - &global->hart_index_bits); - if (rc) { - /* Assume default value */ - global->hart_index_bits =3D __fls(*nr_parent_irqs); - if (BIT(global->hart_index_bits) < *nr_parent_irqs) - global->hart_index_bits++; - } + /* Find number of HART index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits =3D __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } =20 - /* Find number of group index bits */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,group-index-bits", - &global->group_index_bits); - if (rc) - global->group_index_bits =3D 0; + /* Find number of group index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits =3D 0; =20 - /* - * Find first bit position of group index. - * If not specified assumed the default APLIC-IMSIC configuration. - */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,group-index-shift", - &global->group_index_shift); - if (rc) - global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-shift", + &global->group_index_shift); + if (rc) + global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", fwnode); + return rc; + } =20 - /* Find number of interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,num-ids", - &global->nr_ids); - if (rc) { - pr_err("%pfwP: number of interrupt identities not found\n", - fwnode); - return rc; + /* Find number of guest interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids =3D global->nr_ids; + } else { + global->guest_index_bits =3D imsic->guest_index_bits; + global->hart_index_bits =3D imsic->hart_index_bits; + global->group_index_bits =3D imsic->group_index_bits; + global->group_index_shift =3D imsic->group_index_shift; + global->nr_ids =3D imsic->num_ids; + global->nr_guest_ids =3D imsic->num_guest_ids; } =20 - /* Find number of guest interrupt identities */ - rc =3D of_property_read_u32(to_of_node(fwnode), - "riscv,num-guest-ids", - &global->nr_guest_ids); - if (rc) - global->nr_guest_ids =3D global->nr_ids; - /* Sanity check guest index bits */ i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; if (i < global->guest_index_bits) { @@ -775,7 +771,7 @@ static int __init imsic_parse_fwnode(struct fwnode_hand= le *fwnode, return 0; } =20 -int __init imsic_setup_state(struct fwnode_handle *fwnode) +int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) { int rc, cpu; phys_addr_t base_addr; @@ -817,7 +813,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwno= de) } =20 /* Parse IMSIC fwnode */ - rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios); + rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opa= que); if (rc) goto out_free_local; =20 diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 8d209e77432e..ee1f52891e89 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -105,6 +105,6 @@ void imsic_vector_debug_show_summary(struct seq_file *m= , int ind); int imsic_hwirqs_alloc(unsigned int order); void imsic_hwirqs_free(unsigned int base_hwirq, unsigned int order); =20 -int imsic_setup_state(struct fwnode_handle *fwnode); +int imsic_setup_state(struct fwnode_handle *fwnode, void *opaque); =20 #endif diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h index cbb7bcd0e4dd..c112e5559d88 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -84,4 +84,14 @@ static inline const struct imsic_global_config *imsic_ge= t_global_config(void) =20 #endif =20 +#ifdef CONFIG_ACPI +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode); +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev); +#else +static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *d= ev) +{ + return NULL; +} +#endif + #endif --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3CA8C25B6B for ; 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Wed, 25 Oct 2023 13:25:36 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:35 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 15/21] irqchip: riscv-aplic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:38 +0530 Message-Id: <20231025202344.581132-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ACPI support in APLIC drivers. In ACPI, IO devices use Global System Interrupts (GSI) which is a flat space split across multiple APLICs. So, the driver also need to provide the mapping from GSI to correct APLIC. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 6 ++ drivers/irqchip/irq-riscv-aplic-direct.c | 22 +++-- drivers/irqchip/irq-riscv-aplic-main.c | 105 +++++++++++++++++------ drivers/irqchip/irq-riscv-aplic-main.h | 1 + drivers/irqchip/irq-riscv-aplic-msi.c | 10 ++- 5 files changed, 109 insertions(+), 35 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index ef102b6fa86e..00eb8b0333c2 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -22,6 +22,12 @@ #define APLIC_PLIC_ID(x) ((x) >> 24) #define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) =20 +#ifdef CONFIG_RISCV_APLIC +struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi); +#else +static inline struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) { ret= urn NULL; } +#endif + int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq= -riscv-aplic-direct.c index 9ed2666bfb5e..3902e6d32856 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -4,6 +4,7 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include =20 #include "irq-riscv-aplic-main.h" =20 @@ -203,17 +205,20 @@ static int aplic_direct_starting_cpu(unsigned int cpu) =20 static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, u32 *parent_hwirq, - unsigned long *parent_hartid) + unsigned long *parent_hartid, + struct aplic_priv *priv) { struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc =3D acpi_get_ext_intc_parent_hartid(priv->id, index, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), index, &parent); if (rc) @@ -251,7 +256,7 @@ int aplic_direct_setup(struct device *dev, void __iomem= *regs) =20 /* Setup per-CPU IDC and target CPU mask */ for (i =3D 0; i < priv->nr_idcs; i++) { - rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid); + rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid, priv); if (rc) { dev_warn(dev, "parent irq for IDC%d not found\n", i); continue; @@ -335,6 +340,7 @@ int aplic_direct_setup(struct device *dev, void __iomem= *regs) return -ENOMEM; } =20 + dev_set_drvdata(dev, priv); /* Advertise the interrupt controller */ dev_info(dev, "%d interrupts directly connected to %d CPUs\n", priv->nr_irqs, priv->nr_idcs); diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-r= iscv-aplic-main.c index d1b342b66551..f0ba1411c95e 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.c +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -4,12 +4,15 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ =20 +#include #include #include #include #include #include #include +#include +#include =20 #include "irq-riscv-aplic-main.h" =20 @@ -137,38 +140,44 @@ int aplic_setup_priv(struct aplic_priv *priv, struct = device *dev, void __iomem *regs) { struct of_phandle_args parent; + struct acpi_madt_aplic *aplic; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - /* Save device pointer and register base */ priv->dev =3D dev; priv->regs =3D regs; =20 - /* Find out number of interrupt sources */ - rc =3D of_property_read_u32(to_of_node(dev->fwnode), - "riscv,num-sources", - &priv->nr_irqs); - if (rc) { - dev_err(dev, "failed to get number of interrupt sources\n"); - return rc; - } - - /* - * Find out number of IDCs based on parent interrupts - * - * If "msi-parent" property is present then we ignore the - * APLIC IDCs which forces the APLIC driver to use MSI mode. - */ - if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { - while (!of_irq_parse_one(to_of_node(dev->fwnode), - priv->nr_idcs, &parent)) - priv->nr_idcs++; + if (is_of_node(dev->fwnode)) { + /* Find out number of interrupt sources */ + rc =3D of_property_read_u32(to_of_node(dev->fwnode), + "riscv,num-sources", + &priv->nr_irqs); + if (rc) { + dev_err(dev, "failed to get number of interrupt sources\n"); + return rc; + } + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { + while (!of_irq_parse_one(to_of_node(dev->fwnode), + priv->nr_idcs, &parent)) + priv->nr_idcs++; + } + } else { + aplic =3D *(struct acpi_madt_aplic **)dev_get_platdata(dev); + if (!aplic) { + dev_err(dev, "APLIC platform data is NULL!\n"); + return -1; + } + priv->gsi_base =3D aplic->gsi_base; + priv->nr_irqs =3D aplic->num_sources; + priv->nr_idcs =3D aplic->num_idcs; + priv->id =3D aplic->id; } =20 /* Setup initial state APLIC interrupts */ @@ -177,9 +186,36 @@ int aplic_setup_priv(struct aplic_priv *priv, struct d= evice *dev, return 0; } =20 +#ifdef CONFIG_ACPI + +LIST_HEAD(aplic_list); +struct aplic_priv_list { + struct aplic_priv *priv; + struct list_head list; +}; + +struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) +{ + struct aplic_priv_list *aplic_element; + struct list_head *i, *tmp; + + /* Find the APLIC that manages this GSI. */ + list_for_each_safe(i, tmp, &aplic_list) { + aplic_element =3D list_entry(i, struct aplic_priv_list, list); + if (gsi >=3D aplic_element->priv->gsi_base && + gsi < (aplic_element->priv->gsi_base + aplic_element->priv->nr_irqs)) + return aplic_element->priv->dev->fwnode; + } + + return NULL; +} + +#endif + static int aplic_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + struct aplic_priv *priv; bool msi_mode =3D false; struct resource *res; void __iomem *regs; @@ -204,6 +240,9 @@ static int aplic_probe(struct platform_device *pdev) if (is_of_node(dev->fwnode)) msi_mode =3D of_property_present(to_of_node(dev->fwnode), "msi-parent"); + else + msi_mode =3D imsic_acpi_get_fwnode(NULL) ? 1 : 0; + if (msi_mode) rc =3D aplic_msi_setup(dev, regs); else @@ -214,6 +253,20 @@ static int aplic_probe(struct platform_device *pdev) return rc; } =20 +#ifdef CONFIG_ACPI + struct aplic_priv_list *aplic_element; + + priv =3D dev_get_drvdata(dev); + if (priv) { + aplic_element =3D devm_kzalloc(dev, sizeof(*aplic_element), GFP_KERNEL); + if (!aplic_element) + return -ENOMEM; + + aplic_element->priv =3D priv; + list_add_tail(&aplic_element->list, &aplic_list); + } +#endif + return 0; } =20 diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-r= iscv-aplic-main.h index 78267ec58098..dc022e89bc97 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.h +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -28,6 +28,7 @@ struct aplic_priv { u32 gsi_base; u32 nr_irqs; u32 nr_idcs; + u32 id; void __iomem *regs; struct aplic_msicfg msicfg; }; diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-ri= scv-aplic-msi.c index 086d00e0429e..433ab2f270d9 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -178,6 +178,7 @@ static void aplic_msi_write_msg(struct msi_desc *desc, = struct msi_msg *msg) int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; + struct irq_domain *msi_domain; struct irq_domain *irqdomain; struct aplic_priv *priv; struct aplic_msicfg *mc; @@ -261,8 +262,14 @@ int aplic_msi_setup(struct device *dev, void __iomem *= regs) * IMSIC and the IMSIC MSI domains are created later through * the platform driver probing so we set it explicitly here. */ - if (is_of_node(dev->fwnode)) + if (is_of_node(dev->fwnode)) { of_msi_configure(dev, to_of_node(dev->fwnode)); + } else { + msi_domain =3D irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + if (msi_domain) + dev_set_msi_domain(dev, msi_domain); + } } =20 /* Create irq domain instance for the APLIC MSI-mode */ @@ -276,6 +283,7 @@ int aplic_msi_setup(struct device *dev, void __iomem *r= egs) return -ENOMEM; } =20 + dev_set_drvdata(dev, priv); /* Advertise the interrupt controller */ pa =3D priv->msicfg.base_ppn << APLIC_xMSICFGADDR_PPN_SHIFT; dev_info(dev, "%d interrupts forwared to MSI base %pa\n", --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A3F4C25B6F for ; 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Wed, 25 Oct 2023 13:25:41 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:41 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 16/21] irqchip: irq-sifive-plic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:39 +0530 Message-Id: <20231025202344.581132-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ACPI support in PLIC driver. In ACPI, IO devices use Global System Interrupts (GSI) which is a flat space split across multiple PLICs. So, the driver also need to provide the mapping from GSI to correct PLIC. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- arch/riscv/include/asm/irq.h | 6 ++ drivers/irqchip/irq-sifive-plic.c | 113 +++++++++++++++++++++++++----- 2 files changed, 101 insertions(+), 18 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 00eb8b0333c2..eff442766c87 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -28,6 +28,12 @@ struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi); static inline struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) { ret= urn NULL; } #endif =20 +#ifdef CONFIG_SIFIVE_PLIC +struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi); +#else +static inline struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) { retu= rn NULL; } +#endif + int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index c8f8a8cdcce1..9c61084a74eb 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ +#include #include #include #include @@ -70,6 +71,8 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; + int id; }; =20 struct plic_handler { @@ -316,6 +319,10 @@ static int plic_irq_domain_translate(struct irq_domain= *d, { struct plic_priv *priv =3D d->host_data; =20 + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >=3D priv->gsi_base) + fwspec->param[0] =3D fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); =20 @@ -417,17 +424,31 @@ static const struct of_device_id plic_match[] =3D { }; =20 static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, - u32 *nr_irqs, u32 *nr_contexts) + u32 *nr_irqs, u32 *nr_contexts, + u32 *gsi_base, u32 *id) { struct device *dev =3D &pdev->dev; + struct acpi_madt_plic *plic; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + plic =3D *(struct acpi_madt_plic **)dev_get_platdata(dev); + if (!plic) { + dev_err(dev, "PLIC platform data is NULL!\n"); + return -EINVAL; + } + + *nr_irqs =3D plic->num_irqs; + acpi_get_plic_nr_contexts(plic->id, nr_contexts); + if (WARN_ON(!*nr_contexts)) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + *gsi_base =3D plic->gsi_base; + *id =3D plic->id; + return 0; + } =20 rc =3D of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs); @@ -442,23 +463,28 @@ static int plic_parse_nr_irqs_and_contexts(struct pla= tform_device *pdev, return -EINVAL; } =20 + *gsi_base =3D 0; + *id =3D 0; + return 0; } =20 static int plic_parse_context_parent_hwirq(struct platform_device *pdev, - u32 context, u32 *parent_hwirq, + u32 context, u32 id, u32 *parent_hwirq, unsigned long *parent_hartid) { struct device *dev =3D &pdev->dev; struct of_phandle_args parent; int rc; =20 - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc =3D acpi_get_ext_intc_parent_hartid(id, context, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D RV_IRQ_EXT; + return 0; + } =20 rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); if (rc) @@ -472,6 +498,32 @@ static int plic_parse_context_parent_hwirq(struct plat= form_device *pdev, return 0; } =20 +#ifdef CONFIG_ACPI + +LIST_HEAD(plic_list); +struct plic_priv_list { + struct plic_priv *priv; + struct list_head list; +}; + +struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) +{ + struct plic_priv_list *plic_element; + struct list_head *i, *tmp; + + /* Find the PLIC that manages this GSI. */ + list_for_each_safe(i, tmp, &plic_list) { + plic_element =3D list_entry(i, struct plic_priv_list, list); + if (gsi >=3D plic_element->priv->gsi_base && + gsi <=3D (plic_element->priv->gsi_base + plic_element->priv->nr_irqs= )) + return plic_element->priv->dev->fwnode; + } + + return NULL; +} + +#endif + static int plic_probe(struct platform_device *pdev) { int rc, nr_contexts, nr_handlers =3D 0, i, cpu; @@ -483,7 +535,9 @@ static int plic_probe(struct platform_device *pdev) struct plic_priv *priv; irq_hw_number_t hwirq; struct resource *res; + int id, context_id; bool cpuhp_setup; + u32 gsi_base; =20 if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -510,19 +564,21 @@ static int plic_probe(struct platform_device *pdev) return -EIO; } =20 - rc =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + rc =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &gsi= _base, &id); if (rc) { dev_err(dev, "failed to parse irqs and contexts\n"); return rc; } priv->nr_irqs =3D nr_irqs; + priv->gsi_base =3D gsi_base; + priv->id =3D id; =20 priv->prio_save =3D devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); if (!priv->prio_save) return -ENOMEM; =20 for (i =3D 0; i < nr_contexts; i++) { - rc =3D plic_parse_context_parent_hwirq(pdev, i, + rc =3D plic_parse_context_parent_hwirq(pdev, i, priv->id, &parent_hwirq, &hartid); if (rc) { dev_warn(dev, "hwirq for context%d not found\n", i); @@ -574,13 +630,23 @@ static int plic_probe(struct platform_device *pdev) goto done; } =20 + if (is_of_node(dev->fwnode)) { + context_id =3D i; + } else { + rc =3D acpi_get_plic_context(priv->id, i, &context_id); + if (rc) { + dev_warn(dev, "invalid context id for context%d\n", i); + continue; + } + } + cpumask_set_cpu(cpu, &priv->lmask); handler->present =3D true; handler->hart_base =3D priv->regs + CONTEXT_BASE + - i * CONTEXT_SIZE; + context_id * CONTEXT_SIZE; raw_spin_lock_init(&handler->enable_lock); handler->enable_base =3D priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; + context_id * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 handler->enable_save =3D devm_kcalloc(dev, @@ -624,6 +690,17 @@ static int plic_probe(struct platform_device *pdev) register_syscore_ops(&plic_irq_syscore_ops); } =20 +#ifdef CONFIG_ACPI + struct plic_priv_list *plic_element; + + plic_element =3D devm_kzalloc(dev, sizeof(*plic_element), GFP_KERNEL); + if (!plic_element) + return -ENOMEM; + + plic_element->priv =3D priv; + list_add_tail(&plic_element->list, &plic_list); +#endif + dev_info(dev, "mapped %d interrupts with %d handlers for" " %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C499C0032E for ; Wed, 25 Oct 2023 20:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235041AbjJYU1G (ORCPT ); Wed, 25 Oct 2023 16:27:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234971AbjJYU0b (ORCPT ); Wed, 25 Oct 2023 16:26:31 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D9D5173A for ; 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 17/21] ACPI: bus: Add RINTC IRQ model for RISC-V Date: Thu, 26 Oct 2023 01:53:40 +0530 Message-Id: <20231025202344.581132-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index a4aa53b7e2bb..9eace6c7042e 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1158,6 +1158,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message =3D "LPIC"; break; + case ACPI_IRQ_MODEL_RINTC: + message =3D "RINTC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 4ad256a0039c..19c3dda9c2ed 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -95,6 +95,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_RINTC, ACPI_IRQ_MODEL_COUNT }; =20 --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7596C25B6F for ; Wed, 25 Oct 2023 20:27:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234693AbjJYU1T (ORCPT ); Wed, 25 Oct 2023 16:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343747AbjJYU0h (ORCPT ); Wed, 25 Oct 2023 16:26:37 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2760D1BEA for ; Wed, 25 Oct 2023 13:25:54 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6b36e1fcee9so130422b3a.3 for ; Wed, 25 Oct 2023 13:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265553; x=1698870353; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VwZ9IOYC0gRC/owt7RZ2EBdGuffYJiDuVuQ5+XRLwVw=; b=gni9otB/RxqkdQcBtDhkGtxYXI1WhO6/nBa5LuP10/nNencAljOkoEGMmIzHInY/ky oDlR4aIa6BOWPeVwvMeutGJ5V6ffVJCjq9yAVxUgQJ2NWKDBS7IHFKiQ+l6fFBvSh15A mZC/WjARqRxm2wTMlRiEvP5OHITXIqMDoeYIdAubOwiSoJbWpW6qqgDG3R3ijHPWgG3l RZ7TnvwKTmJTwhe02+58gFnl2LR1WgjHj440rGe69OikbaJsYYesrFvKharIMMus1Hog QqV5S9f6vTbimWXy/i5vLDf/0GQKcbKhCidzew7Kz1qBK6XcaGk99AbAHyc/PlHte0Xp EzEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265553; x=1698870353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VwZ9IOYC0gRC/owt7RZ2EBdGuffYJiDuVuQ5+XRLwVw=; b=eBWvE420c6c8QG4Cd4k2vme4j6DjYZ0aqHLwMEEaunIfFg3fqHMeAz5+xSjy65xEL8 IpGgJHZml1T7STdIYckmh2Zc7kpWC0g8zZN0LQp6BSOAlLBVwzjITTBvgk9Ly2XiZwOy 6QFh7xYOqkOnk5vcXB6zgGkIzu823S/7wWD9MqvLgmBrvn4G4uszp8/satEC6WMpnxr7 nyKWAMT0pSucM2X6SIDqL3Ep2nwZwoPTMoyJesj4cV+5DDSkd5hDsXP5W+v1gJnK/5yo djnNmn2tI51hm3Tsky8rkg9q0S2x+OXJiKkt/ztpjVGlvrD04mi9vph2n/f1VbRWoX7H 9CMg== X-Gm-Message-State: AOJu0Yw4/0YiUeDBmfVcje2UwgvzhSIyqI/ia/yBn/tALSkiRoz5SuXi mMc0QngFXPIBH2fFhLCtneIlLw== X-Google-Smtp-Source: AGHT+IHkn2z1G+Hl0DvKFF4S04ijeypy9mwQD0HYMK+syY66BONzs/0zW1LpSVQhK3aml5xBfnLnBg== X-Received: by 2002:a05:6a00:17a1:b0:6be:265:1bf6 with SMTP id s33-20020a056a0017a100b006be02651bf6mr14834736pfg.32.1698265553494; Wed, 25 Oct 2023 13:25:53 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:53 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 18/21] irqchip: riscv-intc: Set ACPI irqmodel Date: Thu, 26 Oct 2023 01:53:41 +0530 Message-Id: <20231025202344.581132-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" INTC being the root interrupt controller, set the ACPI irqmodel with callback function to get the GSI domain id. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-intc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index f3aaecde12dd..627723d72b01 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -273,6 +273,17 @@ int acpi_get_imsic_mmio_info(u32 index, struct resourc= e *res) return 0; } =20 +static struct fwnode_handle *riscv_get_gsi_domain_id(u32 gsi) +{ + struct fwnode_handle *gsi_fwnode =3D NULL; + + gsi_fwnode =3D aplic_get_gsi_domain_id(gsi); + if (!gsi_fwnode) + gsi_fwnode =3D plic_get_gsi_domain_id(gsi); + + return gsi_fwnode; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { @@ -318,6 +329,7 @@ static int __init riscv_intc_acpi_init(union acpi_subta= ble_headers *header, * unsupported. Once IMSIC is probed, MSI support will be set. */ pci_no_msi(); + acpi_set_irq_model(ACPI_IRQ_MODEL_RINTC, riscv_get_gsi_domain_id); return 0; } =20 --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42A5AC07545 for ; Wed, 25 Oct 2023 20:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234926AbjJYU1b (ORCPT ); Wed, 25 Oct 2023 16:27:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234913AbjJYU05 (ORCPT ); Wed, 25 Oct 2023 16:26:57 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1310110E3 for ; Wed, 25 Oct 2023 13:26:00 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6b5af4662b7so121689b3a.3 for ; Wed, 25 Oct 2023 13:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265559; x=1698870359; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6iZbx/IhbkeIBI8+FFzeu8yqPtMDZXtB3E1NSIPmMj8=; b=QEHaA3wcgswZPYvKtFvfe/69k4FY46ERnR8WMgXV1IMqoelcM4rz2XqdzfkYCJXcHA AZeXQv7QoKGxqZ8ztRXRHR9/meSUBV06R56NGZ0Bg4afony776+cS/GP0IMhMqcGOPeR BXmQXbwU0ap+UQ2w4s/WYEtaHQZTbJ+E9qp0/JBGXAVRiliE31C9a2pEb9jGPqDb//5F i7Gi+IZmFLPOhb5//zueDpHn2Gg8GUHChn2TdeHDV+4lyzpfvEf+quAO5gN25dyGVvVN XDNQQ+hvzvrwbpVPDQpk/iwr8m3MuhroNohrJ9lv6idIL4D5Op4XIlq/P3lu0wHBCkvV CU2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265559; x=1698870359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6iZbx/IhbkeIBI8+FFzeu8yqPtMDZXtB3E1NSIPmMj8=; b=B6PxOIRlnhcYk7q0KGVtSPsjzwcohCKidUougLWrkkCzT82CJpyeWJIt4ODjtIV7iP bsMgsbAAqjeUYWWw9uTd+WMY+7+04xnDVvdCF04bIhv3Nm/6lPRKrj5UtgT1OiNRSy5q oRVJ615CR0FAemXGhdwzMZfdak3hqiFoI3cyvxMcg5hm/SrK/maQZJlcTSgkBZMQsKOp 5c75ifU+b8/Wx5V0MmxSOcOsd5+mGxbNRkLqWE4P5+ATSztDb24SF1govaYC8DCUQBsB K1LVWpjrGA2SDdH1OrV1csle0INii57ZrdIdh/+PKUD287DPM6BdaChCMQFiSOs6mj7D NT2g== X-Gm-Message-State: AOJu0YwKwrnHFTJjKhUGf+QwgKbn2dCOOEXqdLiZ/7hP3263TOm983rK t5UQ3Y8USTe9eXxjS5IKyu6ALg== X-Google-Smtp-Source: AGHT+IFsNPal98bQ9F5MiljlxhKf86YWd9QVm8kQWxT7ZeiK3cahwXFdqVcGHEG00PzdPooHKx2sEg== X-Received: by 2002:a05:6a00:1798:b0:6ad:535e:6ed9 with SMTP id s24-20020a056a00179800b006ad535e6ed9mr16898802pfg.16.1698265559236; Wed, 25 Oct 2023 13:25:59 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:25:58 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 19/21] ACPI: bus: Add acpi_riscv_init function Date: Thu, 26 Oct 2023 01:53:42 +0530 Message-Id: <20231025202344.581132-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new function for RISC-V to do any architecture specific initialization. This function will be used to create platform devices like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init(). Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 9eace6c7042e..f7ac0caf04cf 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1417,6 +1417,7 @@ static int __init acpi_init(void) acpi_hest_init(); acpi_ghes_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_scan_init(); acpi_ec_init(); acpi_debugfs_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index f80b3da230e9..c4d679b1359e 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o irq.o +obj-y +=3D rhct.o irq.o init.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..b5807bbdb171 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 19c3dda9c2ed..c408070ac52e 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1527,6 +1527,12 @@ void acpi_arm_init(void); static inline void acpi_arm_init(void) { } #endif =20 +#ifdef CONFIG_RISCV +void acpi_riscv_init(void); +#else +static inline void acpi_riscv_init(void) { } +#endif + #ifdef CONFIG_ACPI_PCC void acpi_init_pcc(void); #else --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5752EC07545 for ; Wed, 25 Oct 2023 20:27:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234986AbjJYU1l (ORCPT ); Wed, 25 Oct 2023 16:27:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343976AbjJYU1G (ORCPT ); Wed, 25 Oct 2023 16:27:06 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 896661FCF for ; Wed, 25 Oct 2023 13:26:05 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-5a9d8f4388bso150872a12.3 for ; Wed, 25 Oct 2023 13:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698265565; x=1698870365; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YyAbjmaR4eN/4ltFJMCVbHeHJN24CQKSdc3guUQ+sXY=; b=lYxzdUsuOneYhoIV+rYgVVKZNSp0/KjI1w4hVj4ZjBNi+d684vIjZpU3C5bvKho2ua T2HrWtolaPG2TtCyFcRW3Xxn5fhO+hrUq0ptTInqJZpUTl6SEfVKEY0lCWGHetvIItds a1q4/Rd9BDYEV60OZ/wnKfgr2DV0HhRXr7hQWLRB7a4JI6UCSb1IEnbVRoCK6N5+zJQ0 E0xjWFarsTv4yN7dEsRjvdFs32Fj+9KZwuRWlZfe+pfoND04lmh6m1gf2zVvL+qSKrgH Al57+cknEsACPvo1q0XjaTcQjPfchYsjS+zI9JL+wL2NK2BykB3W+pb5SlOr+1hLhTKX nSSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698265565; x=1698870365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YyAbjmaR4eN/4ltFJMCVbHeHJN24CQKSdc3guUQ+sXY=; b=M80zHqiyQtw18LYYweoU9J41uRxTAjv9DOUW0UzfJjmXk7vzw5xhWptFa3MhvFrxyL PHs4u8JQLKp0QAIEkwkxR3j0N5iTUXsxKWhY1/Mx89WqQDUrHXcdTwf4YQByNkjSZO8G hKICZuRpIZHHrNeDr3D9yBIWfB29X9SUJuASTFblPPrde0XgE3Vt1DLkoBUGT/7c/vMg FPkNUP2UIAMvRn2EcQcVsJefrFQJlYwMo1MwEMVlKE+NKp+Xka3uqyHmpRvW1858231e 21Eb7vVzFsYhC//KDzmxSd6vD2u5ah2AyblrfucXErIqgcOx55JPMmODoCSE81Be59MP rCMw== X-Gm-Message-State: AOJu0YxCqeAWk+wVeAL7t5ItYEBwzuNoRh8bVCXj3+LEIJ1wJXHS582L qu6I6sN2SS/QQdOycpDqbIRjtA== X-Google-Smtp-Source: AGHT+IF7LV+DTM8Xp2zCb8vMCjjf9RgtWialAHShVkTza7omnaz58BwRnPvcOqBLoChX7glmevCqxQ== X-Received: by 2002:a05:6a20:3d13:b0:16b:8132:b547 with SMTP id y19-20020a056a203d1300b0016b8132b547mr8489178pzi.4.1698265564985; Wed, 25 Oct 2023 13:26:04 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:26:04 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 20/21] ACPI: RISC-V: Create APLIC platform device Date: Thu, 26 Oct 2023 01:53:43 +0530 Message-Id: <20231025202344.581132-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since APLIC needs to be a platform device, probe the MADT and create platform devices for each APLIC in the system. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 2 ++ drivers/acpi/riscv/init.h | 5 +++ drivers/acpi/riscv/irq.c | 74 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index b5807bbdb171..e7eff7ab1474 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ =20 #include +#include "init.h" =20 void __init acpi_riscv_init(void) { + riscv_acpi_aplic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..17bcf0baaadb --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_imsic_platform_init(void); +void __init riscv_acpi_aplic_platform_init(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 36e0525b3235..fbccecdcbf8b 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -6,6 +6,8 @@ */ =20 #include +#include +#include #include =20 static int irqchip_cmp_func(const void *in0, const void *in1) @@ -30,3 +32,75 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap= _head, int nr) return; sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); } + +static int __init irqchip_add_platform_device(char *irqchip_name, u32 irqc= hip_id, + resource_size_t iomem_res_start, + resource_size_t iomem_res_size, + union acpi_subtable_headers *header) +{ + struct platform_device *pdev; + struct fwnode_handle *fn; + struct resource *res; + int ret; + + fn =3D irq_domain_alloc_named_id_fwnode(irqchip_name, irqchip_id); + if (!fn) + return -ENOMEM; + + pdev =3D platform_device_alloc(irqchip_name, irqchip_id); + if (!pdev) { + irq_domain_free_fwnode(fn); + return -ENOMEM; + } + + res =3D kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return -ENOMEM; + } + + res->start =3D iomem_res_start; + res->end =3D res->start + iomem_res_size - 1; + res->flags =3D IORESOURCE_MEM; + ret =3D platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + /* + * Add copy of aplic pointer so that platform driver get aplic details. + */ + ret =3D platform_device_add_data(pdev, &header, sizeof(header)); + if (ret) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return ret; + } + + pdev->dev.fwnode =3D fn; + ret =3D platform_device_add(pdev); + if (ret) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return ret; + } + + return 0; +} + +static int __init aplic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic =3D (struct acpi_madt_aplic *)header; + + return irqchip_add_platform_device("riscv-aplic", aplic->id, aplic->base_= addr, + aplic->size, header); +} + +void __init riscv_acpi_aplic_platform_init(void) +{ + acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0); +} --=20 2.39.2 From nobody Wed Dec 17 11:34:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C625C25B6B for ; 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Wed, 25 Oct 2023 13:26:10 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y3-20020aa79423000000b006b84ed9371esm10079590pfo.177.2023.10.25.13.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:26:10 -0700 (PDT) From: Sunil V L To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 21/21] ACPI: RISC-V: Create PLIC platform device Date: Thu, 26 Oct 2023 01:53:44 +0530 Message-Id: <20231025202344.581132-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since PLIC needs to be a platform device, probe the MADT and create platform devices for each PLIC in the system. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irq.c | 14 ++++++++++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index e7eff7ab1474..c6fd4097e8ae 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -11,4 +11,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_aplic_platform_init(); + riscv_acpi_plic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index 17bcf0baaadb..b4b305d83b3a 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -3,3 +3,4 @@ =20 void __init riscv_acpi_imsic_platform_init(void); void __init riscv_acpi_aplic_platform_init(void); +void __init riscv_acpi_plic_platform_init(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index fbccecdcbf8b..90b0738e2b9f 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -104,3 +104,17 @@ void __init riscv_acpi_aplic_platform_init(void) { acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0); } + +static int __init plic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_plic *plic =3D (struct acpi_madt_plic *)header; + + return irqchip_add_platform_device("riscv-plic", plic->id, plic->base_add= r, + plic->size, header); +} + +void __init riscv_acpi_plic_platform_init(void) +{ + acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, plic_parse_madt, 0); +} --=20 2.39.2