From nobody Wed Dec 17 11:37:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 096ACC0032E for ; Wed, 25 Oct 2023 14:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344944AbjJYO2u (ORCPT ); Wed, 25 Oct 2023 10:28:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344931AbjJYO2o (ORCPT ); Wed, 25 Oct 2023 10:28:44 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D1C819D for ; Wed, 25 Oct 2023 07:28:42 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6bd96cfb99cso4772858b3a.2 for ; Wed, 25 Oct 2023 07:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698244121; x=1698848921; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SYhetJOGeGWONv0pBZCT4Mywf3EBvVtv+lOqGOUogJM=; b=mCzYS6nDySUvdJr17CiMC67ONyFIfKc1V5K91Ov1W62LK4H8TQYXMePBuad7GtJg8b Zz4XbiMb/+jWfcwqiBFhPNuzIH5F2ycKnO5Tv/xhu1nSCPyZj/nPuOPOvnX4AuNyHAZ0 eJiGEY7Q43B+GIPYD+a4Dqt+4i6bHsGxxVuEFOydjy83bPdJYB30sXDpatFNNduYBO2k 5T+b3v4/kJEHvPLFDB6BbB7SkZNDpxvomge/NhqDA8vjrEdMvZNspz3DWef8XHqRyo7v mA+5B7tJ9fsPUrdVeJj02nAvYPRJfna8ZMv6jChb355PLdMf77ET6Ebg7dqV67dMbcPk jxcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698244121; x=1698848921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SYhetJOGeGWONv0pBZCT4Mywf3EBvVtv+lOqGOUogJM=; b=T2ockJrsBGlYacOQzoUAZw+Iu3IYsRiVdjImO8tR5obNkQgDd+jBizXQIgGyhk33jy m+pA+ZBcVUEbGTuPwfZ+Ol9JJ2N0U89z1I8lffOlUdM5jSDjDp4+Mccgk6y8FvIukQe/ bmZuTogfhUoCX4rj6qrwl9239J15omn5eqhlMQDo7S4dHw+s1sGGPjImh9CoskMqt0BY S2yJ+MM/VsaQwpvDRZ7iIZpAM7AsAJg/L3FGCbjLRuKHpMAuaFDPunpEddoowXA4IbjL QwAQa7UkLfq9z3LwzINRzKUVeOEHyIniyq7Mriu7YiMm8SJtqk/5m8OTAPJtq5rnr62g fDGw== X-Gm-Message-State: AOJu0Yzf7P9u47D9hLFDP9pK4MMZb+5ufQ3cpqH+mK6gN9v3wWrl+68i WNvwjRNVpSfJ658GETINQZJxag== X-Google-Smtp-Source: AGHT+IFQNbBr+sMT3u5z/l+o0iF+ppZGPFxjQxnFACN4M50PeyfMhxm13pEjMBXrYf9gZntSp2P55w== X-Received: by 2002:a05:6a00:985:b0:68e:417c:ed5c with SMTP id u5-20020a056a00098500b0068e417ced5cmr14915842pfg.32.1698244121321; Wed, 25 Oct 2023 07:28:41 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id g2-20020aa796a2000000b0068ff6d21563sm9817411pfk.148.2023.10.25.07.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 07:28:40 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand Cc: Conor Dooley , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Date: Wed, 25 Oct 2023 19:58:18 +0530 Message-Id: <20231025142820.390238-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025142820.390238-1-apatel@ventanamicro.com> References: <20231025142820.390238-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails for HARTs disabled in the DT. This results in the following warning thrown by the RISC-V INTC driver for the E-core on SiFive boards: [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt= -controller The riscv_of_parent_hartid() is only expected to read the hartid from the DT so we should directly call of_get_cpu_hwid() instead of calling riscv_of_processor_hartid(). Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c17dacb1141c..157ace8b262c 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct dev= ice_node *node, unsigned lo */ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { - int rc; - for (; node; node =3D node->parent) { if (of_device_is_compatible(node, "riscv")) { - rc =3D riscv_of_processor_hartid(node, hartid); - if (!rc) - return 0; + *hartid =3D (unsigned long)of_get_cpu_hwid(node, 0); + if (*hartid =3D=3D ~0UL) { + pr_warn("Found CPU without hart ID\n"); + return -ENODEV; + } + return 0; } } =20 --=20 2.34.1 From nobody Wed Dec 17 11:37:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D57EEC0032E for ; Wed, 25 Oct 2023 14:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344945AbjJYO3N (ORCPT ); Wed, 25 Oct 2023 10:29:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344943AbjJYO2u (ORCPT ); Wed, 25 Oct 2023 10:28:50 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F51A99 for ; Wed, 25 Oct 2023 07:28:48 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6be0277c05bso4686986b3a.0 for ; Wed, 25 Oct 2023 07:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698244128; x=1698848928; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7KBK3NZC+n7aQ9gEOFAwoNpYjPv+cjuqYwdG+XSaoH8=; b=BavMbCpphcFIUwz1RVi2TDeIwmJeuAt3HhJZH3vBAq877YqpibcGcwpWFsGDJBQQGI gp3odMjce4EgaoPYz4DWfexUHOewu9FWRSHHFAMJeinPl/L55LCFRK8oY47fmeIBpPGN bCFdWVaSnE4pldMYk0H1DlZB7s1aBApXdAHC6vYcL5Ww5dP+FiNl2IdwJVsOmekDkpOO lXszh6cM//cRWcTI5olxcQCKqS6UWAd+LVNi23ys8DVrOL5Hfz+kBSL1DJPOUVY1JsFO g9ap90ecc3J9Z5lOe4US5CiNgdyki/Z1sQ6k8bSpvtVu2+EzND/SJXXcPR9bdZeq/8me D+Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698244128; x=1698848928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7KBK3NZC+n7aQ9gEOFAwoNpYjPv+cjuqYwdG+XSaoH8=; b=e+BJrFAVjxefQz6ZEIKHMPaCAOLxmZzhEscTJY+Ckvn6ZN1L36FUTczYHAUz+7ec7K 7NaWA4ujLKktWGQ7ROC9Gwv2QkDfZlcPEq5tS45RdQkl2paSykS+IinE8YrxyHlZCMmx dQY6ee4QQgvXB9RsNfGV329FMXnrtqn+heNBNmFvwGrxYd27Zasd2Zx6jxbwF/JwlxeY GrbkqkO3VziQM6PMTbeNNluW1k0ae1F9gYmRbhl4nfJGAWk4kQzvmAH1L2hIZRRp0fj6 lt34RqczftYjS1mvrmnpz6g9PMC2pT9rPaKZLAYCs6jPyx4mJu4eImsJ3N90FnJ0AtjA vmvQ== X-Gm-Message-State: AOJu0YxIHhjLImLykWBEhZVKL2KrjEsjTZqBG0HWHJrEBR9hUJLB30zn 9xz1TLRREW0DiIgecT7YAUUpSw== X-Google-Smtp-Source: AGHT+IHf5xLTf1KfVLoRMBRais+yDi8I/s1NVEGKVd+AFMTt9BY+nGX8/ulLd9cgkH/b1pX/mifhiw== X-Received: by 2002:a05:6a00:2308:b0:6be:367a:2a71 with SMTP id h8-20020a056a00230800b006be367a2a71mr15594745pfh.16.1698244127853; Wed, 25 Oct 2023 07:28:47 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id g2-20020aa796a2000000b0068ff6d21563sm9817411pfk.148.2023.10.25.07.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 07:28:47 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand Cc: Conor Dooley , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Rob Herring Subject: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent Date: Wed, 25 Oct 2023 19:58:19 +0530 Message-Id: <20231025142820.390238-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025142820.390238-1-apatel@ventanamicro.com> References: <20231025142820.390238-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This allows fw_devlink to create device links between consumers of a MSI and the supplier of the MSI. Signed-off-by: Anup Patel Acked-by: Rob Herring Reviewed-by: Saravana Kannan --- drivers/of/property.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c index cf8dacf3e3b8..afdaefbd03f6 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1267,6 +1267,7 @@ DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells") DEFINE_SIMPLE_PROP(leds, "leds", NULL) DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) DEFINE_SIMPLE_PROP(panel, "panel", NULL) +DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells") DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") =20 @@ -1356,6 +1357,7 @@ static const struct supplier_bindings of_supplier_bin= dings[] =3D { { .parse_prop =3D parse_leds, }, { .parse_prop =3D parse_backlight, }, { .parse_prop =3D parse_panel, }, + { .parse_prop =3D parse_msi_parent, }, { .parse_prop =3D parse_gpio_compat, }, { .parse_prop =3D parse_interrupts, }, { .parse_prop =3D parse_regulators, }, --=20 2.34.1 From nobody Wed Dec 17 11:37:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1AA9C25B70 for ; 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Wed, 25 Oct 2023 07:28:53 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id g2-20020aa796a2000000b0068ff6d21563sm9817411pfk.148.2023.10.25.07.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 07:28:53 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand Cc: Conor Dooley , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Date: Wed, 25 Oct 2023 19:58:20 +0530 Message-Id: <20231025142820.390238-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025142820.390238-1-apatel@ventanamicro.com> References: <20231025142820.390238-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On multi-socket systems, we will have a separate PLIC in each socket so we should register syscore operation only once for multi-socket systems. Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hi= bernation") Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index e1484905b7bd..5b7bc4fd9517 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -532,17 +532,18 @@ static int __init __plic_init(struct device_node *nod= e, } =20 /* - * We can have multiple PLIC instances so setup cpuhp state only - * when context handler for current/boot CPU is present. + * We can have multiple PLIC instances so setup cpuhp state + * and register syscore operations only when context handler + * for current/boot CPU is present. */ handler =3D this_cpu_ptr(&plic_handlers); if (handler->present && !plic_cpuhp_setup_done) { cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); + register_syscore_ops(&plic_irq_syscore_ops); plic_cpuhp_setup_done =3D true; } - register_syscore_ops(&plic_irq_syscore_ops); =20 pr_info("%pOFP: mapped %d interrupts with %d handlers for" " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); --=20 2.34.1