From nobody Thu Dec 18 05:19:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F698C07545 for ; Wed, 25 Oct 2023 13:34:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344678AbjJYNeu (ORCPT ); Wed, 25 Oct 2023 09:34:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344572AbjJYNel (ORCPT ); Wed, 25 Oct 2023 09:34:41 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 562A7B4; Wed, 25 Oct 2023 06:34:37 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39PBuMDh032482; Wed, 25 Oct 2023 13:34:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=Im47LQ4bagq4vg44EgIKhsdexxEEJQC1O75RgqyRoFw=; b=Y5bm1um/2l9pLs8ZYnX9BfszdqGgvVUXZb6BEnH18BA3axmiFmarmHJMKQQHrCc8/SJV dk0sJ/DaWMNuJLyqCS5UwKfmgTf/WSHBMuoQemxdGUgOunAmx+9Ifz70KUz+NiBtJTbz qzOSw7njWnk+72c7l5fxXFv+z2KElX8YxBglcjoqTtzA0+Pk/I/URQtEQ0EValL9Vbk3 4E5I6TOmvdfkxrE79NpP2SE02D9JePa+QVXaUh6sk6FuFFT4ULjkNsrqWSs78gRjehaj U58OHW3St1gY1AR6A80o4/t/DETasPTBWt5ut95Y59JLE6ojSE/bJQRcLAdGggiA5EYu zg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3txumsh0xw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 13:34:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39PDYBsr031954 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 13:34:11 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 06:34:05 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , Sibi Sankar Subject: [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Date: Wed, 25 Oct 2023 19:03:17 +0530 Message-ID: <20231025133320.4720-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231025133320.4720-1-quic_sibis@quicinc.com> References: <20231025133320.4720-1-quic_sibis@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0z5nuz40-5yVzi0kUt2s9HFWyg7AdbZ0 X-Proofpoint-ORIG-GUID: 0z5nuz40-5yVzi0kUt2s9HFWyg7AdbZ0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_02,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rajendra Nayak Add device tree bindings for global clock controller on SC8380XP SoCs. Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sc8380xp-gcc.yaml | 72 +++ include/dt-bindings/clock/qcom,sc8380xp-gcc.h | 485 ++++++++++++++++++ 2 files changed, 557 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8380xp-g= cc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8380xp-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml new file mode 100644 index 000000000000..8b231e1d25ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8380xp-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC8380XP + +maintainers: + - Rajendra Nayak + +description: | + Qualcomm global clock control module provides the clocks, resets and pow= er + domains on SC8380XP + + See also:: include/dt-bindings/clock/qcom,sc8380xp-gcc.h + +properties: + compatible: + const: qcom,sc8380xp-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIe 3 pipe clock + - description: PCIe 4 pipe clock + - description: PCIe 5 pipe clock + - description: PCIe 6a pipe clock + - description: PCIe 6b pipe clock + - description: USB QMP Phy 0 clock source + - description: USB QMP Phy 1 clock source + - description: USB QMP Phy 2 clock source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible =3D "qcom,sc8380xp-gcc"; + reg =3D <0x00100000 0x200000>; + clocks =3D <&bi_tcxo_div2>, + <&sleep_clk>, + <&pcie3_phy>, + <&pcie4_phy>, + <&pcie5_phy>, + <&pcie6a_phy>, + <&pcie6b_phy>, + <&usb_1_ss0_qmpphy 0>, + <&usb_1_ss1_qmpphy 1>, + <&usb_1_ss2_qmpphy 2>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sc8380xp-gcc.h b/include/dt-bin= dings/clock/qcom,sc8380xp-gcc.h new file mode 100644 index 000000000000..c4cf449accf8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8380xp-gcc.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8380XP_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC8380XP_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0 +#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3 +#define GCC_AGGRE_USB3_MP_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 +#define GCC_AGGRE_USB3_TERT_AXI_CLK 7 +#define GCC_AGGRE_USB4_0_AXI_CLK 8 +#define GCC_AGGRE_USB4_1_AXI_CLK 9 +#define GCC_AGGRE_USB4_2_AXI_CLK 10 +#define GCC_AGGRE_USB_NOC_AXI_CLK 11 +#define GCC_AV1E_AHB_CLK 12 +#define GCC_AV1E_AXI_CLK 13 +#define GCC_AV1E_XO_CLK 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CAMERA_AHB_CLK 16 +#define GCC_CAMERA_HF_AXI_CLK 17 +#define GCC_CAMERA_SF_AXI_CLK 18 +#define GCC_CAMERA_XO_CLK 19 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20 +#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21 +#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26 +#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27 +#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28 +#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29 +#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30 +#define GCC_CNOC_PCIE1_TUNNEL_CLK 31 +#define GCC_CNOC_PCIE2_TUNNEL_CLK 32 +#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33 +#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34 +#define GCC_CNOC_PCIE_TUNNEL_CLK 35 +#define GCC_DDRSS_GPU_AXI_CLK 36 +#define GCC_DISP_AHB_CLK 37 +#define GCC_DISP_HF_AXI_CLK 38 +#define GCC_DISP_XO_CLK 39 +#define GCC_GP1_CLK 40 +#define GCC_GP1_CLK_SRC 41 +#define GCC_GP2_CLK 42 +#define GCC_GP2_CLK_SRC 43 +#define GCC_GP3_CLK 44 +#define GCC_GP3_CLK_SRC 45 +#define GCC_GPLL0 46 +#define GCC_GPLL0_OUT_EVEN 47 +#define GCC_GPLL4 48 +#define GCC_GPLL7 49 +#define GCC_GPLL8 50 +#define GCC_GPLL9 51 +#define GCC_GPU_CFG_AHB_CLK 52 +#define GCC_GPU_GPLL0_CPH_CLK_SRC 53 +#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54 +#define GCC_GPU_MEMNOC_GFX_CLK 55 +#define GCC_GPU_SNOC_DVM_GFX_CLK 56 +#define GCC_PCIE0_PHY_RCHNG_CLK 57 +#define GCC_PCIE1_PHY_RCHNG_CLK 58 +#define GCC_PCIE2_PHY_RCHNG_CLK 59 +#define GCC_PCIE_0_AUX_CLK 60 +#define GCC_PCIE_0_AUX_CLK_SRC 61 +#define GCC_PCIE_0_CFG_AHB_CLK 62 +#define GCC_PCIE_0_MSTR_AXI_CLK 63 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64 +#define GCC_PCIE_0_PIPE_CLK 65 +#define GCC_PCIE_0_SLV_AXI_CLK 66 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67 +#define GCC_PCIE_1_AUX_CLK 68 +#define GCC_PCIE_1_AUX_CLK_SRC 69 +#define GCC_PCIE_1_CFG_AHB_CLK 70 +#define GCC_PCIE_1_MSTR_AXI_CLK 71 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72 +#define GCC_PCIE_1_PIPE_CLK 73 +#define GCC_PCIE_1_SLV_AXI_CLK 74 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75 +#define GCC_PCIE_2_AUX_CLK 76 +#define GCC_PCIE_2_AUX_CLK_SRC 77 +#define GCC_PCIE_2_CFG_AHB_CLK 78 +#define GCC_PCIE_2_MSTR_AXI_CLK 79 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80 +#define GCC_PCIE_2_PIPE_CLK 81 +#define GCC_PCIE_2_SLV_AXI_CLK 82 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83 +#define GCC_PCIE_3_AUX_CLK 84 +#define GCC_PCIE_3_AUX_CLK_SRC 85 +#define GCC_PCIE_3_CFG_AHB_CLK 86 +#define GCC_PCIE_3_MSTR_AXI_CLK 87 +#define GCC_PCIE_3_PHY_AUX_CLK 88 +#define GCC_PCIE_3_PHY_RCHNG_CLK 89 +#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90 +#define GCC_PCIE_3_PIPE_CLK 91 +#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92 +#define GCC_PCIE_3_PIPEDIV2_CLK 93 +#define GCC_PCIE_3_SLV_AXI_CLK 94 +#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95 +#define GCC_PCIE_4_AUX_CLK 96 +#define GCC_PCIE_4_AUX_CLK_SRC 97 +#define GCC_PCIE_4_CFG_AHB_CLK 98 +#define GCC_PCIE_4_MSTR_AXI_CLK 99 +#define GCC_PCIE_4_PHY_RCHNG_CLK 100 +#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101 +#define GCC_PCIE_4_PIPE_CLK 102 +#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103 +#define GCC_PCIE_4_PIPEDIV2_CLK 104 +#define GCC_PCIE_4_SLV_AXI_CLK 105 +#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106 +#define GCC_PCIE_5_AUX_CLK 107 +#define GCC_PCIE_5_AUX_CLK_SRC 108 +#define GCC_PCIE_5_CFG_AHB_CLK 109 +#define GCC_PCIE_5_MSTR_AXI_CLK 110 +#define GCC_PCIE_5_PHY_RCHNG_CLK 111 +#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112 +#define GCC_PCIE_5_PIPE_CLK 113 +#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114 +#define GCC_PCIE_5_PIPEDIV2_CLK 115 +#define GCC_PCIE_5_SLV_AXI_CLK 116 +#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117 +#define GCC_PCIE_6A_AUX_CLK 118 +#define GCC_PCIE_6A_AUX_CLK_SRC 119 +#define GCC_PCIE_6A_CFG_AHB_CLK 120 +#define GCC_PCIE_6A_MSTR_AXI_CLK 121 +#define GCC_PCIE_6A_PHY_AUX_CLK 122 +#define GCC_PCIE_6A_PHY_RCHNG_CLK 123 +#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124 +#define GCC_PCIE_6A_PIPE_CLK 125 +#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126 +#define GCC_PCIE_6A_PIPEDIV2_CLK 127 +#define GCC_PCIE_6A_SLV_AXI_CLK 128 +#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129 +#define GCC_PCIE_6B_AUX_CLK 130 +#define GCC_PCIE_6B_AUX_CLK_SRC 131 +#define GCC_PCIE_6B_CFG_AHB_CLK 132 +#define GCC_PCIE_6B_MSTR_AXI_CLK 133 +#define GCC_PCIE_6B_PHY_AUX_CLK 134 +#define GCC_PCIE_6B_PHY_RCHNG_CLK 135 +#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136 +#define GCC_PCIE_6B_PIPE_CLK 137 +#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138 +#define GCC_PCIE_6B_PIPEDIV2_CLK 139 +#define GCC_PCIE_6B_SLV_AXI_CLK 140 +#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141 +#define GCC_PCIE_RSCC_AHB_CLK 142 +#define GCC_PCIE_RSCC_XO_CLK 143 +#define GCC_PCIE_RSCC_XO_CLK_SRC 144 +#define GCC_PDM2_CLK 145 +#define GCC_PDM2_CLK_SRC 146 +#define GCC_PDM_AHB_CLK 147 +#define GCC_PDM_XO4_CLK 148 +#define GCC_QMIP_AV1E_AHB_CLK 149 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 151 +#define GCC_QMIP_DISP_AHB_CLK 152 +#define GCC_QMIP_GPU_AHB_CLK 153 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158 +#define GCC_QUPV3_WRAP0_CORE_CLK 159 +#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160 +#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161 +#define GCC_QUPV3_WRAP0_S0_CLK 162 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163 +#define GCC_QUPV3_WRAP0_S1_CLK 164 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165 +#define GCC_QUPV3_WRAP0_S2_CLK 166 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167 +#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168 +#define GCC_QUPV3_WRAP0_S3_CLK 169 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170 +#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171 +#define GCC_QUPV3_WRAP0_S4_CLK 172 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173 +#define GCC_QUPV3_WRAP0_S5_CLK 174 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175 +#define GCC_QUPV3_WRAP0_S6_CLK 176 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177 +#define GCC_QUPV3_WRAP0_S7_CLK 178 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180 +#define GCC_QUPV3_WRAP1_CORE_CLK 181 +#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182 +#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183 +#define GCC_QUPV3_WRAP1_S0_CLK 184 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185 +#define GCC_QUPV3_WRAP1_S1_CLK 186 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187 +#define GCC_QUPV3_WRAP1_S2_CLK 188 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189 +#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190 +#define GCC_QUPV3_WRAP1_S3_CLK 191 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192 +#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193 +#define GCC_QUPV3_WRAP1_S4_CLK 194 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195 +#define GCC_QUPV3_WRAP1_S5_CLK 196 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197 +#define GCC_QUPV3_WRAP1_S6_CLK 198 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199 +#define GCC_QUPV3_WRAP1_S7_CLK 200 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202 +#define GCC_QUPV3_WRAP2_CORE_CLK 203 +#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204 +#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205 +#define GCC_QUPV3_WRAP2_S0_CLK 206 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207 +#define GCC_QUPV3_WRAP2_S1_CLK 208 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209 +#define GCC_QUPV3_WRAP2_S2_CLK 210 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211 +#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212 +#define GCC_QUPV3_WRAP2_S3_CLK 213 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214 +#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215 +#define GCC_QUPV3_WRAP2_S4_CLK 216 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217 +#define GCC_QUPV3_WRAP2_S5_CLK 218 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219 +#define GCC_QUPV3_WRAP2_S6_CLK 220 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221 +#define GCC_QUPV3_WRAP2_S7_CLK 222 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229 +#define GCC_SDCC2_AHB_CLK 230 +#define GCC_SDCC2_APPS_CLK 231 +#define GCC_SDCC2_APPS_CLK_SRC 232 +#define GCC_SDCC4_AHB_CLK 233 +#define GCC_SDCC4_APPS_CLK 234 +#define GCC_SDCC4_APPS_CLK_SRC 235 +#define GCC_SYS_NOC_USB_AXI_CLK 236 +#define GCC_UFS_PHY_AHB_CLK 237 +#define GCC_UFS_PHY_AXI_CLK 238 +#define GCC_UFS_PHY_AXI_CLK_SRC 239 +#define GCC_UFS_PHY_ICE_CORE_CLK 240 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241 +#define GCC_UFS_PHY_PHY_AUX_CLK 242 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248 +#define GCC_USB20_MASTER_CLK 249 +#define GCC_USB20_MASTER_CLK_SRC 250 +#define GCC_USB20_MOCK_UTMI_CLK 251 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 252 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253 +#define GCC_USB20_SLEEP_CLK 254 +#define GCC_USB30_MP_MASTER_CLK 255 +#define GCC_USB30_MP_MASTER_CLK_SRC 256 +#define GCC_USB30_MP_MOCK_UTMI_CLK 257 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258 +#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259 +#define GCC_USB30_MP_SLEEP_CLK 260 +#define GCC_USB30_PRIM_MASTER_CLK 261 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 262 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265 +#define GCC_USB30_PRIM_SLEEP_CLK 266 +#define GCC_USB30_SEC_MASTER_CLK 267 +#define GCC_USB30_SEC_MASTER_CLK_SRC 268 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 269 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271 +#define GCC_USB30_SEC_SLEEP_CLK 272 +#define GCC_USB30_TERT_MASTER_CLK 273 +#define GCC_USB30_TERT_MASTER_CLK_SRC 274 +#define GCC_USB30_TERT_MOCK_UTMI_CLK 275 +#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276 +#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277 +#define GCC_USB30_TERT_SLEEP_CLK 278 +#define GCC_USB3_MP_PHY_AUX_CLK 279 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 281 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 282 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 283 +#define GCC_USB3_PRIM_PHY_AUX_CLK 284 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 287 +#define GCC_USB3_SEC_PHY_AUX_CLK 288 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290 +#define GCC_USB3_SEC_PHY_PIPE_CLK 291 +#define GCC_USB3_TERT_PHY_AUX_CLK 292 +#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293 +#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294 +#define GCC_USB3_TERT_PHY_PIPE_CLK 295 +#define GCC_USB4_0_CFG_AHB_CLK 296 +#define GCC_USB4_0_DP0_CLK 297 +#define GCC_USB4_0_DP1_CLK 298 +#define GCC_USB4_0_MASTER_CLK 299 +#define GCC_USB4_0_MASTER_CLK_SRC 300 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303 +#define GCC_USB4_0_PHY_RX0_CLK 304 +#define GCC_USB4_0_PHY_RX1_CLK 305 +#define GCC_USB4_0_PHY_USB_PIPE_CLK 306 +#define GCC_USB4_0_SB_IF_CLK 307 +#define GCC_USB4_0_SB_IF_CLK_SRC 308 +#define GCC_USB4_0_SYS_CLK 309 +#define GCC_USB4_0_TMU_CLK 310 +#define GCC_USB4_0_TMU_CLK_SRC 311 +#define GCC_USB4_1_CFG_AHB_CLK 312 +#define GCC_USB4_1_DP0_CLK 313 +#define GCC_USB4_1_DP1_CLK 314 +#define GCC_USB4_1_MASTER_CLK 315 +#define GCC_USB4_1_MASTER_CLK_SRC 316 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319 +#define GCC_USB4_1_PHY_RX0_CLK 320 +#define GCC_USB4_1_PHY_RX1_CLK 321 +#define GCC_USB4_1_PHY_USB_PIPE_CLK 322 +#define GCC_USB4_1_SB_IF_CLK 323 +#define GCC_USB4_1_SB_IF_CLK_SRC 324 +#define GCC_USB4_1_SYS_CLK 325 +#define GCC_USB4_1_TMU_CLK 326 +#define GCC_USB4_1_TMU_CLK_SRC 327 +#define GCC_USB4_2_CFG_AHB_CLK 328 +#define GCC_USB4_2_DP0_CLK 329 +#define GCC_USB4_2_DP1_CLK 330 +#define GCC_USB4_2_MASTER_CLK 331 +#define GCC_USB4_2_MASTER_CLK_SRC 332 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335 +#define GCC_USB4_2_PHY_RX0_CLK 336 +#define GCC_USB4_2_PHY_RX1_CLK 337 +#define GCC_USB4_2_PHY_USB_PIPE_CLK 338 +#define GCC_USB4_2_SB_IF_CLK 339 +#define GCC_USB4_2_SB_IF_CLK_SRC 340 +#define GCC_USB4_2_SYS_CLK 341 +#define GCC_USB4_2_TMU_CLK 342 +#define GCC_USB4_2_TMU_CLK_SRC 343 +#define GCC_VIDEO_AHB_CLK 344 +#define GCC_VIDEO_AXI0_CLK 345 +#define GCC_VIDEO_AXI1_CLK 346 +#define GCC_VIDEO_XO_CLK 347 +#define GCC_PCIE_3_PIPE_CLK_SRC 348 +#define GCC_PCIE_4_PIPE_CLK_SRC 349 +#define GCC_PCIE_5_PIPE_CLK_SRC 350 +#define GCC_PCIE_6A_PIPE_CLK_SRC 351 +#define GCC_PCIE_6B_PIPE_CLK_SRC 352 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 +#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 + +/* GCC power domains */ +#define GCC_PCIE_0_TUNNEL_GDSC 0 +#define GCC_PCIE_1_TUNNEL_GDSC 1 +#define GCC_PCIE_2_TUNNEL_GDSC 2 +#define GCC_PCIE_3_GDSC 3 +#define GCC_PCIE_3_PHY_GDSC 4 +#define GCC_PCIE_4_GDSC 5 +#define GCC_PCIE_4_PHY_GDSC 6 +#define GCC_PCIE_5_GDSC 7 +#define GCC_PCIE_5_PHY_GDSC 8 +#define GCC_PCIE_6_PHY_GDSC 9 +#define GCC_PCIE_6A_GDSC 10 +#define GCC_PCIE_6B_GDSC 11 +#define GCC_UFS_MEM_PHY_GDSC 12 +#define GCC_UFS_PHY_GDSC 13 +#define GCC_USB20_PRIM_GDSC 14 +#define GCC_USB30_MP_GDSC 15 +#define GCC_USB30_PRIM_GDSC 16 +#define GCC_USB30_SEC_GDSC 17 +#define GCC_USB30_TERT_GDSC 18 +#define GCC_USB3_MP_SS0_PHY_GDSC 19 +#define GCC_USB3_MP_SS1_PHY_GDSC 20 +#define GCC_USB4_0_GDSC 21 +#define GCC_USB4_1_GDSC 22 +#define GCC_USB4_2_GDSC 23 +#define GCC_USB_0_PHY_GDSC 24 +#define GCC_USB_1_PHY_GDSC 25 +#define GCC_USB_2_PHY_GDSC 26 + +/* GCC resets */ +#define GCC_AV1E_BCR 0 +#define GCC_CAMERA_BCR 1 +#define GCC_DISPLAY_BCR 2 +#define GCC_GPU_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_0_TUNNEL_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_1_TUNNEL_BCR 13 +#define GCC_PCIE_2_LINK_DOWN_BCR 14 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15 +#define GCC_PCIE_2_PHY_BCR 16 +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_PCIE_2_TUNNEL_BCR 18 +#define GCC_PCIE_3_BCR 19 +#define GCC_PCIE_3_LINK_DOWN_BCR 20 +#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21 +#define GCC_PCIE_3_PHY_BCR 22 +#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_4_BCR 24 +#define GCC_PCIE_4_LINK_DOWN_BCR 25 +#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26 +#define GCC_PCIE_4_PHY_BCR 27 +#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28 +#define GCC_PCIE_5_BCR 29 +#define GCC_PCIE_5_LINK_DOWN_BCR 30 +#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31 +#define GCC_PCIE_5_PHY_BCR 32 +#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33 +#define GCC_PCIE_6A_BCR 34 +#define GCC_PCIE_6A_LINK_DOWN_BCR 35 +#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36 +#define GCC_PCIE_6A_PHY_BCR 37 +#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38 +#define GCC_PCIE_6B_BCR 39 +#define GCC_PCIE_6B_LINK_DOWN_BCR 40 +#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41 +#define GCC_PCIE_6B_PHY_BCR 42 +#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43 +#define GCC_PCIE_PHY_BCR 44 +#define GCC_PCIE_PHY_CFG_AHB_BCR 45 +#define GCC_PCIE_PHY_COM_BCR 46 +#define GCC_PCIE_RSCC_BCR 47 +#define GCC_PDM_BCR 48 +#define GCC_QUPV3_WRAPPER_0_BCR 49 +#define GCC_QUPV3_WRAPPER_1_BCR 50 +#define GCC_QUPV3_WRAPPER_2_BCR 51 +#define GCC_QUSB2PHY_HS0_MP_BCR 52 +#define GCC_QUSB2PHY_HS1_MP_BCR 53 +#define GCC_QUSB2PHY_PRIM_BCR 54 +#define GCC_QUSB2PHY_SEC_BCR 55 +#define GCC_QUSB2PHY_TERT_BCR 56 +#define GCC_QUSB2PHY_USB20_HS_BCR 57 +#define GCC_SDCC2_BCR 58 +#define GCC_SDCC4_BCR 59 +#define GCC_UFS_PHY_BCR 60 +#define GCC_USB20_PRIM_BCR 61 +#define GCC_USB30_MP_BCR 62 +#define GCC_USB30_PRIM_BCR 63 +#define GCC_USB30_SEC_BCR 64 +#define GCC_USB30_TERT_BCR 65 +#define GCC_USB3_MP_SS0_PHY_BCR 66 +#define GCC_USB3_MP_SS1_PHY_BCR 67 +#define GCC_USB3_PHY_PRIM_BCR 68 +#define GCC_USB3_PHY_SEC_BCR 69 +#define GCC_USB3_PHY_TERT_BCR 70 +#define GCC_USB3_UNIPHY_MP0_BCR 71 +#define GCC_USB3_UNIPHY_MP1_BCR 72 +#define GCC_USB3PHY_PHY_PRIM_BCR 73 +#define GCC_USB3PHY_PHY_SEC_BCR 74 +#define GCC_USB3PHY_PHY_TERT_BCR 75 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 76 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 77 +#define GCC_USB4_0_BCR 78 +#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79 +#define GCC_USB4_1_DP0_PHY_SEC_BCR 80 +#define GCC_USB4_2_DP0_PHY_TERT_BCR 81 +#define GCC_USB4_1_BCR 82 +#define GCC_USB4_2_BCR 83 +#define GCC_USB_0_PHY_BCR 84 +#define GCC_USB_1_PHY_BCR 85 +#define GCC_USB_2_PHY_BCR 86 +#define GCC_VIDEO_BCR 87 +#endif --=20 2.17.1 From nobody Thu Dec 18 05:19:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12DFDC07545 for ; Wed, 25 Oct 2023 13:34:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id 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15.2.1118.39; Wed, 25 Oct 2023 06:34:11 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , Sibi Sankar Subject: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Date: Wed, 25 Oct 2023 19:03:18 +0530 Message-ID: <20231025133320.4720-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231025133320.4720-1-quic_sibis@quicinc.com> References: <20231025133320.4720-1-quic_sibis@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 53GTfYftGi93HOrfK7Vsso88WIOpsExh X-Proofpoint-ORIG-GUID: 53GTfYftGi93HOrfK7Vsso88WIOpsExh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_02,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rajendra Nayak Add support for the global clock controller found on SC8380XP based devices. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Rajendra Nayak Signed-off-by: Sibi Sankar --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++ 3 files changed, 6823 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426..013b3a1ad551 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -515,6 +515,16 @@ config SC_GCC_8280XP Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. =20 +config SC_GCC_8380XP + tristate "SC8380XP Global Clock Controller" + select QCOM_GDSC + depends on COMMON_CLK_QCOM + help + Support for the global clock controller on Qualcomm Technologies, Inc + SC8380XP devices. + Say Y if you want to use peripheral devices such as UART, SPI, I2C, + USB, UFS, SD/eMMC, PCIe, etc. + config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 17edd73f9839..11b1f79e15c5 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -77,6 +77,7 @@ obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) +=3D gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) +=3D gcc-sc8180x.o obj-$(CONFIG_SC_GCC_8280XP) +=3D gcc-sc8280xp.o +obj-$(CONFIG_SC_GCC_8380XP) +=3D gcc-sc8380xp.o obj-$(CONFIG_SC_GPUCC_7180) +=3D gpucc-sc7180.o obj-$(CONFIG_SC_GPUCC_7280) +=3D gpucc-sc7280.o obj-$(CONFIG_SC_GPUCC_8280XP) +=3D gpucc-sc8280xp.o diff --git a/drivers/clk/qcom/gcc-sc8380xp.c b/drivers/clk/qcom/gcc-sc8380x= p.c new file mode 100644 index 000000000000..48c50f9421c8 --- /dev/null +++ b/drivers/clk/qcom/gcc-sc8380xp.c @@ -0,0 +1,6812 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_PCIE_3_PIPE, + DT_PCIE_4_PIPE, + DT_PCIE_5_PIPE, + DT_PCIE_6A_PIPE, + DT_PCIE_6B_PIPE, + DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, + DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, + DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, +}; + +enum { + P_BI_TCXO, + P_GCC_GPLL0_OUT_EVEN, + P_GCC_GPLL0_OUT_MAIN, + P_GCC_GPLL4_OUT_MAIN, + P_GCC_GPLL7_OUT_MAIN, + P_GCC_GPLL8_OUT_MAIN, + P_GCC_GPLL9_OUT_MAIN, + P_SLEEP_CLK, + P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, + P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, + P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static struct clk_alpha_pll gcc_gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gcc_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll gcc_gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52030, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll7 =3D { + .offset =3D 0x7000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52030, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll7", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll8 =3D { + .offset =3D 0x8000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52030, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll8", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gcc_gpll9 =3D { + .offset =3D 0x9000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x52030, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpll9", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL8_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll8.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll7.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL7_OUT_MAIN, 2 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll7.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, + { P_GCC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_GPLL9_OUT_MAIN, 2 }, + { P_GCC_GPLL4_OUT_MAIN, 5 }, + { P_GCC_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gcc_gpll0.clkr.hw }, + { .hw =3D &gcc_gpll9.clkr.hw }, + { .hw =3D &gcc_gpll4.clkr.hw }, + { .hw =3D &gcc_gpll0_out_even.clkr.hw }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x64004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x65004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x66004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_aux_clk_src =3D { + .cmd_rcgr =3D 0xa0180, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0xa0054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_clk_src =3D { + .cmd_rcgr =3D 0x2c180, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2c054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_aux_clk_src =3D { + .cmd_rcgr =3D 0x13180, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x13054, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_3_aux_clk_src =3D { + .cmd_rcgr =3D 0x5808c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x58070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_4_aux_clk_src =3D { + .cmd_rcgr =3D 0x6b080, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x6b064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_5_aux_clk_src =3D { + .cmd_rcgr =3D 0x2f080, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x2f064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_6a_aux_clk_src =3D { + .cmd_rcgr =3D 0x3108c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x31070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_6b_aux_clk_src =3D { + .cmd_rcgr =3D 0x8d08c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x8d070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src =3D { + .cmd_rcgr =3D 0xa400c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rscc_xo_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x33010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x42010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x42148, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x42288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x423c8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] =3D { + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x42500, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x42638, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { + .cmd_rcgr =3D 0x42770, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { + .cmd_rcgr =3D 0x428a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src =3D { + .cmd_rcgr =3D 0x18010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src =3D { + .cmd_rcgr =3D 0x18148, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src =3D { + .cmd_rcgr =3D 0x18288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src =3D { + .cmd_rcgr =3D 0x183c8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src =3D { + .cmd_rcgr =3D 0x18500, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src =3D { + .cmd_rcgr =3D 0x18638, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src =3D { + .cmd_rcgr =3D 0x18770, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap1_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src =3D { + .cmd_rcgr =3D 0x188a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap1_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src =3D { + .cmd_rcgr =3D 0x1e010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src =3D { + .cmd_rcgr =3D 0x1e148, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src =3D { + .cmd_rcgr =3D 0x1e288, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src =3D { + .cmd_rcgr =3D 0x1e3c8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src =3D { + .cmd_rcgr =3D 0x1e500, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src =3D { + .cmd_rcgr =3D 0x1e638, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s6_clk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src =3D { + .cmd_rcgr =3D 0x1e770, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_8, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap2_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src =3D { + .cmd_rcgr =3D 0x1e8a8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s4_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap2_s7_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x14018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_9, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src =3D { + .cmd_rcgr =3D 0x16018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] =3D { + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src =3D { + .cmd_rcgr =3D 0x77030, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_axi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] =3D { + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src =3D { + .cmd_rcgr =3D 0x77080, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_7, + .freq_tbl =3D ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ice_core_clk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x770b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] =3D { + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src =3D { + .cmd_rcgr =3D 0x77098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_unipro_core_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] =3D { + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb20_master_clk_src =3D { + .cmd_rcgr =3D 0x2902c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb20_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x29158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] =3D { + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_mp_master_clk_src =3D { + .cmd_rcgr =3D 0x1702c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_mp_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x17158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src =3D { + .cmd_rcgr =3D 0x3902c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_mp_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x39044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_master_clk_src =3D { + .cmd_rcgr =3D 0xa102c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_mp_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0xa1044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_tert_master_clk_src =3D { + .cmd_rcgr =3D 0xa202c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_mp_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0xa2044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x172a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_mp_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x39074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xa1074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_sec_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0xa2074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_tert_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] =3D { + F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0), + F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0), + F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb4_0_master_clk_src =3D { + .cmd_rcgr =3D 0x9f024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_usb4_0_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_master_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0), + F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src =3D { + .cmd_rcgr =3D 0x9f0e8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_pcie_pipe_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src =3D { + .cmd_rcgr =3D 0x9f08c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_sb_if_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb4_0_tmu_clk_src =3D { + .cmd_rcgr =3D 0x9f070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_usb4_0_tmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_tmu_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_1_master_clk_src =3D { + .cmd_rcgr =3D 0x2b024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_usb4_0_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_master_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src =3D { + .cmd_rcgr =3D 0x2b0e8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_pcie_pipe_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src =3D { + .cmd_rcgr =3D 0x2b08c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_sb_if_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_1_tmu_clk_src =3D { + .cmd_rcgr =3D 0x2b070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_usb4_0_tmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_tmu_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_2_master_clk_src =3D { + .cmd_rcgr =3D 0x11024, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_usb4_0_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_master_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src =3D { + .cmd_rcgr =3D 0x110e8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_5, + .freq_tbl =3D ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_pcie_pipe_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src =3D { + .cmd_rcgr =3D 0x1108c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_sb_if_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb4_2_tmu_clk_src =3D { + .cmd_rcgr =3D 0x11070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_6, + .freq_tbl =3D ftbl_gcc_usb4_0_tmu_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_tmu_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src =3D { + .reg =3D 0x58088, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pcie_3_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_3_PIPE, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src =3D { + .reg =3D 0x5806c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_3_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src =3D { + .reg =3D 0x6b07c, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pcie_4_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_4_PIPE, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src =3D { + .reg =3D 0x6b060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_4_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src =3D { + .reg =3D 0x2f07c, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pcie_5_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_5_PIPE, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src =3D { + .reg =3D 0x2f060, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_5_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src =3D { + .reg =3D 0x31088, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pcie_6a_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_6A_PIPE, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src =3D { + .reg =3D 0x3106c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6a_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src =3D { + .reg =3D 0x8d088, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_pcie_6b_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_PCIE_6B_PIPE, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src =3D { + .reg =3D 0x8d06c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_pipe_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6b_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src =3D { + .reg =3D 0x42284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src =3D { + .reg =3D 0x423c4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src =3D { + .reg =3D 0x18284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src =3D { + .reg =3D 0x183c4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s3_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src =3D { + .reg =3D 0x1e284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src =3D { + .reg =3D 0x1e3c4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s3_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x29284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x17284, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x3905c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0xa105c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0xa205c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_tert_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_aggre_noc_usb_north_axi_clk =3D { + .halt_reg =3D 0x2d17c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d17c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2d17c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_usb_north_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_noc_usb_south_axi_clk =3D { + .halt_reg =3D 0x2d174, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d174, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2d174, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_noc_usb_south_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x770e4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770e4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb2_prim_axi_clk =3D { + .halt_reg =3D 0x2928c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2928c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2928c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb2_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_mp_axi_clk =3D { + .halt_reg =3D 0x173d0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x173d0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x173d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb3_mp_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mp_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x39090, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x39090, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x39090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_sec_axi_clk =3D { + .halt_reg =3D 0xa1090, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa1090, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa1090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_tert_axi_clk =3D { + .halt_reg =3D 0xa2090, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa2090, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa2090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb3_tert_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_tert_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb4_0_axi_clk =3D { + .halt_reg =3D 0x9f118, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9f118, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9f118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb4_0_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb4_1_axi_clk =3D { + .halt_reg =3D 0x2b118, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2b118, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2b118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb4_1_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb4_2_axi_clk =3D { + .halt_reg =3D 0x11118, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x11118, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x11118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb4_2_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb_noc_axi_clk =3D { + .halt_reg =3D 0x2d034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2d034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_aggre_usb_noc_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_av1e_ahb_clk =3D { + .halt_reg =3D 0x4a004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4a004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_av1e_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_av1e_axi_clk =3D { + .halt_reg =3D 0x4a008, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x4a008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4a008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_av1e_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_av1e_xo_clk =3D { + .halt_reg =3D 0x4a014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x4a014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_av1e_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x38004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x38004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk =3D { + .halt_reg =3D 0x26010, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x26010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_camera_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk =3D { + .halt_reg =3D 0x2601c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2601c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2601c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_camera_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk =3D { + .halt_reg =3D 0x10028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x10028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_pcie_anoc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk =3D { + .halt_reg =3D 0x1002c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1002c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_pcie_anoc_north_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk =3D { + .halt_reg =3D 0x10030, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x10030, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_pcie_anoc_south_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk =3D { + .halt_reg =3D 0x29288, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x29288, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x29288, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb2_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk =3D { + .halt_reg =3D 0x173cc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x173cc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x173cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_mp_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mp_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk =3D { + .halt_reg =3D 0x3908c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3908c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3908c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk =3D { + .halt_reg =3D 0xa108c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa108c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa108c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_sec_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk =3D { + .halt_reg =3D 0xa208c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa208c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa208c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb3_tert_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_tert_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk =3D { + .halt_reg =3D 0x2d024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb_anoc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk =3D { + .halt_reg =3D 0x2d028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb_anoc_north_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk =3D { + .halt_reg =3D 0x2d02c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d02c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cfg_noc_usb_anoc_south_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie1_tunnel_clk =3D { + .halt_reg =3D 0x2c2b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie1_tunnel_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie2_tunnel_clk =3D { + .halt_reg =3D 0x132b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie2_tunnel_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk =3D { + .halt_reg =3D 0x10014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x10014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie_north_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk =3D { + .halt_reg =3D 0x10018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x10018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie_south_sf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cnoc_pcie_tunnel_clk =3D { + .halt_reg =3D 0xa02b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa02b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_cnoc_pcie_tunnel_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk =3D { + .halt_reg =3D 0x7115c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x7115c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7115c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ddrss_gpu_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk =3D { + .halt_reg =3D 0x2700c, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2700c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2700c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_disp_hf_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_xo_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_disp_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x64000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x64000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x65000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x65000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x66000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x66000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { + .halt_reg =3D 0x71004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_cph_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_gpll0_cph_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src =3D { + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_gpll0_div_cph_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gpll0_out_even.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk =3D { + .halt_reg =3D 0x71010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gpu_snoc_dvm_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_phy_rchng_clk =3D { + .halt_reg =3D 0xa0050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie0_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_phy_rchng_clk =3D { + .halt_reg =3D 0x2c050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie1_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_phy_rchng_clk =3D { + .halt_reg =3D 0x13050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie2_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_aux_clk =3D { + .halt_reg =3D 0xa0038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_cfg_ahb_clk =3D { + .halt_reg =3D 0xa0034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa0034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk =3D { + .halt_reg =3D 0xa0028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0xa0028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_clk =3D { + .halt_reg =3D 0xa0044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_axi_clk =3D { + .halt_reg =3D 0xa001c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa001c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk =3D { + .halt_reg =3D 0xa0018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk =3D { + .halt_reg =3D 0x2c038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk =3D { + .halt_reg =3D 0x2c034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk =3D { + .halt_reg =3D 0x2c028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2c028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk =3D { + .halt_reg =3D 0x2c044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk =3D { + .halt_reg =3D 0x2c01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2c01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x2c018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_aux_clk =3D { + .halt_reg =3D 0x13038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_cfg_ahb_clk =3D { + .halt_reg =3D 0x13034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x13034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_mstr_axi_clk =3D { + .halt_reg =3D 0x13028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x13028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_clk =3D { + .halt_reg =3D 0x13044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_axi_clk =3D { + .halt_reg =3D 0x1301c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x1301c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x13018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_aux_clk =3D { + .halt_reg =3D 0x58038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_3_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_cfg_ahb_clk =3D { + .halt_reg =3D 0x58034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x58034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_mstr_axi_clk =3D { + .halt_reg =3D 0x58028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x58028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_phy_aux_clk =3D { + .halt_reg =3D 0x58044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_phy_aux_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_phy_rchng_clk =3D { + .halt_reg =3D 0x5805c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_3_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_pipe_clk =3D { + .halt_reg =3D 0x58050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_pipediv2_clk =3D { + .halt_reg =3D 0x58060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_3_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_slv_axi_clk =3D { + .halt_reg =3D 0x5801c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x5801c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x58018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_3_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_aux_clk =3D { + .halt_reg =3D 0x6b038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_4_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_cfg_ahb_clk =3D { + .halt_reg =3D 0x6b034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x6b034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_mstr_axi_clk =3D { + .halt_reg =3D 0x6b028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x6b028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_phy_rchng_clk =3D { + .halt_reg =3D 0x6b050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_4_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_pipe_clk =3D { + .halt_reg =3D 0x6b044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_pipediv2_clk =3D { + .halt_reg =3D 0x6b054, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_4_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_slv_axi_clk =3D { + .halt_reg =3D 0x6b01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x6b01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x6b018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_4_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_aux_clk =3D { + .halt_reg =3D 0x2f038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_5_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_cfg_ahb_clk =3D { + .halt_reg =3D 0x2f034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2f034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_mstr_axi_clk =3D { + .halt_reg =3D 0x2f028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x2f028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_phy_rchng_clk =3D { + .halt_reg =3D 0x2f050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_5_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_pipe_clk =3D { + .halt_reg =3D 0x2f044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_pipediv2_clk =3D { + .halt_reg =3D 0x2f054, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_5_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_slv_axi_clk =3D { + .halt_reg =3D 0x2f01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2f01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x2f018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_5_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_aux_clk =3D { + .halt_reg =3D 0x31038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6a_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_cfg_ahb_clk =3D { + .halt_reg =3D 0x31034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x31034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_mstr_axi_clk =3D { + .halt_reg =3D 0x31028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x31028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_phy_aux_clk =3D { + .halt_reg =3D 0x31044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_phy_aux_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_phy_rchng_clk =3D { + .halt_reg =3D 0x3105c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6a_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_pipe_clk =3D { + .halt_reg =3D 0x31050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_pipediv2_clk =3D { + .halt_reg =3D 0x31060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6a_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_slv_axi_clk =3D { + .halt_reg =3D 0x3101c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3101c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x31018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52018, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6a_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_aux_clk =3D { + .halt_reg =3D 0x8d038, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6b_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_cfg_ahb_clk =3D { + .halt_reg =3D 0x8d034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8d034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_mstr_axi_clk =3D { + .halt_reg =3D 0x8d028, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x8d028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_phy_aux_clk =3D { + .halt_reg =3D 0x8d044, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_phy_aux_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_phy_rchng_clk =3D { + .halt_reg =3D 0x8d05c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6b_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_pipe_clk =3D { + .halt_reg =3D 0x8d050, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_pipediv2_clk =3D { + .halt_reg =3D 0x8d060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_pipediv2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_6b_pipe_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_slv_axi_clk =3D { + .halt_reg =3D 0x8d01c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8d01c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x8d018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52000, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_6b_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rscc_ahb_clk =3D { + .halt_reg =3D 0xa4008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa4008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rscc_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rscc_xo_clk =3D { + .halt_reg =3D 0xa4004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rscc_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_rscc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3300c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3300c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x33004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x33004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x33004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x33008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x33008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_av1e_ahb_clk =3D { + .halt_reg =3D 0x4a018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x4a018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x4a018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_av1e_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk =3D { + .halt_reg =3D 0x26008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x26008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x26008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_camera_nrt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk =3D { + .halt_reg =3D 0x2600c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2600c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2600c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_camera_rt_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk =3D { + .halt_reg =3D 0x27008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x27008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x27008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_disp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_ahb_clk =3D { + .halt_reg =3D 0x71008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_gpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk =3D { + .halt_reg =3D 0x32014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x32014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_cv_cpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk =3D { + .halt_reg =3D 0x32008, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x32008, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_cvp_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk =3D { + .halt_reg =3D 0x32010, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x32010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_v_cpu_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk =3D { + .halt_reg =3D 0x3200c, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x3200c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3200c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qmip_video_vcodec_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x23018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x23008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk =3D { + .halt_reg =3D 0x42280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_qspi_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk =3D { + .halt_reg =3D 0x423c0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_qspi_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x42004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x4213c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x42274, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x423b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x424f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x4262c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { + .halt_reg =3D 0x42764, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk =3D { + .halt_reg =3D 0x4289c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk =3D { + .halt_reg =3D 0x23168, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk =3D { + .halt_reg =3D 0x23158, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk =3D { + .halt_reg =3D 0x18280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_qspi_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk =3D { + .halt_reg =3D 0x183c0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_qspi_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk =3D { + .halt_reg =3D 0x18004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk =3D { + .halt_reg =3D 0x1813c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk =3D { + .halt_reg =3D 0x18274, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk =3D { + .halt_reg =3D 0x183b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk =3D { + .halt_reg =3D 0x184f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk =3D { + .halt_reg =3D 0x1862c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(27), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s6_clk =3D { + .halt_reg =3D 0x18764, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s7_clk =3D { + .halt_reg =3D 0x1889c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap1_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk =3D { + .halt_reg =3D 0x232b8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_clk =3D { + .halt_reg =3D 0x232a8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk =3D { + .halt_reg =3D 0x1e280, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_qspi_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk =3D { + .halt_reg =3D 0x1e3c0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_qspi_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s0_clk =3D { + .halt_reg =3D 0x1e004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s1_clk =3D { + .halt_reg =3D 0x1e13c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s2_clk =3D { + .halt_reg =3D 0x1e274, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s3_clk =3D { + .halt_reg =3D 0x1e3b4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s4_clk =3D { + .halt_reg =3D 0x1e4f4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s5_clk =3D { + .halt_reg =3D 0x1e62c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(9), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s6_clk =3D { + .halt_reg =3D 0x1e764, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s7_clk =3D { + .halt_reg =3D 0x1e89c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap2_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap2_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x23000, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23000, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x23004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52020, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk =3D { + .halt_reg =3D 0x23150, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23150, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk =3D { + .halt_reg =3D 0x23154, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x23154, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_1_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk =3D { + .halt_reg =3D 0x232a0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x232a0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(2), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_2_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk =3D { + .halt_reg =3D 0x232a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x232a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_2_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x14010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x14004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x14004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk =3D { + .halt_reg =3D 0x16010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk =3D { + .halt_reg =3D 0x16004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x16004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc4_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb_axi_clk =3D { + .halt_reg =3D 0x2d014, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d014, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2d014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sys_noc_usb_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk =3D { + .halt_reg =3D 0x77024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk =3D { + .halt_reg =3D 0x77018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk =3D { + .halt_reg =3D 0x77074, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77074, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_ice_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk =3D { + .halt_reg =3D 0x770b0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x770b0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x770b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { + .halt_reg =3D 0x7702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x7702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { + .halt_reg =3D 0x770cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x770cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { + .halt_reg =3D 0x77028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x77028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk =3D { + .halt_reg =3D 0x77068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x77068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x77068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_unipro_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk =3D { + .halt_reg =3D 0x29018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk =3D { + .halt_reg =3D 0x29028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk =3D { + .halt_reg =3D 0x29024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x29024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb20_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mp_master_clk =3D { + .halt_reg =3D 0x17018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mp_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mp_mock_utmi_clk =3D { + .halt_reg =3D 0x17028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mp_sleep_clk =3D { + .halt_reg =3D 0x17024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mp_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk =3D { + .halt_reg =3D 0x39018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk =3D { + .halt_reg =3D 0x39028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk =3D { + .halt_reg =3D 0x39024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_prim_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_master_clk =3D { + .halt_reg =3D 0xa1018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa1018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_mock_utmi_clk =3D { + .halt_reg =3D 0xa1028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa1028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_sleep_clk =3D { + .halt_reg =3D 0xa1024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa1024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sec_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_tert_master_clk =3D { + .halt_reg =3D 0xa2018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa2018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_tert_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_tert_mock_utmi_clk =3D { + .halt_reg =3D 0xa2028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa2028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_tert_sleep_clk =3D { + .halt_reg =3D 0xa2024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa2024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_tert_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_mp_phy_aux_clk =3D { + .halt_reg =3D 0x17288, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17288, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_mp_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_mp_phy_com_aux_clk =3D { + .halt_reg =3D 0x1728c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1728c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_mp_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_mp_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk =3D { + .halt_reg =3D 0x17290, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17290, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_mp_phy_pipe_0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk =3D { + .halt_reg =3D 0x17298, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x17298, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_mp_phy_pipe_1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk =3D { + .halt_reg =3D 0x39060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk =3D { + .halt_reg =3D 0x39064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x39064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src =3D { + .reg =3D 0x3906c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_10, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_prim_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { + .halt_reg =3D 0x39068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x39068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x39068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_aux_clk =3D { + .halt_reg =3D 0xa1060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa1060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_sec_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_com_aux_clk =3D { + .halt_reg =3D 0xa1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_sec_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src =3D { + .reg =3D 0xa106c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_11, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_sec_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_pipe_clk =3D { + .halt_reg =3D 0xa1068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa1068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa1068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_sec_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_tert_phy_aux_clk =3D { + .halt_reg =3D 0xa2060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa2060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_tert_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_tert_phy_com_aux_clk =3D { + .halt_reg =3D 0xa2064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa2064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_tert_phy_com_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_tert_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src =3D { + .reg =3D 0xa206c, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_12, + .clkr =3D { + .hw.init =3D &(struct clk_init_data){ + .name =3D "gcc_usb3_tert_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_tert_phy_pipe_clk =3D { + .halt_reg =3D 0xa2068, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0xa2068, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0xa2068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_tert_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_cfg_ahb_clk =3D { + .halt_reg =3D 0x9f0a8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9f0a8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9f0a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_dp0_clk =3D { + .halt_reg =3D 0x9f060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_dp0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_dp1_clk =3D { + .halt_reg =3D 0x9f108, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_dp1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_master_clk =3D { + .halt_reg =3D 0x9f018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk =3D { + .halt_reg =3D 0x9f0d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f0d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_p2rr2p_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk =3D { + .halt_reg =3D 0x9f048, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52010, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_pcie_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_phy_rx0_clk =3D { + .halt_reg =3D 0x9f0b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f0b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_rx0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_phy_rx1_clk =3D { + .halt_reg =3D 0x9f0c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f0c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_rx1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk =3D { + .halt_reg =3D 0x9f0a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9f0a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9f0a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_usb_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_sb_if_clk =3D { + .halt_reg =3D 0x9f044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_sb_if_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_sb_if_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_sys_clk =3D { + .halt_reg =3D 0x9f054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9f054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_sys_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_0_tmu_clk =3D { + .halt_reg =3D 0x9f088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x9f088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x9f088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_tmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_tmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_cfg_ahb_clk =3D { + .halt_reg =3D 0x2b0a8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2b0a8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2b0a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_dp0_clk =3D { + .halt_reg =3D 0x2b060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_dp0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_dp1_clk =3D { + .halt_reg =3D 0x2b108, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_dp1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_master_clk =3D { + .halt_reg =3D 0x2b018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk =3D { + .halt_reg =3D 0x2b0d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b0d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_p2rr2p_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk =3D { + .halt_reg =3D 0x2b048, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_pcie_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_phy_rx0_clk =3D { + .halt_reg =3D 0x2b0b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b0b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_rx0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_phy_rx1_clk =3D { + .halt_reg =3D 0x2b0c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b0c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_rx1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk =3D { + .halt_reg =3D 0x2b0a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2b0a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2b0a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_usb_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_sb_if_clk =3D { + .halt_reg =3D 0x2b044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_sb_if_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_sb_if_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_sys_clk =3D { + .halt_reg =3D 0x2b054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2b054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_sys_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_1_tmu_clk =3D { + .halt_reg =3D 0x2b088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2b088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2b088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_tmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_tmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_cfg_ahb_clk =3D { + .halt_reg =3D 0x110a8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x110a8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x110a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_dp0_clk =3D { + .halt_reg =3D 0x11060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_dp0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_dp1_clk =3D { + .halt_reg =3D 0x11108, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_dp1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_master_clk =3D { + .halt_reg =3D 0x11018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk =3D { + .halt_reg =3D 0x110d8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_p2rr2p_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk =3D { + .halt_reg =3D 0x11048, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x52028, + .enable_mask =3D BIT(1), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_pcie_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_phy_rx0_clk =3D { + .halt_reg =3D 0x110b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_rx0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_phy_rx1_clk =3D { + .halt_reg =3D 0x110c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_rx1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk =3D { + .halt_reg =3D 0x110a4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x110a4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x110a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_usb_pipe_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_sb_if_clk =3D { + .halt_reg =3D 0x11044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_sb_if_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_sb_if_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_sys_clk =3D { + .halt_reg =3D 0x11054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_sys_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb4_2_tmu_clk =3D { + .halt_reg =3D 0x11088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x11088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x11088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_tmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_tmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk =3D { + .halt_reg =3D 0x32018, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_video_axi0_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi1_clk =3D { + .halt_reg =3D 0x32024, + .halt_check =3D BRANCH_HALT_SKIP, + .hwcg_reg =3D 0x32024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x32024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_video_axi1_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gcc_pcie_0_tunnel_gdsc =3D { + .gdscr =3D 0xa0004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_0_tunnel_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_1_tunnel_gdsc =3D { + .gdscr =3D 0x2c004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_1_tunnel_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_2_tunnel_gdsc =3D { + .gdscr =3D 0x13004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_2_tunnel_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_3_gdsc =3D { + .gdscr =3D 0x58004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_3_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_3_phy_gdsc =3D { + .gdscr =3D 0x3e000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_3_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_4_gdsc =3D { + .gdscr =3D 0x6b004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_4_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_4_phy_gdsc =3D { + .gdscr =3D 0x6c000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_4_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_5_gdsc =3D { + .gdscr =3D 0x2f004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_5_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_5_phy_gdsc =3D { + .gdscr =3D 0x30000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_5_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_6_phy_gdsc =3D { + .gdscr =3D 0x8e000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_6_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_6a_gdsc =3D { + .gdscr =3D 0x31004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_6a_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_pcie_6b_gdsc =3D { + .gdscr =3D 0x8d004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_6b_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, +}; + +static struct gdsc gcc_ufs_mem_phy_gdsc =3D { + .gdscr =3D 0x9e000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_ufs_mem_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_ufs_phy_gdsc =3D { + .gdscr =3D 0x77004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_ufs_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb20_prim_gdsc =3D { + .gdscr =3D 0x29004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb20_prim_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_mp_gdsc =3D { + .gdscr =3D 0x17004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_mp_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_prim_gdsc =3D { + .gdscr =3D 0x39004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_prim_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_sec_gdsc =3D { + .gdscr =3D 0xa1004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_sec_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_tert_gdsc =3D { + .gdscr =3D 0xa2004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_tert_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb3_mp_ss0_phy_gdsc =3D { + .gdscr =3D 0x1900c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb3_mp_ss0_phy_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb3_mp_ss1_phy_gdsc =3D { + .gdscr =3D 0x5400c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb3_mp_ss1_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb4_0_gdsc =3D { + .gdscr =3D 0x9f004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb4_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb4_1_gdsc =3D { + .gdscr =3D 0x2b004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb4_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb4_2_gdsc =3D { + .gdscr =3D 0x11004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb4_2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb_0_phy_gdsc =3D { + .gdscr =3D 0x50024, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb_0_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb_1_phy_gdsc =3D { + .gdscr =3D 0x2a024, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb_1_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb_2_phy_gdsc =3D { + .gdscr =3D 0xa3024, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb_2_phy_gdsc", + }, + .pwrsts =3D PWRSTS_RET_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_sc8380xp_clocks[] =3D { + [GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] =3D &gcc_aggre_noc_usb_north_axi_clk.cl= kr, + [GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] =3D &gcc_aggre_noc_usb_south_axi_clk.cl= kr, + [GCC_AGGRE_UFS_PHY_AXI_CLK] =3D &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB2_PRIM_AXI_CLK] =3D &gcc_aggre_usb2_prim_axi_clk.clkr, + [GCC_AGGRE_USB3_MP_AXI_CLK] =3D &gcc_aggre_usb3_mp_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] =3D &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_AGGRE_USB3_SEC_AXI_CLK] =3D &gcc_aggre_usb3_sec_axi_clk.clkr, + [GCC_AGGRE_USB3_TERT_AXI_CLK] =3D &gcc_aggre_usb3_tert_axi_clk.clkr, + [GCC_AGGRE_USB4_0_AXI_CLK] =3D &gcc_aggre_usb4_0_axi_clk.clkr, + [GCC_AGGRE_USB4_1_AXI_CLK] =3D &gcc_aggre_usb4_1_axi_clk.clkr, + [GCC_AGGRE_USB4_2_AXI_CLK] =3D &gcc_aggre_usb4_2_axi_clk.clkr, + [GCC_AGGRE_USB_NOC_AXI_CLK] =3D &gcc_aggre_usb_noc_axi_clk.clkr, + [GCC_AV1E_AHB_CLK] =3D &gcc_av1e_ahb_clk.clkr, + [GCC_AV1E_AXI_CLK] =3D &gcc_av1e_axi_clk.clkr, + [GCC_AV1E_XO_CLK] =3D &gcc_av1e_xo_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] =3D &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] =3D &gcc_camera_sf_axi_clk.clkr, + [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] =3D &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, + [GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] =3D &gcc_cfg_noc_pcie_anoc_north_ah= b_clk.clkr, + [GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] =3D &gcc_cfg_noc_pcie_anoc_south_ah= b_clk.clkr, + [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb2_prim_axi_clk.clkr, + [GCC_CFG_NOC_USB3_MP_AXI_CLK] =3D &gcc_cfg_noc_usb3_mp_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CFG_NOC_USB3_SEC_AXI_CLK] =3D &gcc_cfg_noc_usb3_sec_axi_clk.clkr, + [GCC_CFG_NOC_USB3_TERT_AXI_CLK] =3D &gcc_cfg_noc_usb3_tert_axi_clk.clkr, + [GCC_CFG_NOC_USB_ANOC_AHB_CLK] =3D &gcc_cfg_noc_usb_anoc_ahb_clk.clkr, + [GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] =3D &gcc_cfg_noc_usb_anoc_north_ahb_= clk.clkr, + [GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] =3D &gcc_cfg_noc_usb_anoc_south_ahb_= clk.clkr, + [GCC_CNOC_PCIE1_TUNNEL_CLK] =3D &gcc_cnoc_pcie1_tunnel_clk.clkr, + [GCC_CNOC_PCIE2_TUNNEL_CLK] =3D &gcc_cnoc_pcie2_tunnel_clk.clkr, + [GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] =3D &gcc_cnoc_pcie_north_sf_axi_clk.clkr, + [GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] =3D &gcc_cnoc_pcie_south_sf_axi_clk.clkr, + [GCC_CNOC_PCIE_TUNNEL_CLK] =3D &gcc_cnoc_pcie_tunnel_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] =3D &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_XO_CLK] =3D &gcc_disp_xo_clk.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_GPLL0] =3D &gcc_gpll0.clkr, + [GCC_GPLL0_OUT_EVEN] =3D &gcc_gpll0_out_even.clkr, + [GCC_GPLL4] =3D &gcc_gpll4.clkr, + [GCC_GPLL7] =3D &gcc_gpll7.clkr, + [GCC_GPLL8] =3D &gcc_gpll8.clkr, + [GCC_GPLL9] =3D &gcc_gpll9.clkr, + [GCC_GPU_CFG_AHB_CLK] =3D &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CPH_CLK_SRC] =3D &gcc_gpu_gpll0_cph_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] =3D &gcc_gpu_gpll0_div_cph_clk_src.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] =3D &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_PCIE0_PHY_RCHNG_CLK] =3D &gcc_pcie0_phy_rchng_clk.clkr, + [GCC_PCIE1_PHY_RCHNG_CLK] =3D &gcc_pcie1_phy_rchng_clk.clkr, + [GCC_PCIE2_PHY_RCHNG_CLK] =3D &gcc_pcie2_phy_rchng_clk.clkr, + [GCC_PCIE_0_AUX_CLK] =3D &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_AUX_CLK_SRC] =3D &gcc_pcie_0_aux_clk_src.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] =3D &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] =3D &gcc_pcie_0_mstr_axi_clk.clkr, + [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_0_phy_rchng_clk_src.clkr, + [GCC_PCIE_0_PIPE_CLK] =3D &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] =3D &gcc_pcie_0_slv_axi_clk.clkr, + [GCC_PCIE_0_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_0_slv_q2a_axi_clk.clkr, + [GCC_PCIE_1_AUX_CLK] =3D &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_AUX_CLK_SRC] =3D &gcc_pcie_1_aux_clk_src.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] =3D &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] =3D &gcc_pcie_1_mstr_axi_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_1_phy_rchng_clk_src.clkr, + [GCC_PCIE_1_PIPE_CLK] =3D &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] =3D &gcc_pcie_1_slv_axi_clk.clkr, + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [GCC_PCIE_2_AUX_CLK] =3D &gcc_pcie_2_aux_clk.clkr, + [GCC_PCIE_2_AUX_CLK_SRC] =3D &gcc_pcie_2_aux_clk_src.clkr, + [GCC_PCIE_2_CFG_AHB_CLK] =3D &gcc_pcie_2_cfg_ahb_clk.clkr, + [GCC_PCIE_2_MSTR_AXI_CLK] =3D &gcc_pcie_2_mstr_axi_clk.clkr, + [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_2_phy_rchng_clk_src.clkr, + [GCC_PCIE_2_PIPE_CLK] =3D &gcc_pcie_2_pipe_clk.clkr, + [GCC_PCIE_2_SLV_AXI_CLK] =3D &gcc_pcie_2_slv_axi_clk.clkr, + [GCC_PCIE_2_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_2_slv_q2a_axi_clk.clkr, + [GCC_PCIE_3_AUX_CLK] =3D &gcc_pcie_3_aux_clk.clkr, + [GCC_PCIE_3_AUX_CLK_SRC] =3D &gcc_pcie_3_aux_clk_src.clkr, + [GCC_PCIE_3_CFG_AHB_CLK] =3D &gcc_pcie_3_cfg_ahb_clk.clkr, + [GCC_PCIE_3_MSTR_AXI_CLK] =3D &gcc_pcie_3_mstr_axi_clk.clkr, + [GCC_PCIE_3_PHY_AUX_CLK] =3D &gcc_pcie_3_phy_aux_clk.clkr, + [GCC_PCIE_3_PHY_RCHNG_CLK] =3D &gcc_pcie_3_phy_rchng_clk.clkr, + [GCC_PCIE_3_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_3_phy_rchng_clk_src.clkr, + [GCC_PCIE_3_PIPE_CLK] =3D &gcc_pcie_3_pipe_clk.clkr, + [GCC_PCIE_3_PIPE_CLK_SRC] =3D &gcc_pcie_3_pipe_clk_src.clkr, + [GCC_PCIE_3_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_3_pipe_div_clk_src.clkr, + [GCC_PCIE_3_PIPEDIV2_CLK] =3D &gcc_pcie_3_pipediv2_clk.clkr, + [GCC_PCIE_3_SLV_AXI_CLK] =3D &gcc_pcie_3_slv_axi_clk.clkr, + [GCC_PCIE_3_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_3_slv_q2a_axi_clk.clkr, + [GCC_PCIE_4_AUX_CLK] =3D &gcc_pcie_4_aux_clk.clkr, + [GCC_PCIE_4_AUX_CLK_SRC] =3D &gcc_pcie_4_aux_clk_src.clkr, + [GCC_PCIE_4_CFG_AHB_CLK] =3D &gcc_pcie_4_cfg_ahb_clk.clkr, + [GCC_PCIE_4_MSTR_AXI_CLK] =3D &gcc_pcie_4_mstr_axi_clk.clkr, + [GCC_PCIE_4_PHY_RCHNG_CLK] =3D &gcc_pcie_4_phy_rchng_clk.clkr, + [GCC_PCIE_4_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_4_phy_rchng_clk_src.clkr, + [GCC_PCIE_4_PIPE_CLK] =3D &gcc_pcie_4_pipe_clk.clkr, + [GCC_PCIE_4_PIPE_CLK_SRC] =3D &gcc_pcie_4_pipe_clk_src.clkr, + [GCC_PCIE_4_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_4_pipe_div_clk_src.clkr, + [GCC_PCIE_4_PIPEDIV2_CLK] =3D &gcc_pcie_4_pipediv2_clk.clkr, + [GCC_PCIE_4_SLV_AXI_CLK] =3D &gcc_pcie_4_slv_axi_clk.clkr, + [GCC_PCIE_4_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_4_slv_q2a_axi_clk.clkr, + [GCC_PCIE_5_AUX_CLK] =3D &gcc_pcie_5_aux_clk.clkr, + [GCC_PCIE_5_AUX_CLK_SRC] =3D &gcc_pcie_5_aux_clk_src.clkr, + [GCC_PCIE_5_CFG_AHB_CLK] =3D &gcc_pcie_5_cfg_ahb_clk.clkr, + [GCC_PCIE_5_MSTR_AXI_CLK] =3D &gcc_pcie_5_mstr_axi_clk.clkr, + [GCC_PCIE_5_PHY_RCHNG_CLK] =3D &gcc_pcie_5_phy_rchng_clk.clkr, + [GCC_PCIE_5_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_5_phy_rchng_clk_src.clkr, + [GCC_PCIE_5_PIPE_CLK] =3D &gcc_pcie_5_pipe_clk.clkr, + [GCC_PCIE_5_PIPE_CLK_SRC] =3D &gcc_pcie_5_pipe_clk_src.clkr, + [GCC_PCIE_5_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_5_pipe_div_clk_src.clkr, + [GCC_PCIE_5_PIPEDIV2_CLK] =3D &gcc_pcie_5_pipediv2_clk.clkr, + [GCC_PCIE_5_SLV_AXI_CLK] =3D &gcc_pcie_5_slv_axi_clk.clkr, + [GCC_PCIE_5_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_5_slv_q2a_axi_clk.clkr, + [GCC_PCIE_6A_AUX_CLK] =3D &gcc_pcie_6a_aux_clk.clkr, + [GCC_PCIE_6A_AUX_CLK_SRC] =3D &gcc_pcie_6a_aux_clk_src.clkr, + [GCC_PCIE_6A_CFG_AHB_CLK] =3D &gcc_pcie_6a_cfg_ahb_clk.clkr, + [GCC_PCIE_6A_MSTR_AXI_CLK] =3D &gcc_pcie_6a_mstr_axi_clk.clkr, + [GCC_PCIE_6A_PHY_AUX_CLK] =3D &gcc_pcie_6a_phy_aux_clk.clkr, + [GCC_PCIE_6A_PHY_RCHNG_CLK] =3D &gcc_pcie_6a_phy_rchng_clk.clkr, + [GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_6a_phy_rchng_clk_src.clkr, + [GCC_PCIE_6A_PIPE_CLK] =3D &gcc_pcie_6a_pipe_clk.clkr, + [GCC_PCIE_6A_PIPE_CLK_SRC] =3D &gcc_pcie_6a_pipe_clk_src.clkr, + [GCC_PCIE_6A_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_6a_pipe_div_clk_src.clkr, + [GCC_PCIE_6A_PIPEDIV2_CLK] =3D &gcc_pcie_6a_pipediv2_clk.clkr, + [GCC_PCIE_6A_SLV_AXI_CLK] =3D &gcc_pcie_6a_slv_axi_clk.clkr, + [GCC_PCIE_6A_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_6a_slv_q2a_axi_clk.clkr, + [GCC_PCIE_6B_AUX_CLK] =3D &gcc_pcie_6b_aux_clk.clkr, + [GCC_PCIE_6B_AUX_CLK_SRC] =3D &gcc_pcie_6b_aux_clk_src.clkr, + [GCC_PCIE_6B_CFG_AHB_CLK] =3D &gcc_pcie_6b_cfg_ahb_clk.clkr, + [GCC_PCIE_6B_MSTR_AXI_CLK] =3D &gcc_pcie_6b_mstr_axi_clk.clkr, + [GCC_PCIE_6B_PHY_AUX_CLK] =3D &gcc_pcie_6b_phy_aux_clk.clkr, + [GCC_PCIE_6B_PHY_RCHNG_CLK] =3D &gcc_pcie_6b_phy_rchng_clk.clkr, + [GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_6b_phy_rchng_clk_src.clkr, + [GCC_PCIE_6B_PIPE_CLK] =3D &gcc_pcie_6b_pipe_clk.clkr, + [GCC_PCIE_6B_PIPE_CLK_SRC] =3D &gcc_pcie_6b_pipe_clk_src.clkr, + [GCC_PCIE_6B_PIPE_DIV_CLK_SRC] =3D &gcc_pcie_6b_pipe_div_clk_src.clkr, + [GCC_PCIE_6B_PIPEDIV2_CLK] =3D &gcc_pcie_6b_pipediv2_clk.clkr, + [GCC_PCIE_6B_SLV_AXI_CLK] =3D &gcc_pcie_6b_slv_axi_clk.clkr, + [GCC_PCIE_6B_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_6b_slv_q2a_axi_clk.clkr, + [GCC_PCIE_RSCC_AHB_CLK] =3D &gcc_pcie_rscc_ahb_clk.clkr, + [GCC_PCIE_RSCC_XO_CLK] =3D &gcc_pcie_rscc_xo_clk.clkr, + [GCC_PCIE_RSCC_XO_CLK_SRC] =3D &gcc_pcie_rscc_xo_clk_src.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QMIP_AV1E_AHB_CLK] =3D &gcc_qmip_av1e_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] =3D &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] =3D &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] =3D &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_GPU_AHB_CLK] =3D &gcc_qmip_gpu_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] =3D &gcc_qmip_video_cv_cpu_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] =3D &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] =3D &gcc_qmip_video_v_cpu_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] =3D &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_QSPI_S2_CLK] =3D &gcc_qupv3_wrap0_qspi_s2_clk.clkr, + [GCC_QUPV3_WRAP0_QSPI_S3_CLK] =3D &gcc_qupv3_wrap0_qspi_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_div_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_div_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] =3D &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] =3D &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP0_S7_CLK] =3D &gcc_qupv3_wrap0_s7_clk.clkr, + [GCC_QUPV3_WRAP0_S7_CLK_SRC] =3D &gcc_qupv3_wrap0_s7_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] =3D &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] =3D &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_QSPI_S2_CLK] =3D &gcc_qupv3_wrap1_qspi_s2_clk.clkr, + [GCC_QUPV3_WRAP1_QSPI_S3_CLK] =3D &gcc_qupv3_wrap1_qspi_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] =3D &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] =3D &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] =3D &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] =3D &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] =3D &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] =3D &gcc_qupv3_wrap1_s2_div_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] =3D &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] =3D &gcc_qupv3_wrap1_s3_div_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] =3D &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] =3D &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] =3D &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] =3D &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_S6_CLK] =3D &gcc_qupv3_wrap1_s6_clk.clkr, + [GCC_QUPV3_WRAP1_S6_CLK_SRC] =3D &gcc_qupv3_wrap1_s6_clk_src.clkr, + [GCC_QUPV3_WRAP1_S7_CLK] =3D &gcc_qupv3_wrap1_s7_clk.clkr, + [GCC_QUPV3_WRAP1_S7_CLK_SRC] =3D &gcc_qupv3_wrap1_s7_clk_src.clkr, + [GCC_QUPV3_WRAP2_CORE_2X_CLK] =3D &gcc_qupv3_wrap2_core_2x_clk.clkr, + [GCC_QUPV3_WRAP2_CORE_CLK] =3D &gcc_qupv3_wrap2_core_clk.clkr, + [GCC_QUPV3_WRAP2_QSPI_S2_CLK] =3D &gcc_qupv3_wrap2_qspi_s2_clk.clkr, + [GCC_QUPV3_WRAP2_QSPI_S3_CLK] =3D &gcc_qupv3_wrap2_qspi_s3_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK] =3D &gcc_qupv3_wrap2_s0_clk.clkr, + [GCC_QUPV3_WRAP2_S0_CLK_SRC] =3D &gcc_qupv3_wrap2_s0_clk_src.clkr, + [GCC_QUPV3_WRAP2_S1_CLK] =3D &gcc_qupv3_wrap2_s1_clk.clkr, + [GCC_QUPV3_WRAP2_S1_CLK_SRC] =3D &gcc_qupv3_wrap2_s1_clk_src.clkr, + [GCC_QUPV3_WRAP2_S2_CLK] =3D &gcc_qupv3_wrap2_s2_clk.clkr, + [GCC_QUPV3_WRAP2_S2_CLK_SRC] =3D &gcc_qupv3_wrap2_s2_clk_src.clkr, + [GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] =3D &gcc_qupv3_wrap2_s2_div_clk_src.clkr, + [GCC_QUPV3_WRAP2_S3_CLK] =3D &gcc_qupv3_wrap2_s3_clk.clkr, + [GCC_QUPV3_WRAP2_S3_CLK_SRC] =3D &gcc_qupv3_wrap2_s3_clk_src.clkr, + [GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] =3D &gcc_qupv3_wrap2_s3_div_clk_src.clkr, + [GCC_QUPV3_WRAP2_S4_CLK] =3D &gcc_qupv3_wrap2_s4_clk.clkr, + [GCC_QUPV3_WRAP2_S4_CLK_SRC] =3D &gcc_qupv3_wrap2_s4_clk_src.clkr, + [GCC_QUPV3_WRAP2_S5_CLK] =3D &gcc_qupv3_wrap2_s5_clk.clkr, + [GCC_QUPV3_WRAP2_S5_CLK_SRC] =3D &gcc_qupv3_wrap2_s5_clk_src.clkr, + [GCC_QUPV3_WRAP2_S6_CLK] =3D &gcc_qupv3_wrap2_s6_clk.clkr, + [GCC_QUPV3_WRAP2_S6_CLK_SRC] =3D &gcc_qupv3_wrap2_s6_clk_src.clkr, + [GCC_QUPV3_WRAP2_S7_CLK] =3D &gcc_qupv3_wrap2_s7_clk.clkr, + [GCC_QUPV3_WRAP2_S7_CLK_SRC] =3D &gcc_qupv3_wrap2_s7_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] =3D &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] =3D &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_M_AHB_CLK] =3D &gcc_qupv3_wrap_2_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_2_S_AHB_CLK] =3D &gcc_qupv3_wrap_2_s_ahb_clk.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SDCC4_AHB_CLK] =3D &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] =3D &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] =3D &gcc_sdcc4_apps_clk_src.clkr, + [GCC_SYS_NOC_USB_AXI_CLK] =3D &gcc_sys_noc_usb_axi_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] =3D &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] =3D &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] =3D &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] =3D &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] =3D &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] =3D &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] =3D &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] =3D &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] =3D &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3D &gcc_ufs_phy_unipro_core_clk_src.cl= kr, + [GCC_USB20_MASTER_CLK] =3D &gcc_usb20_master_clk.clkr, + [GCC_USB20_MASTER_CLK_SRC] =3D &gcc_usb20_master_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_CLK] =3D &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK_SRC] =3D &gcc_usb20_mock_utmi_clk_src.clkr, + [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb20_mock_utmi_postdiv_cl= k_src.clkr, + [GCC_USB20_SLEEP_CLK] =3D &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_MP_MASTER_CLK] =3D &gcc_usb30_mp_master_clk.clkr, + [GCC_USB30_MP_MASTER_CLK_SRC] =3D &gcc_usb30_mp_master_clk_src.clkr, + [GCC_USB30_MP_MOCK_UTMI_CLK] =3D &gcc_usb30_mp_mock_utmi_clk.clkr, + [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_mp_mock_utmi_clk_src.clkr, + [GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_mp_mock_utmi_post= div_clk_src.clkr, + [GCC_USB30_MP_SLEEP_CLK] =3D &gcc_usb30_mp_sleep_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] =3D &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_clk_src.= clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_prim_mock_utmi_= postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] =3D &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB30_SEC_MASTER_CLK] =3D &gcc_usb30_sec_master_clk.clkr, + [GCC_USB30_SEC_MASTER_CLK_SRC] =3D &gcc_usb30_sec_master_clk_src.clkr, + [GCC_USB30_SEC_MOCK_UTMI_CLK] =3D &gcc_usb30_sec_mock_utmi_clk.clkr, + [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_sec_mock_utmi_clk_src.cl= kr, + [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_sec_mock_utmi_po= stdiv_clk_src.clkr, + [GCC_USB30_SEC_SLEEP_CLK] =3D &gcc_usb30_sec_sleep_clk.clkr, + [GCC_USB30_TERT_MASTER_CLK] =3D &gcc_usb30_tert_master_clk.clkr, + [GCC_USB30_TERT_MASTER_CLK_SRC] =3D &gcc_usb30_tert_master_clk_src.clkr, + [GCC_USB30_TERT_MOCK_UTMI_CLK] =3D &gcc_usb30_tert_mock_utmi_clk.clkr, + [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_tert_mock_utmi_clk_src.= clkr, + [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_tert_mock_utmi_= postdiv_clk_src.clkr, + [GCC_USB30_TERT_SLEEP_CLK] =3D &gcc_usb30_tert_sleep_clk.clkr, + [GCC_USB3_MP_PHY_AUX_CLK] =3D &gcc_usb3_mp_phy_aux_clk.clkr, + [GCC_USB3_MP_PHY_AUX_CLK_SRC] =3D &gcc_usb3_mp_phy_aux_clk_src.clkr, + [GCC_USB3_MP_PHY_COM_AUX_CLK] =3D &gcc_usb3_mp_phy_com_aux_clk.clkr, + [GCC_USB3_MP_PHY_PIPE_0_CLK] =3D &gcc_usb3_mp_phy_pipe_0_clk.clkr, + [GCC_USB3_MP_PHY_PIPE_1_CLK] =3D &gcc_usb3_mp_phy_pipe_1_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] =3D &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] =3D &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] =3D &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] =3D &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_USB3_SEC_PHY_AUX_CLK] =3D &gcc_usb3_sec_phy_aux_clk.clkr, + [GCC_USB3_SEC_PHY_AUX_CLK_SRC] =3D &gcc_usb3_sec_phy_aux_clk_src.clkr, + [GCC_USB3_SEC_PHY_COM_AUX_CLK] =3D &gcc_usb3_sec_phy_com_aux_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK] =3D &gcc_usb3_sec_phy_pipe_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_sec_phy_pipe_clk_src.clkr, + [GCC_USB3_TERT_PHY_AUX_CLK] =3D &gcc_usb3_tert_phy_aux_clk.clkr, + [GCC_USB3_TERT_PHY_AUX_CLK_SRC] =3D &gcc_usb3_tert_phy_aux_clk_src.clkr, + [GCC_USB3_TERT_PHY_COM_AUX_CLK] =3D &gcc_usb3_tert_phy_com_aux_clk.clkr, + [GCC_USB3_TERT_PHY_PIPE_CLK] =3D &gcc_usb3_tert_phy_pipe_clk.clkr, + [GCC_USB3_TERT_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_tert_phy_pipe_clk_src.clkr, + [GCC_USB4_0_CFG_AHB_CLK] =3D &gcc_usb4_0_cfg_ahb_clk.clkr, + [GCC_USB4_0_DP0_CLK] =3D &gcc_usb4_0_dp0_clk.clkr, + [GCC_USB4_0_DP1_CLK] =3D &gcc_usb4_0_dp1_clk.clkr, + [GCC_USB4_0_MASTER_CLK] =3D &gcc_usb4_0_master_clk.clkr, + [GCC_USB4_0_MASTER_CLK_SRC] =3D &gcc_usb4_0_master_clk_src.clkr, + [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_0_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_0_phy_pcie_pipe_clk.clkr, + [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_0_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_0_PHY_RX0_CLK] =3D &gcc_usb4_0_phy_rx0_clk.clkr, + [GCC_USB4_0_PHY_RX1_CLK] =3D &gcc_usb4_0_phy_rx1_clk.clkr, + [GCC_USB4_0_PHY_USB_PIPE_CLK] =3D &gcc_usb4_0_phy_usb_pipe_clk.clkr, + [GCC_USB4_0_SB_IF_CLK] =3D &gcc_usb4_0_sb_if_clk.clkr, + [GCC_USB4_0_SB_IF_CLK_SRC] =3D &gcc_usb4_0_sb_if_clk_src.clkr, + [GCC_USB4_0_SYS_CLK] =3D &gcc_usb4_0_sys_clk.clkr, + [GCC_USB4_0_TMU_CLK] =3D &gcc_usb4_0_tmu_clk.clkr, + [GCC_USB4_0_TMU_CLK_SRC] =3D &gcc_usb4_0_tmu_clk_src.clkr, + [GCC_USB4_1_CFG_AHB_CLK] =3D &gcc_usb4_1_cfg_ahb_clk.clkr, + [GCC_USB4_1_DP0_CLK] =3D &gcc_usb4_1_dp0_clk.clkr, + [GCC_USB4_1_DP1_CLK] =3D &gcc_usb4_1_dp1_clk.clkr, + [GCC_USB4_1_MASTER_CLK] =3D &gcc_usb4_1_master_clk.clkr, + [GCC_USB4_1_MASTER_CLK_SRC] =3D &gcc_usb4_1_master_clk_src.clkr, + [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_1_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_1_phy_pcie_pipe_clk.clkr, + [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_1_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_1_PHY_RX0_CLK] =3D &gcc_usb4_1_phy_rx0_clk.clkr, + [GCC_USB4_1_PHY_RX1_CLK] =3D &gcc_usb4_1_phy_rx1_clk.clkr, + [GCC_USB4_1_PHY_USB_PIPE_CLK] =3D &gcc_usb4_1_phy_usb_pipe_clk.clkr, + [GCC_USB4_1_SB_IF_CLK] =3D &gcc_usb4_1_sb_if_clk.clkr, + [GCC_USB4_1_SB_IF_CLK_SRC] =3D &gcc_usb4_1_sb_if_clk_src.clkr, + [GCC_USB4_1_SYS_CLK] =3D &gcc_usb4_1_sys_clk.clkr, + [GCC_USB4_1_TMU_CLK] =3D &gcc_usb4_1_tmu_clk.clkr, + [GCC_USB4_1_TMU_CLK_SRC] =3D &gcc_usb4_1_tmu_clk_src.clkr, + [GCC_USB4_2_CFG_AHB_CLK] =3D &gcc_usb4_2_cfg_ahb_clk.clkr, + [GCC_USB4_2_DP0_CLK] =3D &gcc_usb4_2_dp0_clk.clkr, + [GCC_USB4_2_DP1_CLK] =3D &gcc_usb4_2_dp1_clk.clkr, + [GCC_USB4_2_MASTER_CLK] =3D &gcc_usb4_2_master_clk.clkr, + [GCC_USB4_2_MASTER_CLK_SRC] =3D &gcc_usb4_2_master_clk_src.clkr, + [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_2_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_2_phy_pcie_pipe_clk.clkr, + [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_2_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_2_PHY_RX0_CLK] =3D &gcc_usb4_2_phy_rx0_clk.clkr, + [GCC_USB4_2_PHY_RX1_CLK] =3D &gcc_usb4_2_phy_rx1_clk.clkr, + [GCC_USB4_2_PHY_USB_PIPE_CLK] =3D &gcc_usb4_2_phy_usb_pipe_clk.clkr, + [GCC_USB4_2_SB_IF_CLK] =3D &gcc_usb4_2_sb_if_clk.clkr, + [GCC_USB4_2_SB_IF_CLK_SRC] =3D &gcc_usb4_2_sb_if_clk_src.clkr, + [GCC_USB4_2_SYS_CLK] =3D &gcc_usb4_2_sys_clk.clkr, + [GCC_USB4_2_TMU_CLK] =3D &gcc_usb4_2_tmu_clk.clkr, + [GCC_USB4_2_TMU_CLK_SRC] =3D &gcc_usb4_2_tmu_clk_src.clkr, + [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_AXI1_CLK] =3D &gcc_video_axi1_clk.clkr, +}; + +static struct gdsc *gcc_sc8380xp_gdscs[] =3D { + [GCC_PCIE_0_TUNNEL_GDSC] =3D &gcc_pcie_0_tunnel_gdsc, + [GCC_PCIE_1_TUNNEL_GDSC] =3D &gcc_pcie_1_tunnel_gdsc, + [GCC_PCIE_2_TUNNEL_GDSC] =3D &gcc_pcie_2_tunnel_gdsc, + [GCC_PCIE_3_GDSC] =3D &gcc_pcie_3_gdsc, + [GCC_PCIE_3_PHY_GDSC] =3D &gcc_pcie_3_phy_gdsc, + [GCC_PCIE_4_GDSC] =3D &gcc_pcie_4_gdsc, + [GCC_PCIE_4_PHY_GDSC] =3D &gcc_pcie_4_phy_gdsc, + [GCC_PCIE_5_GDSC] =3D &gcc_pcie_5_gdsc, + [GCC_PCIE_5_PHY_GDSC] =3D &gcc_pcie_5_phy_gdsc, + [GCC_PCIE_6_PHY_GDSC] =3D &gcc_pcie_6_phy_gdsc, + [GCC_PCIE_6A_GDSC] =3D &gcc_pcie_6a_gdsc, + [GCC_PCIE_6B_GDSC] =3D &gcc_pcie_6b_gdsc, + [GCC_UFS_MEM_PHY_GDSC] =3D &gcc_ufs_mem_phy_gdsc, + [GCC_UFS_PHY_GDSC] =3D &gcc_ufs_phy_gdsc, + [GCC_USB20_PRIM_GDSC] =3D &gcc_usb20_prim_gdsc, + [GCC_USB30_MP_GDSC] =3D &gcc_usb30_mp_gdsc, + [GCC_USB30_PRIM_GDSC] =3D &gcc_usb30_prim_gdsc, + [GCC_USB30_SEC_GDSC] =3D &gcc_usb30_sec_gdsc, + [GCC_USB30_TERT_GDSC] =3D &gcc_usb30_tert_gdsc, + [GCC_USB3_MP_SS0_PHY_GDSC] =3D &gcc_usb3_mp_ss0_phy_gdsc, + [GCC_USB3_MP_SS1_PHY_GDSC] =3D &gcc_usb3_mp_ss1_phy_gdsc, + [GCC_USB4_0_GDSC] =3D &gcc_usb4_0_gdsc, + [GCC_USB4_1_GDSC] =3D &gcc_usb4_1_gdsc, + [GCC_USB4_2_GDSC] =3D &gcc_usb4_2_gdsc, + [GCC_USB_0_PHY_GDSC] =3D &gcc_usb_0_phy_gdsc, + [GCC_USB_1_PHY_GDSC] =3D &gcc_usb_1_phy_gdsc, + [GCC_USB_2_PHY_GDSC] =3D &gcc_usb_2_phy_gdsc, +}; + +static const struct qcom_reset_map gcc_sc8380xp_resets[] =3D { + [GCC_AV1E_BCR] =3D { 0x4a000 }, + [GCC_CAMERA_BCR] =3D { 0x26000 }, + [GCC_DISPLAY_BCR] =3D { 0x27000 }, + [GCC_GPU_BCR] =3D { 0x71000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] =3D { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] =3D { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] =3D { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] =3D { 0x6c028 }, + [GCC_PCIE_0_TUNNEL_BCR] =3D { 0xa0000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] =3D { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] =3D { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] =3D { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] =3D { 0x8e024 }, + [GCC_PCIE_1_TUNNEL_BCR] =3D { 0x2c000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] =3D { 0xa5014 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] =3D { 0xa5020 }, + [GCC_PCIE_2_PHY_BCR] =3D { 0xa501c }, + [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] =3D { 0xa5028 }, + [GCC_PCIE_2_TUNNEL_BCR] =3D { 0x13000 }, + [GCC_PCIE_3_BCR] =3D { 0x58000 }, + [GCC_PCIE_3_LINK_DOWN_BCR] =3D { 0xab014 }, + [GCC_PCIE_3_NOCSR_COM_PHY_BCR] =3D { 0xab020 }, + [GCC_PCIE_3_PHY_BCR] =3D { 0xab01c }, + [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] =3D { 0xab024 }, + [GCC_PCIE_4_BCR] =3D { 0x6b000 }, + [GCC_PCIE_4_LINK_DOWN_BCR] =3D { 0xb3014 }, + [GCC_PCIE_4_NOCSR_COM_PHY_BCR] =3D { 0xb3020 }, + [GCC_PCIE_4_PHY_BCR] =3D { 0xb301c }, + [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] =3D { 0xb3028 }, + [GCC_PCIE_5_BCR] =3D { 0x2f000 }, + [GCC_PCIE_5_LINK_DOWN_BCR] =3D { 0xaa014 }, + [GCC_PCIE_5_NOCSR_COM_PHY_BCR] =3D { 0xaa020 }, + [GCC_PCIE_5_PHY_BCR] =3D { 0xaa01c }, + [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] =3D { 0xaa028 }, + [GCC_PCIE_6A_BCR] =3D { 0x31000 }, + [GCC_PCIE_6A_LINK_DOWN_BCR] =3D { 0xac014 }, + [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] =3D { 0xac020 }, + [GCC_PCIE_6A_PHY_BCR] =3D { 0xac01c }, + [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] =3D { 0xac024 }, + [GCC_PCIE_6B_BCR] =3D { 0x8d000 }, + [GCC_PCIE_6B_LINK_DOWN_BCR] =3D { 0xb5014 }, + [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] =3D { 0xb5020 }, + [GCC_PCIE_6B_PHY_BCR] =3D { 0xb501c }, + [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] =3D { 0xb5024 }, + [GCC_PCIE_PHY_BCR] =3D { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x6f010 }, + [GCC_PCIE_RSCC_BCR] =3D { 0xa4000 }, + [GCC_PDM_BCR] =3D { 0x33000 }, + [GCC_QUPV3_WRAPPER_0_BCR] =3D { 0x42000 }, + [GCC_QUPV3_WRAPPER_1_BCR] =3D { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] =3D { 0x1e000 }, + [GCC_QUSB2PHY_HS0_MP_BCR] =3D { 0x1200c }, + [GCC_QUSB2PHY_HS1_MP_BCR] =3D { 0x12010 }, + [GCC_QUSB2PHY_PRIM_BCR] =3D { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] =3D { 0x12004 }, + [GCC_QUSB2PHY_TERT_BCR] =3D { 0x12008 }, + [GCC_QUSB2PHY_USB20_HS_BCR] =3D { 0x12014 }, + [GCC_SDCC2_BCR] =3D { 0x14000 }, + [GCC_SDCC4_BCR] =3D { 0x16000 }, + [GCC_UFS_PHY_BCR] =3D { 0x77000 }, + [GCC_USB20_PRIM_BCR] =3D { 0x29000 }, + [GCC_USB30_MP_BCR] =3D { 0x17000 }, + [GCC_USB30_PRIM_BCR] =3D { 0x39000 }, + [GCC_USB30_SEC_BCR] =3D { 0xa1000 }, + [GCC_USB30_TERT_BCR] =3D { 0xa2000 }, + [GCC_USB3_MP_SS0_PHY_BCR] =3D { 0x19008 }, + [GCC_USB3_MP_SS1_PHY_BCR] =3D { 0x54008 }, + [GCC_USB3_PHY_PRIM_BCR] =3D { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] =3D { 0x2a000 }, + [GCC_USB3_PHY_TERT_BCR] =3D { 0xa3000 }, + [GCC_USB3_UNIPHY_MP0_BCR] =3D { 0x19000 }, + [GCC_USB3_UNIPHY_MP1_BCR] =3D { 0x54000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x2a004 }, + [GCC_USB3PHY_PHY_TERT_BCR] =3D { 0xa3004 }, + [GCC_USB3UNIPHY_PHY_MP0_BCR] =3D { 0x19004 }, + [GCC_USB3UNIPHY_PHY_MP1_BCR] =3D { 0x54004 }, + [GCC_USB4_0_BCR] =3D { 0x9f000 }, + [GCC_USB4_0_DP0_PHY_PRIM_BCR] =3D { 0x50010 }, + [GCC_USB4_1_DP0_PHY_SEC_BCR] =3D { 0x2a010 }, + [GCC_USB4_2_DP0_PHY_TERT_BCR] =3D { 0xa3010 }, + [GCC_USB4_1_BCR] =3D { 0x2b000 }, + [GCC_USB4_2_BCR] =3D { 0x11000 }, + [GCC_USB_0_PHY_BCR] =3D { 0x50020 }, + [GCC_USB_1_PHY_BCR] =3D { 0x2a020 }, + [GCC_USB_2_PHY_BCR] =3D { 0xa3020 }, + [GCC_VIDEO_BCR] =3D { 0x32000 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src), +}; + +static const struct regmap_config gcc_sc8380xp_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_sc8380xp_desc =3D { + .config =3D &gcc_sc8380xp_regmap_config, + .clks =3D gcc_sc8380xp_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sc8380xp_clocks), + .resets =3D gcc_sc8380xp_resets, + .num_resets =3D ARRAY_SIZE(gcc_sc8380xp_resets), + .gdscs =3D gcc_sc8380xp_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sc8380xp_gdscs), +}; + +static const struct of_device_id gcc_sc8380xp_match_table[] =3D { + { .compatible =3D "qcom,sc8380xp-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sc8380xp_match_table); + +static int gcc_sc8380xp_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_sc8380xp_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + /* + * Keep the critical clock always-On + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, + * gcc_video_xo_clk + */ + regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); + + /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ + regmap_write(regmap, 0x52224, 0x0); + + return qcom_cc_really_probe(pdev, &gcc_sc8380xp_desc, regmap); +} + +static struct platform_driver gcc_sc8380xp_driver =3D { + .probe =3D gcc_sc8380xp_probe, + .driver =3D { + .name =3D "gcc-sc8380xp", + .of_match_table =3D gcc_sc8380xp_match_table, + }, +}; + +static int __init gcc_sc8380xp_init(void) +{ + return platform_driver_register(&gcc_sc8380xp_driver); +} +subsys_initcall(gcc_sc8380xp_init); + +static void __exit gcc_sc8380xp_exit(void) +{ + platform_driver_unregister(&gcc_sc8380xp_driver); +} +module_exit(gcc_sc8380xp_exit); + +MODULE_DESCRIPTION("QTI GCC SC8380XP Driver"); +MODULE_LICENSE("GPL"); --=20 2.17.1 From nobody Thu Dec 18 05:19:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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verify=NOT); Wed, 25 Oct 2023 13:34:26 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 06:34:20 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , , , Sibi Sankar Subject: [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP Date: Wed, 25 Oct 2023 19:03:19 +0530 Message-ID: <20231025133320.4720-4-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231025133320.4720-1-quic_sibis@quicinc.com> References: <20231025133320.4720-1-quic_sibis@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Euqkb6PwFM3Yq0KQAOK2JpmAJb_f8hi- X-Proofpoint-ORIG-GUID: Euqkb6PwFM3Yq0KQAOK2JpmAJb_f8hi- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_02,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=809 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250118 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rajendra Nayak Add bindings and update documentation for clock rpmh driver on SC8380XP SoCs. Signed-off-by: Rajendra Nayak Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Doc= umentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 4eb5e59f6772..b1faf99b75c6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -23,6 +23,7 @@ properties: - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk - qcom,sc8280xp-rpmh-clk + - qcom,sc8380xp-rpmh-clk - qcom,sdm670-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk --=20 2.17.1 From nobody Thu Dec 18 05:19:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9B9BC07545 for ; Wed, 25 Oct 2023 13:34:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344609AbjJYNen (ORCPT ); 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charset="utf-8" From: Rajendra Nayak Adds the RPMH clocks present in SC8380XP SoC Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Rajendra Nayak Signed-off-by: Sibi Sankar Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 5d853fd43294..7f6d5f98957b 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -372,6 +372,9 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); =20 +DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2); +DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2); +DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2); DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); @@ -737,6 +740,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 =3D { .num_clks =3D ARRAY_SIZE(sm4450_rpmh_clocks), }; =20 +static struct clk_hw *sc8380xp_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] =3D &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] =3D &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] =3D &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] =3D &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK3] =3D &clk_rpmh_clk3_a2.hw, + [RPMH_RF_CLK3_A] =3D &clk_rpmh_clk3_a2_ao.hw, + [RPMH_RF_CLK4] =3D &clk_rpmh_clk4_a2.hw, + [RPMH_RF_CLK4_A] =3D &clk_rpmh_clk4_a2_ao.hw, + [RPMH_RF_CLK5] =3D &clk_rpmh_clk5_a2.hw, + [RPMH_RF_CLK5_A] =3D &clk_rpmh_clk5_a2_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sc8380xp =3D { + .clks =3D sc8380xp_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(sc8380xp_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -825,6 +850,7 @@ static const struct of_device_id clk_rpmh_match_table[]= =3D { { .compatible =3D "qcom,sc7180-rpmh-clk", .data =3D &clk_rpmh_sc7180}, { .compatible =3D "qcom,sc8180x-rpmh-clk", .data =3D &clk_rpmh_sc8180x}, { .compatible =3D "qcom,sc8280xp-rpmh-clk", .data =3D &clk_rpmh_sc8280xp}, + { .compatible =3D "qcom,sc8380xp-rpmh-clk", .data =3D &clk_rpmh_sc8380xp}, { .compatible =3D "qcom,sdm845-rpmh-clk", .data =3D &clk_rpmh_sdm845}, { .compatible =3D "qcom,sdm670-rpmh-clk", .data =3D &clk_rpmh_sdm670}, { .compatible =3D "qcom,sdx55-rpmh-clk", .data =3D &clk_rpmh_sdx55}, --=20 2.17.1