From nobody Wed Dec 17 12:57:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A683C0032E for ; Wed, 25 Oct 2023 13:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344368AbjJYNAq (ORCPT ); Wed, 25 Oct 2023 09:00:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344307AbjJYNAm (ORCPT ); Wed, 25 Oct 2023 09:00:42 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 713D1C1 for ; Wed, 25 Oct 2023 06:00:40 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6b89ab5ddb7so5651742b3a.0 for ; Wed, 25 Oct 2023 06:00:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698238840; x=1698843640; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qBEwFvY7A0Gjt/uGwV7Ad9RZEpWO878DTXchrP8q7sQ=; b=EEhz0UMDkhZ2eOmZeQjckv8P5v377syHwE/1UgnQjaLQoEtkhbafzWUYT5wiYeVlD8 eHbD3yFHe7Zao93woWsrQ7LycLi+Koq6DHIHRSoUenSWy83uS4eykUphw0A+vxKkafgm GDUL3A3DQq/vvtN/T/Kido7s8G88GMhKueCCvlAAWiZFTnyaWdYAZJ2tjlgl/hBLMAmc PioDvAzsxScPRLJjbwYx2NqgJS3uqYxJmVFTfUQiuQRg4TqEol6KUvy5cCxhgqUIY916 spFzLiX+lVoMBLHAdetuSeyE+GT0XonoXybsvao+cWQUroA7hxj477VQfG8dAUNJ939h xTJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698238840; x=1698843640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qBEwFvY7A0Gjt/uGwV7Ad9RZEpWO878DTXchrP8q7sQ=; b=jhn2SCrDmqPH72pZ8XUGKWDAfAA+/78hpb7uuBvQ+ZxoD+uKcWcacAXT0CZ9heKPw2 E65OB9fO7rnMls5QRgDzQscVuykt8N+ik4U7VaCHIuOxrBgMAzmq2VLo3cpSVmKHrbmc cow0NgVQu9vSgzMzNF5kQvAVU1g357tLQXuy0fwpk0+R798rKfsRcFe2xfAivrKrPtW0 ebTVJPVhIo3ljttUU/RzW9BgzlaoTaozb30LmUFDRMs/BOmSjKyffqcXUO5k1WVcm0aC aIS/RpUgM38ODfLm7vtiyM4fx/21KGglBGI0EtG+jhcRXpfPFxZzbQBUiSiu+TZYs0VJ yuXQ== X-Gm-Message-State: AOJu0Yw4A64pqbHJDpG/flgNizQm3SOShm3BRnmCCA2FHoRDzCd0ecvL si2JWTPrsxW2yQ9qS45LVWoF X-Google-Smtp-Source: AGHT+IEVkUngxZRdSdjSL45GkWy53SYUx/kkkQQJqxN8PbAX2hJu8E/SqYXD38Jqrf69Wz2Bmuv59Q== X-Received: by 2002:a05:6a21:778d:b0:16b:8498:d9bc with SMTP id bd13-20020a056a21778d00b0016b8498d9bcmr5327839pzc.62.1698238839655; Wed, 25 Oct 2023 06:00:39 -0700 (PDT) Received: from localhost.localdomain ([103.28.246.120]) by smtp.gmail.com with ESMTPSA id n11-20020aa7984b000000b00690d4464b95sm9616304pfq.16.2023.10.25.06.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 06:00:39 -0700 (PDT) From: Manivannan Sadhasivam To: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_bjorande@quicinc.com, fancer.lancer@gmail.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 1/1] PCI: qcom-ep: Implement write_dbi2() callback for writing DBI2 registers properly Date: Wed, 25 Oct 2023 18:30:29 +0530 Message-Id: <20231025130029.74693-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231025130029.74693-1-manivannan.sadhasivam@linaro.org> References: <20231025130029.74693-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DWC core driver exposes the write_dbi2() callback for writing to the DBI2 registers in a vendor specific way. On the Qcom EP plaforms, DBI_CS2 bit in the ELBI region needs to be asserted before writing to any DBI2 registers and deasserted once done. So let's implement the callback for the Qcom PCIe EP driver so that the DBI2 writes are handled properly in the hardware. Without this callback, DBI2 register writes like BAR size won't go through and as a result, the default BAR size is set for all BARs. Cc: stable@vger.kernel.org # 5.16+ Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller d= river") Suggested-by: Serge Semin Signed-off-by: Manivannan Sadhasivam Reviewed-by: Serge Semin --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 32c8d9e37876..7da0599f70e7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -124,6 +124,7 @@ =20 /* ELBI registers */ #define ELBI_SYS_STTS 0x08 +#define ELBI_CS2_ENABLE 0xa4 =20 /* DBI registers */ #define DBI_CON_STATUS 0x44 @@ -262,6 +263,21 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } =20 +static void qcom_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct qcom_pcie_ep *pcie_ep =3D to_pcie_ep(pci); + int ret; + + writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE); + + ret =3D dw_pcie_write(pci->dbi_base2 + reg, size, val); + if (ret) + dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret= ); + + writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE); +} + static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci =3D &pcie_ep->pci; @@ -500,6 +516,7 @@ static const struct dw_pcie_ops pci_ops =3D { .link_up =3D qcom_pcie_dw_link_up, .start_link =3D qcom_pcie_dw_start_link, .stop_link =3D qcom_pcie_dw_stop_link, + .write_dbi2 =3D qcom_pcie_write_dbi2, }; =20 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev, --=20 2.25.1