From nobody Fri Sep 20 09:43:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16701C07545 for ; Tue, 24 Oct 2023 13:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbjJXNCz (ORCPT ); Tue, 24 Oct 2023 09:02:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234547AbjJXNBL (ORCPT ); Tue, 24 Oct 2023 09:01:11 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A31110D7; Tue, 24 Oct 2023 06:01:07 -0700 (PDT) X-UUID: 5f3fae10726d11eea33bb35ae8d461a2-20231024 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=yXPKqi+EJx+hFEBjGUNkwptQPNfgosBQdZuUgrEhk/U=; b=s5n4Gb+6EGL7lj2wYBFrMUotYkoQhCTcMavyvKUrkGq1UIm3KT4RzZYl7IewTCX6+7GHvcAPNpkik9/xbVU6difWyuTg1gvSXq38gHDx223YJOBzlrKDnCSOREI8VEDXL/E2S+v8SE7XWQ6NMLey3ETEIZGrACCCmAxcPGLUR8s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:12b34fe5-6f5e-4ea2-a35e-4c75994ef601,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:c7c4da28-cb22-4fa7-8134-287af20ad1fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 5f3fae10726d11eea33bb35ae8d461a2-20231024 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1175345767; Tue, 24 Oct 2023 21:00:57 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 24 Oct 2023 21:00:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 24 Oct 2023 21:00:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , Hsiao Chien Sung , "Jason-JH . Lin" , Nathan Lu , , , , , Subject: [PATCH v11 19/23] drm/mediatek: Add Padding to OVL adaptor Date: Tue, 24 Oct 2023 21:00:44 +0800 Message-ID: <20231024130048.14749-20-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231024130048.14749-1-shawn.sung@mediatek.com> References: <20231024130048.14749-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 Padding to OVL adaptor to probe the driver. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index df6e6cb0a9ef..10d23e76acaa 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type { OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_MDP_RDMA, OVL_ADAPTOR_TYPE_MERGE, + OVL_ADAPTOR_TYPE_PADDING, OVL_ADAPTOR_TYPE_NUM, }; @@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id { OVL_ADAPTOR_MERGE1, OVL_ADAPTOR_MERGE2, OVL_ADAPTOR_MERGE3, + OVL_ADAPTOR_PADDING0, + OVL_ADAPTOR_PADDING1, + OVL_ADAPTOR_PADDING2, + OVL_ADAPTOR_PADDING3, + OVL_ADAPTOR_PADDING4, + OVL_ADAPTOR_PADDING5, + OVL_ADAPTOR_PADDING6, + OVL_ADAPTOR_PADDING7, OVL_ADAPTOR_ID_MAX }; @@ -66,6 +75,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_T= YPE_NUM] =3D { [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", + [OVL_ADAPTOR_TYPE_PADDING] =3D "padding", }; static const struct mtk_ddp_comp_funcs ethdr =3D { @@ -80,6 +90,13 @@ static const struct mtk_ddp_comp_funcs merge =3D { .clk_disable =3D mtk_merge_clk_disable, }; +static const struct mtk_ddp_comp_funcs padding =3D { + .clk_enable =3D mtk_padding_clk_enable, + .clk_disable =3D mtk_padding_clk_disable, + .start =3D mtk_padding_start, + .stop =3D mtk_padding_stop, +}; + static const struct mtk_ddp_comp_funcs rdma =3D { .power_on =3D mtk_mdp_rdma_power_on, .power_off =3D mtk_mdp_rdma_power_off, @@ -101,6 +118,14 @@ static const struct ovl_adaptor_comp_match comp_matche= s[OVL_ADAPTOR_ID_MAX] =3D { [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &merge }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &merge }, [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &merge }, + [OVL_ADAPTOR_PADDING0] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING0, 0, &padding }, + [OVL_ADAPTOR_PADDING1] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING1, 1, &padding }, + [OVL_ADAPTOR_PADDING2] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING2, 2, &padding }, + [OVL_ADAPTOR_PADDING3] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING3, 3, &padding }, + [OVL_ADAPTOR_PADDING4] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING4, 4, &padding }, + [OVL_ADAPTOR_PADDING5] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING5, 5, &padding }, + [OVL_ADAPTOR_PADDING6] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING6, 6, &padding }, + [OVL_ADAPTOR_PADDING7] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING7, 7, &padding }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -436,6 +461,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, = struct device_node *node, } static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { + { .compatible =3D "mediatek,mt8188-disp-padding", .data =3D (void *)OVL_A= DAPTOR_TYPE_PADDING }, { .compatible =3D "mediatek,mt8195-disp-ethdr", .data =3D (void *)OVL_ADA= PTOR_TYPE_ETHDR }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADA= PTOR_TYPE_MERGE }, { .compatible =3D "mediatek,mt8195-vdo1-rdma", .data =3D (void *)OVL_ADAP= TOR_TYPE_MDP_RDMA }, -- 2.18.0