From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89A35C07545 for ; Tue, 24 Oct 2023 13:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234480AbjJXNUs (ORCPT ); Tue, 24 Oct 2023 09:20:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234421AbjJXNUk (ORCPT ); Tue, 24 Oct 2023 09:20:40 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C17C12C for ; Tue, 24 Oct 2023 06:20:33 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-507b96095abso6656717e87.3 for ; Tue, 24 Oct 2023 06:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698153632; x=1698758432; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UT552xSRxg7vfw/B4jlHzjbiGIGKhdCrIlQ9lB9ogSk=; b=RS6oO+kOF6nFFUVyLqUXSibAbxFVFD2hlRtuAZmm5qt2pu+qY5uBmBvWge6Dos0uDr 4CtOsOImZWm1DeRwDfsVlV8eiKIKskzDay04kBVtIIOv81jIhU+7FgKLtjFZ8x9PeEfN VK6xhrdVk15l4GIpzzZCU5Vl+Pd9wfEYgQXyyP2IihEHDfJ0ST8cpc3QpVjHDMFphJc2 eluxCaR6YYRBznfJrluPosuTuEBQgdKQWOe/TlJKv4xrCZEKewbSCE0t2IQctjBayRcg ICT+FSUc5yi6CbyJuL8U+cDuu4WqSULFW4pAQJyrq/tLdG3ulXrM+ISVFOTh9Iv9aQFt J5Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698153632; x=1698758432; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UT552xSRxg7vfw/B4jlHzjbiGIGKhdCrIlQ9lB9ogSk=; b=xA0vpAX2MbHhWbIgRHrILauw0KL3K2hmrTBj/shuTpNZYl0zzrMVbcjpnVrPlqH9o4 Bhvij4BRvJNkLY11RkYHSfMlo/A2GmsyV9ML+/0InNeNvV+zurTMSPuVthhGxlmVMFNV VFdo/ct0Oi5tgOGffVWcTlWn1gNOeS2BmHURZb8w3/1ByxEFzjbMvDGGij+knFujX5Zw K5/xnlb8n8HFybpK6/3IvY6Al33pnGaZ/0jgK4917sX3z6zsQ2AhwzIvQ8VvDUlccvVk ahS2D2p3tQuugN/Aueqvyl8T8+mFldkzPlraVAgppw/ENqE5f7szeJMZlS2zu+bnB+tP hURw== X-Gm-Message-State: AOJu0YywWszPQjwZeXYQ9yMg2qwGpDa1g2nuKWWQ/gOwOd0eAT2KQD8j 8oYr6KXjPemAkXJDWWF8W8qhzw== X-Google-Smtp-Source: AGHT+IEj+KMeONE10q/gquHsR7jOzyg2PFLfGY6LK/CyGvVzrP9Ev1G3Y33qwldjE7BWxEeoNM6aWg== X-Received: by 2002:a05:6512:4016:b0:508:1178:efa4 with SMTP id br22-20020a056512401600b005081178efa4mr188587lfb.55.1698153631805; Tue, 24 Oct 2023 06:20:31 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id d5-20020a193845000000b00507ab956ab9sm2147365lfj.147.2023.10.24.06.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 06:20:31 -0700 (PDT) From: Linus Walleij Date: Tue, 24 Oct 2023 15:20:27 +0200 Subject: [PATCH net-next v7 1/7] dt-bindings: net: dsa: Require ports or ethernet-ports MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-1-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij , Rob Herring X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Bindings using dsa.yaml#/$defs/ethernet-ports specify that a DSA switch node need to have a ports or ethernet-ports subnode, and that is actually required, so add requirements using oneOf. Suggested-by: Rob Herring Signed-off-by: Linus Walleij Acked-by: Florian Fainelli Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/net/dsa/dsa.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documenta= tion/devicetree/bindings/net/dsa/dsa.yaml index 6107189d276a..2abd036578d1 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -46,4 +46,10 @@ $defs: $ref: dsa-port.yaml# unevaluatedProperties: false =20 +oneOf: + - required: + - ports + - required: + - ethernet-ports + ... --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D52BC07545 for ; Tue, 24 Oct 2023 13:20:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234459AbjJXNUp (ORCPT ); Tue, 24 Oct 2023 09:20:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234418AbjJXNUk (ORCPT ); Tue, 24 Oct 2023 09:20:40 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFAEFE8 for ; Tue, 24 Oct 2023 06:20:34 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-507b96095abso6656742e87.3 for ; Tue, 24 Oct 2023 06:20:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698153633; x=1698758433; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Q8dS0fiX8s3oTQdiSNWl2/6C6tud53gSSackCKtgSFY=; b=fgmuT7+7UTFWpHnkgEtCIHBht6rKqPuBKoAoHh173UC53GMZIa0G1kHHC+y3YasIaY IdzRe5zqZ1Tzzxdvf9Mnmw4BeLO4eA/9Gm3JYFX8k+3gX4wYrB1JqcITHMYPbgcYrywN 7kFieQYXcBXlot5wMsOsOE2P5YHuWHUQIvI8nKizxCDepPug715miP6rAbG8OiJX6x0A VeQ0uMzCZJnf8/X8ZEjxUg2MiYdSy7KjhV0UK1BHwxxg59Z+NIyXnUvyum5DtaTUyGlW lWQlpjEvE6yR6UFSWoocx/XZwbZ48iTDARuIaGl9KauBQIjCNNiIspECPio7Yu7a6JIK Kh/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698153633; x=1698758433; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q8dS0fiX8s3oTQdiSNWl2/6C6tud53gSSackCKtgSFY=; b=ouRSxXpz8j9RhfyMF6HCMxdvSYUAmzJT80udRrvDbZAdnOl4PRn+RP/gPIuotXclJA bbw6/uq4YpIhpRnZe7JJfwibHhuzKRDobCr3Qm0PvB/gSK8a9uyMh3WF27D+/8dmNQZx EVTGbocoRSemxc8kftI57Moa8TU0ZhwkR+7dn+qragYB1Kbz6IlIFFkFeGpz403yg1Js ZewilTB5X7X2RFRf/dlKs/Vlv1FS2kSJbOuEtIVTnpbs3Cm1dYn4TPN9qUAVMmXLhh+9 A3ImjV1CW14gHT0QE4pwWknImnxezkiUqFsY44BvRNcPmIHN34XOM37ULECd+/UWVda2 wSpg== X-Gm-Message-State: AOJu0YzWUgJVDMiomtZJhkJqNwI266Bdckv53+gOnurFoXdLcghPRTV4 ISK2l36HGdZ1BEK2goqKbPBLuw== X-Google-Smtp-Source: AGHT+IHMtXzw21flMwTEMR5C4A+qw3BxpCf34frnRqxgXOGfce6I7SN6Bq4PJJvbRwvYIl/PbOEf7A== X-Received: by 2002:a05:6512:4016:b0:508:1178:efa4 with SMTP id br22-20020a056512401600b005081178efa4mr188638lfb.55.1698153632957; Tue, 24 Oct 2023 06:20:32 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id d5-20020a193845000000b00507ab956ab9sm2147365lfj.147.2023.10.24.06.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 06:20:32 -0700 (PDT) From: Linus Walleij Date: Tue, 24 Oct 2023 15:20:28 +0200 Subject: [PATCH net-next v7 2/7] dt-bindings: net: mvusb: Fix up DSA example MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-2-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij , Vladimir Oltean , Rob Herring X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When adding a proper schema for the Marvell mx88e6xxx switch, the scripts start complaining about this embedded example: dtschema/dtc warnings/errors: net/marvell,mvusb.example.dtb: switch@0: ports: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.= yaml# net/marvell,mvusb.example.dtb: switch@0: ports: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.= yaml# Fix this up by extending the example with those properties in the ports node. While we are at it, rename "ports" to "ethernet-ports" and rename "switch" to "ethernet-switch" as this is recommended practice. Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- Documentation/devicetree/bindings/net/marvell,mvusb.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml b/Doc= umentation/devicetree/bindings/net/marvell,mvusb.yaml index 3a3325168048..ab838c1ffeed 100644 --- a/Documentation/devicetree/bindings/net/marvell,mvusb.yaml +++ b/Documentation/devicetree/bindings/net/marvell,mvusb.yaml @@ -50,11 +50,14 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch@0 { + ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; reg =3D <0x0>; =20 - ports { + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + /* Port definitions */ }; =20 --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03FAAC00A8F for ; Tue, 24 Oct 2023 13:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234553AbjJXNVC (ORCPT ); Tue, 24 Oct 2023 09:21:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234346AbjJXNUn (ORCPT ); Tue, 24 Oct 2023 09:20:43 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C9B5186 for ; Tue, 24 Oct 2023 06:20:36 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-507a3b8b113so6681039e87.0 for ; Tue, 24 Oct 2023 06:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698153634; x=1698758434; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JtzWop8mEc3XMcR0ZEd8QQd7a8Vp8IIddlLWcHlCccY=; b=oQnFkjmUGiVfGlphMKEjkx9YipNVFeo+nzCmgp/sWOtFYQIj1N9ykkxqSEd+Xc70fj YEz6t74Xaiz4cf08QJPFOQdnbA8NfhfMUEfGHZhRlUWAl3pezFlv816uaENZkdhv2kRB y8KKFxLXbcunLIRe301LgfzV7Ukd1SlwgBib/IaYWH4yGpouKQ8DjhPyApoaNn7C/AaO rNPNvLhkB88wd6b1uH8kRoa4YVySFxl5dVQpfC959D2lTJ1xDXqP4fWfWP1TGZtupCEz JX6qbOS3OCWOcP5Af75ljTfUq/Mc8R5gFfMVBPS12SA8J+fKdpuSmESR7ha9JUeKMpbT Rr0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698153634; x=1698758434; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JtzWop8mEc3XMcR0ZEd8QQd7a8Vp8IIddlLWcHlCccY=; b=xREYv1g6adb9L21yh62a5AJ7tGFLjNThTAHC1S0h1Il8mEV9JInK4IlVXShfP72sV0 L01z81oNcGJP3e25s0/gkLYwrvIf8Ir/MkmhLcZ2kBG+Y/sAKfFFjY3WcgUaT8XAXPg5 p44J0MlCPxWfPbnh4dJBr/X6sNGPvgWu7e+J63x/xrar4bf0naYKRo5fWtFmyf1YIkxI eK+XHhiEgPAvkbqrdSQilE5cIKybLewV8boWnzMaaoWmlR2eC1g3BoJjlzPEIMCe18RI W54tzjpMgOunQp3qTzw58Kg/Adf55JTcq6b2BhgbtN0QkpieaEVqSX0LjZpTVj0xUZOU EpVA== X-Gm-Message-State: AOJu0Yx1RHZhLpFgpdGb8hegOm5Cltl5Hc0kz20hcdRvYxMXzrYe+R6p SsTNdC6eChhZJaBLSbAVNmav7MUTfAiUf481Wvk= X-Google-Smtp-Source: AGHT+IFvgQ00HzQ6hx6Gx0R46iJIMvibY9TMrgCM1oX8qKlpnd3ih/mMuYpmOCws/xTMACTL8jJ4lg== X-Received: by 2002:a05:6512:6c4:b0:507:a04c:76eb with SMTP id u4-20020a05651206c400b00507a04c76ebmr11062230lff.35.1698153634144; Tue, 24 Oct 2023 06:20:34 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id d5-20020a193845000000b00507ab956ab9sm2147365lfj.147.2023.10.24.06.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 06:20:33 -0700 (PDT) From: Linus Walleij Date: Tue, 24 Oct 2023 15:20:29 +0200 Subject: [PATCH net-next v7 3/7] ARM: dts: marvell: Fix some common switch mistakes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-3-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix some errors in the Marvell MV88E6xxx switch descriptions: - The top node had no address size or cells. - switch0@0 is not OK, should be ethernet-switch@0. - The ports node should be named ethernet-ports - The ethernet-ports node should have port@0 etc children, no plural "ports" in the children. - Ports should be named ethernet-port@0 etc - PHYs should be named ethernet-phy@0 etc This serves as an example of fixes needed for introducing a schema for the bindings, but the patch can simply be applied. Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- arch/arm/boot/dts/marvell/armada-370-rd.dts | 24 ++++++------ .../dts/marvell/armada-381-netgear-gs110emx.dts | 44 +++++++++++-------= ---- .../dts/marvell/armada-385-clearfog-gtr-l8.dts | 38 +++++++++---------- .../dts/marvell/armada-385-clearfog-gtr-s4.dts | 22 +++++------ arch/arm/boot/dts/marvell/armada-385-linksys.dtsi | 18 ++++----- .../boot/dts/marvell/armada-385-turris-omnia.dts | 20 +++++----- arch/arm/boot/dts/marvell/armada-388-clearfog.dts | 20 +++++----- .../boot/dts/marvell/armada-xp-linksys-mamba.dts | 18 ++++----- 8 files changed, 96 insertions(+), 108 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-370-rd.dts b/arch/arm/boot/dt= s/marvell/armada-370-rd.dts index b459a670f615..1b241da11e94 100644 --- a/arch/arm/boot/dts/marvell/armada-370-rd.dts +++ b/arch/arm/boot/dts/marvell/armada-370-rd.dts @@ -149,39 +149,37 @@ led@0 { }; }; =20 - switch: switch@10 { + switch: ethernet-switch@10 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <0x10>; interrupt-controller; #interrupt-cells =3D <2>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "lan0"; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan1"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan3"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; ethernet =3D <ð1>; phy-mode =3D "rgmii-id"; @@ -196,25 +194,25 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switchphy0: switchphy@0 { + switchphy0: ethernet-phy@0 { reg =3D <0>; interrupt-parent =3D <&switch>; interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; }; =20 - switchphy1: switchphy@1 { + switchphy1: ethernet-phy@1 { reg =3D <1>; interrupt-parent =3D <&switch>; interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH>; }; =20 - switchphy2: switchphy@2 { + switchphy2: ethernet-phy@2 { reg =3D <2>; interrupt-parent =3D <&switch>; interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH>; }; =20 - switchphy3: switchphy@3 { + switchphy3: ethernet-phy@3 { reg =3D <3>; interrupt-parent =3D <&switch>; interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts b/ar= ch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts index f4c4b213ef4e..5baf83e5253d 100644 --- a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts @@ -77,51 +77,49 @@ &mdio { pinctrl-0 =3D <&mdio_pins>; status =3D "okay"; =20 - switch@0 { + ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; - #address-cells =3D <1>; #interrupt-cells =3D <2>; interrupt-controller; interrupt-parent =3D <&gpio1>; interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 =3D <&switch_interrupt_pins>; pinctrl-names =3D "default"; - #size-cells =3D <0>; reg =3D <0>; =20 mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; @@ -142,11 +140,11 @@ phy2: ethernet-phy@c { }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { ethernet =3D <ð0>; phy-mode =3D "rgmii"; reg =3D <0>; @@ -158,55 +156,55 @@ fixed-link { }; }; =20 - port@1 { + ethernet-port@1 { label =3D "lan1"; phy-handle =3D <&switch0phy1>; reg =3D <1>; }; =20 - port@2 { + ethernet-port@2 { label =3D "lan2"; phy-handle =3D <&switch0phy2>; reg =3D <2>; }; =20 - port@3 { + ethernet-port@3 { label =3D "lan3"; phy-handle =3D <&switch0phy3>; reg =3D <3>; }; =20 - port@4 { + ethernet-port@4 { label =3D "lan4"; phy-handle =3D <&switch0phy4>; reg =3D <4>; }; =20 - port@5 { + ethernet-port@5 { label =3D "lan5"; phy-handle =3D <&switch0phy5>; reg =3D <5>; }; =20 - port@6 { + ethernet-port@6 { label =3D "lan6"; phy-handle =3D <&switch0phy6>; reg =3D <6>; }; =20 - port@7 { + ethernet-port@7 { label =3D "lan7"; phy-handle =3D <&switch0phy7>; reg =3D <7>; }; =20 - port@8 { + ethernet-port@8 { label =3D "lan8"; phy-handle =3D <&switch0phy8>; reg =3D <8>; }; =20 - port@9 { + ethernet-port@9 { /* 88X3310P external phy */ label =3D "lan9"; phy-handle =3D <&phy1>; @@ -214,7 +212,7 @@ port@9 { reg =3D <9>; }; =20 - port@a { + ethernet-port@a { /* 88X3310P external phy */ label =3D "lan10"; phy-handle =3D <&phy2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arc= h/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1990f7d0cc79..1707d1b01545 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -7,66 +7,66 @@ / { }; =20 &mdio { - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible =3D "marvell,mv88e6190"; reg =3D <4>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cf_gtr_switch_reset_pins>; reset-gpios =3D <&gpio0 18 GPIO_ACTIVE_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan8"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan7"; phy-handle =3D <&switch0phy1>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan6"; phy-handle =3D <&switch0phy2>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan5"; phy-handle =3D <&switch0phy3>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "lan4"; phy-handle =3D <&switch0phy4>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "lan3"; phy-handle =3D <&switch0phy5>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <7>; label =3D "lan2"; phy-handle =3D <&switch0phy6>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <8>; label =3D "lan1"; phy-handle =3D <&switch0phy7>; }; =20 - port@10 { + ethernet-port@10 { reg =3D <10>; phy-mode =3D "2500base-x"; =20 @@ -83,35 +83,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@1 { + switch0phy0: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy1: switch0phy1@2 { + switch0phy1: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy2: switch0phy2@3 { + switch0phy2: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy3: switch0phy3@4 { + switch0phy3: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy4: switch0phy4@5 { + switch0phy4: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy5: switch0phy5@6 { + switch0phy5: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy6: switch0phy6@7 { + switch0phy6: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy7: switch0phy7@8 { + switch0phy7: ethernet-phy@8 { reg =3D <0x8>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arc= h/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index b795ad573891..a7678a784c18 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -11,42 +11,42 @@ &sfp0 { }; =20 &mdio { - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible =3D "marvell,mv88e6085"; reg =3D <4>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cf_gtr_switch_reset_pins>; reset-gpios =3D <&gpio0 18 GPIO_ACTIVE_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan2"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan4"; phy-handle =3D <&switch0phy2>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; phy-mode =3D "2500base-x"; ethernet =3D <ð1>; @@ -63,19 +63,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi b/arch/arm/b= oot/dts/marvell/armada-385-linksys.dtsi index fc8216fd9f60..4116ed60f709 100644 --- a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi @@ -158,42 +158,40 @@ nand: nand@0 { &mdio { status =3D "okay"; =20 - switch@0 { + ethernet-switch@0 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "lan4"; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan3"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan1"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "wan"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; phy-mode =3D "sgmii"; ethernet =3D <ð2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/a= rm/boot/dts/marvell/armada-385-turris-omnia.dts index 2d8d319bec83..7b755bb4e4e7 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -435,12 +435,10 @@ phy1: ethernet-phy@1 { }; =20 /* Switch MV88E6176 at address 0x10 */ - switch@10 { + ethernet-switch@10 { pinctrl-names =3D "default"; pinctrl-0 =3D <&swint_pins>; compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; =20 dsa,member =3D <0 0>; reg =3D <0x10>; @@ -448,36 +446,36 @@ switch@10 { interrupt-parent =3D <&gpio1>; interrupts =3D <13 IRQ_TYPE_LEVEL_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - ports@0 { + ethernet-port@0 { reg =3D <0>; label =3D "lan0"; }; =20 - ports@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan1"; }; =20 - ports@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan2"; }; =20 - ports@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan3"; }; =20 - ports@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan4"; }; =20 - ports@5 { + ethernet-port@5 { reg =3D <5>; ethernet =3D <ð1>; phy-mode =3D "rgmii-id"; @@ -488,7 +486,7 @@ fixed-link { }; }; =20 - ports@6 { + ethernet-port@6 { reg =3D <6>; ethernet =3D <ð0>; phy-mode =3D "rgmii-id"; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/b= oot/dts/marvell/armada-388-clearfog.dts index 32c569df142f..3290ccad2374 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -92,44 +92,42 @@ pcie2-0-w-disable-hog { &mdio { status =3D "okay"; =20 - switch@4 { + ethernet-switch@4 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <4>; pinctrl-0 =3D <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; pinctrl-names =3D "default"; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "lan5"; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan4"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan3"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan2"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan1"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; ethernet =3D <ð1>; phy-mode =3D "1000base-x"; @@ -140,7 +138,7 @@ fixed-link { }; }; =20 - port@6 { + ethernet-port@6 { /* 88E1512 external phy */ reg =3D <6>; label =3D "lan6"; diff --git a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts b/arch/a= rm/boot/dts/marvell/armada-xp-linksys-mamba.dts index 7a0614fd0c93..ea859f7ea042 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts @@ -265,42 +265,40 @@ flash@0 { &mdio { status =3D "okay"; =20 - switch@0 { + ethernet-switch@0 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "lan4"; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan3"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan1"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "internet"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; phy-mode =3D "rgmii-id"; ethernet =3D <ð0>; --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB05AC00A8F for ; Tue, 24 Oct 2023 13:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234494AbjJXNU4 (ORCPT ); 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Tue, 24 Oct 2023 06:20:34 -0700 (PDT) From: Linus Walleij Date: Tue, 24 Oct 2023 15:20:30 +0200 Subject: [PATCH net-next v7 4/7] ARM: dts: nxp: Fix some common switch mistakes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-4-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix some errors in the Marvell MV88E6xxx switch descriptions: - switch0@0 is not OK, should be ethernet-switch@0 - ports should be ethernet-ports - port should be ethernet-port - phy should be ethernet-phy Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts | 14 ++--- arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts | 70 ++++++++++++--------= ---- arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts | 18 +++--- arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts | 20 +++---- arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts | 18 +++--- 5 files changed, 70 insertions(+), 70 deletions(-) diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts b/arch/arm/boot/dt= s/nxp/vf/vf610-zii-cfu1.dts index 1a19aec8957b..7e72f860c3c5 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts @@ -162,7 +162,7 @@ mdio1: mdio { suppress-preamble; status =3D "okay"; =20 - switch0: switch0@0 { + switch0: ethernet-switch@0 { compatible =3D "marvell,mv88e6085"; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_switch>; @@ -173,26 +173,26 @@ switch0: switch0@0 { interrupt-controller; #interrupt-cells =3D <2>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "eth_cu_1000_1"; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "eth_cu_1000_2"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_cu_1000_3"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_fc_1000_1"; phy-mode =3D "1000base-x"; @@ -200,7 +200,7 @@ port@5 { sfp =3D <&sff>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; phy-mode =3D "rmii"; ethernet =3D <&fec1>; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts b/arch/arm/boo= t/dts/nxp/vf/vf610-zii-scu4-aib.dts index df1335492a19..77492eeea450 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts @@ -47,17 +47,17 @@ mdio_mux_1: mdio@1 { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0: switch0@0 { + switch0: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; reg =3D <0>; dsa,member =3D <0 0>; eeprom-length =3D <65536>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; phy-mode =3D "rmii"; ethernet =3D <&fec1>; @@ -68,37 +68,37 @@ fixed-link { }; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "aib2main_1"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "aib2main_2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_cu_1000_5"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "eth_cu_1000_6"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_cu_1000_4"; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "eth_cu_1000_7"; }; =20 - port@7 { + ethernet-port@7 { reg =3D <7>; label =3D "modem_pic"; =20 @@ -108,7 +108,7 @@ fixed-link { }; }; =20 - switch0port10: port@10 { + switch0port10: ethernet-port@10 { reg =3D <10>; label =3D "dsa"; phy-mode =3D "xgmii"; @@ -130,32 +130,32 @@ mdio_mux_2: mdio@2 { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch1: switch1@0 { + switch1: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; reg =3D <0>; dsa,member =3D <0 1>; eeprom-length =3D <65536>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "eth_cu_1000_3"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_cu_100_2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_cu_100_3"; }; =20 - switch1port9: port@9 { + switch1port9: ethernet-port@9 { reg =3D <9>; label =3D "dsa"; phy-mode =3D "xgmii"; @@ -168,7 +168,7 @@ fixed-link { }; }; =20 - switch1port10: port@10 { + switch1port10: ethernet-port@10 { reg =3D <10>; label =3D "dsa"; phy-mode =3D "xgmii"; @@ -188,17 +188,17 @@ mdio_mux_4: mdio@4 { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch2: switch2@0 { + switch2: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; reg =3D <0>; dsa,member =3D <0 2>; eeprom-length =3D <65536>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_fc_1000_2"; phy-mode =3D "1000base-x"; @@ -206,7 +206,7 @@ port@2 { sfp =3D <&sff1>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_fc_1000_3"; phy-mode =3D "1000base-x"; @@ -214,7 +214,7 @@ port@3 { sfp =3D <&sff2>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "eth_fc_1000_4"; phy-mode =3D "1000base-x"; @@ -222,7 +222,7 @@ port@4 { sfp =3D <&sff3>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_fc_1000_5"; phy-mode =3D "1000base-x"; @@ -230,7 +230,7 @@ port@5 { sfp =3D <&sff4>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "eth_fc_1000_6"; phy-mode =3D "1000base-x"; @@ -238,7 +238,7 @@ port@6 { sfp =3D <&sff5>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <7>; label =3D "eth_fc_1000_7"; phy-mode =3D "1000base-x"; @@ -246,7 +246,7 @@ port@7 { sfp =3D <&sff6>; }; =20 - port@9 { + ethernet-port@9 { reg =3D <9>; label =3D "eth_fc_1000_1"; phy-mode =3D "1000base-x"; @@ -254,7 +254,7 @@ port@9 { sfp =3D <&sff0>; }; =20 - switch2port10: port@10 { + switch2port10: ethernet-port@10 { reg =3D <10>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -276,17 +276,17 @@ mdio_mux_8: mdio@8 { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch3: switch3@0 { + switch3: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; reg =3D <0>; dsa,member =3D <0 3>; eeprom-length =3D <65536>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_fc_1000_8"; phy-mode =3D "1000base-x"; @@ -294,7 +294,7 @@ port@2 { sfp =3D <&sff7>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_fc_1000_9"; phy-mode =3D "1000base-x"; @@ -302,7 +302,7 @@ port@3 { sfp =3D <&sff8>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "eth_fc_1000_10"; phy-mode =3D "1000base-x"; @@ -310,7 +310,7 @@ port@4 { sfp =3D <&sff9>; }; =20 - switch3port9: port@9 { + switch3port9: ethernet-port@9 { reg =3D <9>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -322,7 +322,7 @@ fixed-link { }; }; =20 - switch3port10: port@10 { + switch3port10: ethernet-port@10 { reg =3D <10>; label =3D "dsa"; phy-mode =3D "xgmii"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts b/arch/arm/boot/dt= s/nxp/vf/vf610-zii-spb4.dts index 1461804ecaea..2a490464660c 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts @@ -123,7 +123,7 @@ mdio1: mdio { suppress-preamble; status =3D "okay"; =20 - switch0: switch0@0 { + switch0: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; pinctrl-0 =3D <&pinctrl_gpio_switch0>; pinctrl-names =3D "default"; @@ -134,11 +134,11 @@ switch0: switch0@0 { interrupt-controller; #interrupt-cells =3D <2>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; phy-mode =3D "rmii"; ethernet =3D <&fec1>; @@ -149,32 +149,32 @@ fixed-link { }; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "eth_cu_1000_1"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_cu_1000_2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_cu_1000_3"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "eth_cu_1000_4"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_cu_1000_5"; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "eth_cu_1000_6"; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts b/arch/arm/boo= t/dts/nxp/vf/vf610-zii-ssmb-dtu.dts index 463c2452b9b7..078d8699e16d 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts @@ -112,7 +112,7 @@ mdio1: mdio { suppress-preamble; status =3D "okay"; =20 - switch0: switch0@0 { + switch0: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; pinctrl-0 =3D <&pinctrl_gpio_switch0>; pinctrl-names =3D "default"; @@ -123,11 +123,11 @@ switch0: switch0@0 { interrupt-controller; #interrupt-cells =3D <2>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; phy-mode =3D "rmii"; ethernet =3D <&fec1>; @@ -138,27 +138,27 @@ fixed-link { }; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "eth_cu_100_3"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_cu_1000_4"; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "eth_cu_1000_5"; }; =20 - port@8 { + ethernet-port@8 { reg =3D <8>; label =3D "eth_cu_1000_1"; }; =20 - port@9 { + ethernet-port@9 { reg =3D <9>; label =3D "eth_cu_1000_2"; phy-handle =3D <&phy9>; @@ -167,12 +167,12 @@ port@9 { }; }; =20 - mdio1 { + mdio-external { compatible =3D "marvell,mv88e6xxx-mdio-external"; #address-cells =3D <1>; #size-cells =3D <0>; =20 - phy9: phy9@0 { + phy9: ethernet-phy@0 { compatible =3D "ethernet-phy-ieee802.3-c45"; pinctrl-0 =3D <&pinctrl_gpio_phy9>; pinctrl-names =3D "default"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts b/arch/arm/bo= ot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts index f5ae0d5de315..22c8f44390a9 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts @@ -137,7 +137,7 @@ mdio1: mdio { suppress-preamble; status =3D "okay"; =20 - switch0: switch0@0 { + switch0: ethernet-switch@0 { compatible =3D "marvell,mv88e6190"; pinctrl-0 =3D <&pinctrl_gpio_switch0>; pinctrl-names =3D "default"; @@ -148,11 +148,11 @@ switch0: switch0@0 { interrupt-controller; #interrupt-cells =3D <2>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; phy-mode =3D "rmii"; ethernet =3D <&fec1>; @@ -163,32 +163,32 @@ fixed-link { }; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "eth_cu_1000_1"; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "eth_cu_1000_2"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "eth_cu_1000_3"; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "eth_cu_1000_4"; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "eth_cu_1000_5"; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "eth_cu_1000_6"; }; --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C93EC00A8F for ; Tue, 24 Oct 2023 13:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343491AbjJXNVH (ORCPT ); Tue, 24 Oct 2023 09:21:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234461AbjJXNUp (ORCPT ); Tue, 24 Oct 2023 09:20:45 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56D7B110 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-5-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix some errors in the Marvell MV88E6xxx switch descriptions: - The top node had no address size or cells. - switch0@0 is not OK, should be ethernet-switch@0. - ports should be ethernet-ports - port@0 should be ethernet-port@0 - PHYs should be named ethernet-phy@ Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- .../dts/marvell/armada-3720-espressobin-ultra.dts | 14 +- .../boot/dts/marvell/armada-3720-espressobin.dtsi | 20 +-- .../boot/dts/marvell/armada-3720-gl-mv1000.dts | 20 +-- .../boot/dts/marvell/armada-3720-turris-mox.dts | 189 +++++++++++------= ---- .../boot/dts/marvell/armada-7040-mochabin.dts | 24 ++- .../dts/marvell/armada-8040-clearfog-gt-8k.dts | 22 +-- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 42 +++-- 7 files changed, 164 insertions(+), 167 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts = b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index f9abef8dcc94..870bb380a40a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -126,32 +126,32 @@ &switch0 { =20 reset-gpios =3D <&gpiosb 23 GPIO_ACTIVE_LOW>; =20 - ports { - switch0port1: port@1 { + ethernet-ports { + switch0port1: ethernet-port@1 { reg =3D <1>; label =3D "lan0"; phy-handle =3D <&switch0phy0>; }; =20 - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg =3D <3>; label =3D "lan2"; phy-handle =3D <&switch0phy2>; }; =20 - switch0port4: port@4 { + switch0port4: ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - switch0port5: port@5 { + switch0port5: ethernet-port@5 { reg =3D <5>; label =3D "wan"; phy-handle =3D <&extphy>; @@ -160,7 +160,7 @@ switch0port5: port@5 { }; =20 mdio { - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arc= h/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 5fc613d24151..86ec0df1c676 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -145,19 +145,17 @@ &usb2 { }; =20 &mdio { - switch0: switch0@1 { + switch0: ethernet-switch@1 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <1>; =20 dsa,member =3D <0 0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0port0: port@0 { + switch0port0: ethernet-port@0 { reg =3D <0>; label =3D "cpu"; ethernet =3D <ð0>; @@ -168,19 +166,19 @@ fixed-link { }; }; =20 - switch0port1: port@1 { + switch0port1: ethernet-port@1 { reg =3D <1>; label =3D "wan"; phy-handle =3D <&switch0phy0>; }; =20 - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg =3D <2>; label =3D "lan0"; phy-handle =3D <&switch0phy1>; }; =20 - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg =3D <3>; label =3D "lan1"; phy-handle =3D <&switch0phy2>; @@ -192,13 +190,13 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/a= rm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index b1b45b4fa9d4..63fbc8352161 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -152,31 +152,29 @@ &uart0 { }; =20 &mdio { - switch0: switch0@1 { + switch0: ethernet-switch@1 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <1>; =20 dsa,member =3D <0 0>; =20 - ports: ports { + ports: ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "cpu"; ethernet =3D <ð0>; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "wan"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan0"; phy-handle =3D <&switch0phy1>; @@ -185,7 +183,7 @@ port@2 { nvmem-cell-names =3D "mac-address"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan1"; phy-handle =3D <&switch0phy2>; @@ -199,13 +197,13 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/= arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 9eab2bb22134..cdf1b8bdb230 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -304,7 +304,12 @@ phy1: ethernet-phy@1 { reg =3D <1>; }; =20 - /* switch nodes are enabled by U-Boot if modules are present */ + /* + * NOTE: switch nodes are enabled by U-Boot if modules are present + * DO NOT change this node name (switch0@10) even if it is not following + * conventions! Deployed U-Boot binaries are explicitly looking for + * this node in order to augment the device tree! + */ switch0@10 { compatible =3D "marvell,mv88e6190"; reg =3D <0x10>; @@ -317,92 +322,92 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan2"; phy-handle =3D <&switch0phy2>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan4"; phy-handle =3D <&switch0phy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "lan5"; phy-handle =3D <&switch0phy5>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <0x6>; label =3D "lan6"; phy-handle =3D <&switch0phy6>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <0x7>; label =3D "lan7"; phy-handle =3D <&switch0phy7>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <0x8>; label =3D "lan8"; phy-handle =3D <&switch0phy8>; }; =20 - port@9 { + ethernet-port@9 { reg =3D <0x9>; label =3D "cpu"; ethernet =3D <ð1>; @@ -410,7 +415,7 @@ port@9 { managed =3D "in-band-status"; }; =20 - switch0port10: port@a { + switch0port10: ethernet-port@a { reg =3D <0xa>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -430,7 +435,7 @@ port-sfp@a { }; }; =20 - switch0@2 { + ethernet-switch@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; dsa,member =3D <0 0>; @@ -442,52 +447,52 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1_topaz: switch0phy1@11 { + switch0phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch0phy2_topaz: switch0phy2@12 { + switch0phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch0phy3_topaz: switch0phy3@13 { + switch0phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch0phy4_topaz: switch0phy4@14 { + switch0phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan1"; phy-handle =3D <&switch0phy1_topaz>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan2"; phy-handle =3D <&switch0phy2_topaz>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan3"; phy-handle =3D <&switch0phy3_topaz>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan4"; phy-handle =3D <&switch0phy4_topaz>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "cpu"; phy-mode =3D "2500base-x"; @@ -497,7 +502,7 @@ port@5 { }; }; =20 - switch1@11 { + ethernet-switch@11 { compatible =3D "marvell,mv88e6190"; reg =3D <0x11>; dsa,member =3D <0 1>; @@ -509,92 +514,92 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch1phy1: switch1phy1@1 { + switch1phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch1phy2: switch1phy2@2 { + switch1phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch1phy3: switch1phy3@3 { + switch1phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch1phy4: switch1phy4@4 { + switch1phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch1phy5: switch1phy5@5 { + switch1phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch1phy6: switch1phy6@6 { + switch1phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch1phy7: switch1phy7@7 { + switch1phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch1phy8: switch1phy8@8 { + switch1phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan9"; phy-handle =3D <&switch1phy1>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan10"; phy-handle =3D <&switch1phy2>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan11"; phy-handle =3D <&switch1phy3>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan12"; phy-handle =3D <&switch1phy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "lan13"; phy-handle =3D <&switch1phy5>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <0x6>; label =3D "lan14"; phy-handle =3D <&switch1phy6>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <0x7>; label =3D "lan15"; phy-handle =3D <&switch1phy7>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <0x8>; label =3D "lan16"; phy-handle =3D <&switch1phy8>; }; =20 - switch1port9: port@9 { + switch1port9: ethernet-port@9 { reg =3D <0x9>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -602,7 +607,7 @@ switch1port9: port@9 { link =3D <&switch0port10>; }; =20 - switch1port10: port@a { + switch1port10: ethernet-port@a { reg =3D <0xa>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -622,7 +627,7 @@ port-sfp@a { }; }; =20 - switch1@2 { + ethernet-switch@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; dsa,member =3D <0 1>; @@ -634,52 +639,52 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch1phy1_topaz: switch1phy1@11 { + switch1phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch1phy2_topaz: switch1phy2@12 { + switch1phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch1phy3_topaz: switch1phy3@13 { + switch1phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch1phy4_topaz: switch1phy4@14 { + switch1phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan9"; phy-handle =3D <&switch1phy1_topaz>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan10"; phy-handle =3D <&switch1phy2_topaz>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan11"; phy-handle =3D <&switch1phy3_topaz>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan12"; phy-handle =3D <&switch1phy4_topaz>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -689,7 +694,7 @@ port@5 { }; }; =20 - switch2@12 { + ethernet-switch@12 { compatible =3D "marvell,mv88e6190"; reg =3D <0x12>; dsa,member =3D <0 2>; @@ -701,92 +706,92 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch2phy1: switch2phy1@1 { + switch2phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch2phy2: switch2phy2@2 { + switch2phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch2phy3: switch2phy3@3 { + switch2phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch2phy4: switch2phy4@4 { + switch2phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch2phy5: switch2phy5@5 { + switch2phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch2phy6: switch2phy6@6 { + switch2phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch2phy7: switch2phy7@7 { + switch2phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch2phy8: switch2phy8@8 { + switch2phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan17"; phy-handle =3D <&switch2phy1>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan18"; phy-handle =3D <&switch2phy2>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan19"; phy-handle =3D <&switch2phy3>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan20"; phy-handle =3D <&switch2phy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "lan21"; phy-handle =3D <&switch2phy5>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <0x6>; label =3D "lan22"; phy-handle =3D <&switch2phy6>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <0x7>; label =3D "lan23"; phy-handle =3D <&switch2phy7>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <0x8>; label =3D "lan24"; phy-handle =3D <&switch2phy8>; }; =20 - switch2port9: port@9 { + switch2port9: ethernet-port@9 { reg =3D <0x9>; label =3D "dsa"; phy-mode =3D "2500base-x"; @@ -805,7 +810,7 @@ port-sfp@a { }; }; =20 - switch2@2 { + ethernet-switch@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; dsa,member =3D <0 2>; @@ -817,52 +822,52 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch2phy1_topaz: switch2phy1@11 { + switch2phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch2phy2_topaz: switch2phy2@12 { + switch2phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch2phy3_topaz: switch2phy3@13 { + switch2phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch2phy4_topaz: switch2phy4@14 { + switch2phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <0x1>; label =3D "lan17"; phy-handle =3D <&switch2phy1_topaz>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <0x2>; label =3D "lan18"; phy-handle =3D <&switch2phy2_topaz>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <0x3>; label =3D "lan19"; phy-handle =3D <&switch2phy3_topaz>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <0x4>; label =3D "lan20"; phy-handle =3D <&switch2phy4_topaz>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <0x5>; label =3D "dsa"; phy-mode =3D "2500base-x"; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/ar= m64/boot/dts/marvell/armada-7040-mochabin.dts index 48202810bf78..40b7ee7ead72 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -301,10 +301,8 @@ eth2phy: ethernet-phy@1 { }; =20 /* 88E6141 Topaz switch */ - switch: switch@3 { + switch: ethernet-switch@3 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <3>; =20 pinctrl-names =3D "default"; @@ -314,35 +312,35 @@ switch: switch@3 { interrupt-parent =3D <&cp0_gpio1>; interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - swport1: port@1 { + swport1: ethernet-port@1 { reg =3D <1>; label =3D "lan0"; phy-handle =3D <&swphy1>; }; =20 - swport2: port@2 { + swport2: ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&swphy2>; }; =20 - swport3: port@3 { + swport3: ethernet-port@3 { reg =3D <3>; label =3D "lan2"; phy-handle =3D <&swphy3>; }; =20 - swport4: port@4 { + swport4: ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&swphy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "cpu"; ethernet =3D <&cp0_eth1>; @@ -355,19 +353,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - swphy1: swphy1@17 { + swphy1: ethernet-phy@17 { reg =3D <17>; }; =20 - swphy2: swphy2@18 { + swphy2: ethernet-phy@18 { reg =3D <18>; }; =20 - swphy3: swphy3@19 { + swphy3: ethernet-phy@19 { reg =3D <19>; }; =20 - swphy4: swphy4@20 { + swphy4: ethernet-phy@20 { reg =3D <20>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/a= rch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 4125202028c8..67892f0d2863 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -497,42 +497,42 @@ ge_phy: ethernet-phy@0 { reset-deassert-us =3D <10000>; }; =20 - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible =3D "marvell,mv88e6085"; reg =3D <4>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_switch_reset_pins>; reset-gpios =3D <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan2"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan4"; phy-handle =3D <&switch0phy2>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "cpu"; ethernet =3D <&cp1_eth2>; @@ -545,19 +545,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/= dts/marvell/cn9130-crb.dtsi index 32cfb3e2efc3..7538ed56053b 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -207,11 +207,9 @@ phy0: ethernet-phy@0 { reg =3D <0>; }; =20 - switch6: switch0@6 { + switch6: ethernet-switch@6 { /* Actual device is MV88E6393X */ compatible =3D "marvell,mv88e6190"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <6>; interrupt-parent =3D <&cp0_gpio1>; interrupts =3D <28 IRQ_TYPE_LEVEL_LOW>; @@ -220,59 +218,59 @@ switch6: switch0@6 { =20 dsa,member =3D <0 0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "p1"; phy-handle =3D <&switch0phy1>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "p2"; phy-handle =3D <&switch0phy2>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "p3"; phy-handle =3D <&switch0phy3>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "p4"; phy-handle =3D <&switch0phy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "p5"; phy-handle =3D <&switch0phy5>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "p6"; phy-handle =3D <&switch0phy6>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <7>; label =3D "p7"; phy-handle =3D <&switch0phy7>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <8>; label =3D "p8"; phy-handle =3D <&switch0phy8>; }; =20 - port@9 { + ethernet-port@9 { reg =3D <9>; label =3D "p9"; phy-mode =3D "10gbase-r"; @@ -280,7 +278,7 @@ port@9 { managed =3D "in-band-status"; }; =20 - port@a { + ethernet-port@a { reg =3D <10>; ethernet =3D <&cp0_eth0>; phy-mode =3D "10gbase-r"; @@ -293,35 +291,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 540A3C00A8F for ; Tue, 24 Oct 2023 13:21:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234470AbjJXNVA (ORCPT ); Tue, 24 Oct 2023 09:21:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234415AbjJXNUm (ORCPT ); Tue, 24 Oct 2023 09:20:42 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8930510C2 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-6-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij , Rob Herring X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an attempt to rewrite the Marvell MV88E6xxx switch bindings in YAML schema. The current text binding says: WARNING: This binding is currently unstable. Do not program it into a FLASH never to be changed again. Once this binding is stable, this warning will be removed. Well that never happened before we switched to YAML markup, we can't have it like this, what about fixing the mess? Reviewed-by: Andrew Lunn Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- .../bindings/net/dsa/marvell,mv88e6xxx.yaml | 330 +++++++++++++++++= ++++ .../devicetree/bindings/net/dsa/marvell.txt | 109 ------- MAINTAINERS | 2 +- 3 files changed, 331 insertions(+), 110 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.ya= ml b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml new file mode 100644 index 000000000000..34d8561a2187 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml @@ -0,0 +1,330 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MV88E6xxx DSA switch family + +maintainers: + - Andrew Lunn + +description: + The Marvell MV88E6xxx switch series has been produced and sold + by Marvell since at least 2008. The switch has a few compatibles which + just indicate the base address of the switch, then operating systems + can investigate switch ID registers to find out which actual version + of the switch it is dealing with. + +properties: + compatible: + enum: + - marvell,mv88e6085 + - marvell,mv88e6190 + - marvell,mv88e6250 + description: | + marvell,mv88e6085: This switch uses base address 0x10. + This switch and its siblings will be autodetected from + ID registers found in the switch, so only "marvell,mv88e6085" shou= ld be + specified. This includes the following list of MV88Exxxx switches: + 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, = 6176, + 6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352 + marvell,mv88e6190: This switch uses base address 0x00. + This switch and its siblings will be autodetected from + ID registers found in the switch, so only "marvell,mv88e6190" shou= ld be + specified. This includes the following list of MV88Exxxx switches: + 6190, 6190X, 6191, 6290, 6361, 6390, 6390X + marvell,mv88e6250: This switch uses base address 0x08 or 0x18. + This switch and its siblings will be autodetected from + ID registers found in the switch, so only "marvell,mv88e6250" shou= ld be + specified. This includes the following list of MV88Exxxx switches: + 6220, 6250 + + reg: + maxItems: 1 + + eeprom-length: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set to the length of an EEPROM connected to the switch. M= ust be + set if the switch can not detect the presence and/or size of a conne= cted + EEPROM, otherwise optional. + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + interrupts: + description: The switch provides an external interrupt line, but it is + not always used by target systems. + maxItems: 1 + + interrupt-controller: + description: The switch has an internal interrupt controller used by + the different sub-blocks. + + '#interrupt-cells': + description: The internal interrupt controller only supports triggering + on active high level interrupts so the second cell must alway be set= to + IRQ_TYPE_LEVEL_HIGH. + const: 2 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: Marvell MV88E6xxx switches have an varying combination of + internal and external MDIO buses, in some cases a combined bus that + can be used both internally and externally. This node is for the + primary bus, used internally and sometimes also externally. + + mdio-external: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: Marvell MV88E6xxx switches that have a separate external + MDIO bus use this port to access external components on the MDIO bus. + + properties: + compatible: + const: marvell,mv88e6xxx-mdio-external + + required: + - compatible + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-switch@0 { + compatible =3D "marvell,mv88e6085"; + reg =3D <0>; + reset-gpios =3D <&gpio5 1 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sw_phy0: ethernet-phy@0 { + reg =3D <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg =3D <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg =3D <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg =3D <0x3>; + }; + }; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-port@0 { + reg =3D <0>; + label =3D "lan4"; + phy-handle =3D <&sw_phy0>; + phy-mode =3D "internal"; + }; + + ethernet-port@1 { + reg =3D <1>; + label =3D "lan3"; + phy-handle =3D <&sw_phy1>; + phy-mode =3D "internal"; + }; + + ethernet-port@2 { + reg =3D <2>; + label =3D "lan2"; + phy-handle =3D <&sw_phy2>; + phy-mode =3D "internal"; + }; + + ethernet-port@3 { + reg =3D <3>; + label =3D "lan1"; + phy-handle =3D <&sw_phy3>; + phy-mode =3D "internal"; + }; + + ethernet-port@5 { + reg =3D <5>; + ethernet =3D <&fec>; + phy-mode =3D "rgmii-id"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + }; + }; + }; + - | + #include + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-switch@0 { + compatible =3D "marvell,mv88e6190"; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&gpio1>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&switch_interrupt_pins>; + pinctrl-names =3D "default"; + reg =3D <0>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch0phy1: ethernet-phy@1 { + reg =3D <0x1>; + }; + + switch0phy2: ethernet-phy@2 { + reg =3D <0x2>; + }; + + switch0phy3: ethernet-phy@3 { + reg =3D <0x3>; + }; + + switch0phy4: ethernet-phy@4 { + reg =3D <0x4>; + }; + + switch0phy5: ethernet-phy@5 { + reg =3D <0x5>; + }; + + switch0phy6: ethernet-phy@6 { + reg =3D <0x6>; + }; + + switch0phy7: ethernet-phy@7 { + reg =3D <0x7>; + }; + + switch0phy8: ethernet-phy@8 { + reg =3D <0x8>; + }; + }; + + mdio-external { + compatible =3D "marvell,mv88e6xxx-mdio-external"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy1: ethernet-phy@b { + reg =3D <0xb>; + compatible =3D "ethernet-phy-ieee802.3-c45"; + }; + + phy2: ethernet-phy@c { + reg =3D <0xc>; + compatible =3D "ethernet-phy-ieee802.3-c45"; + }; + }; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-port@0 { + ethernet =3D <ð0>; + phy-mode =3D "rgmii"; + reg =3D <0>; + + fixed-link { + full-duplex; + pause; + speed =3D <1000>; + }; + }; + + ethernet-port@1 { + label =3D "lan1"; + phy-handle =3D <&switch0phy1>; + reg =3D <1>; + }; + + ethernet-port@2 { + label =3D "lan2"; + phy-handle =3D <&switch0phy2>; + reg =3D <2>; + }; + + ethernet-port@3 { + label =3D "lan3"; + phy-handle =3D <&switch0phy3>; + reg =3D <3>; + }; + + ethernet-port@4 { + label =3D "lan4"; + phy-handle =3D <&switch0phy4>; + reg =3D <4>; + }; + + ethernet-port@5 { + label =3D "lan5"; + phy-handle =3D <&switch0phy5>; + reg =3D <5>; + }; + + ethernet-port@6 { + label =3D "lan6"; + phy-handle =3D <&switch0phy6>; + reg =3D <6>; + }; + + ethernet-port@7 { + label =3D "lan7"; + phy-handle =3D <&switch0phy7>; + reg =3D <7>; + }; + + ethernet-port@8 { + label =3D "lan8"; + phy-handle =3D <&switch0phy8>; + reg =3D <8>; + }; + + ethernet-port@9 { + /* 88X3310P external phy */ + label =3D "lan9"; + phy-handle =3D <&phy1>; + phy-mode =3D "xaui"; + reg =3D <9>; + }; + + ethernet-port@a { + /* 88X3310P external phy */ + label =3D "lan10"; + phy-handle =3D <&phy2>; + phy-mode =3D "xaui"; + reg =3D <0xa>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Docume= ntation/devicetree/bindings/net/dsa/marvell.txt deleted file mode 100644 index 6ec0c181b6db..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ /dev/null @@ -1,109 +0,0 @@ -Marvell DSA Switch Device Tree Bindings ---------------------------------------- - -WARNING: This binding is currently unstable. Do not program it into a -FLASH never to be changed again. Once this binding is stable, this -warning will be removed. - -If you need a stable binding, use the old dsa.txt binding. - -Marvell Switches are MDIO devices. The following properties should be -placed as a child node of an mdio device. - -The properties described here are those specific to Marvell devices. -Additional required and optional properties can be found in dsa.txt. - -The compatibility string is used only to find an identification register, -which is at a different MDIO base address in different switch families. -- "marvell,mv88e6085" : Switch has base address 0x10. Use with models: - 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, - 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321, - 6341, 6350, 6351, 6352 -- "marvell,mv88e6190" : Switch has base address 0x00. Use with models: - 6190, 6190X, 6191, 6290, 6361, 6390, 6390X -- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with mod= el: - 6220, 6250 - -Required properties: -- compatible : Should be one of "marvell,mv88e6085", - "marvell,mv88e6190" or "marvell,mv88e6250" as - indicated above -- reg : Address on the MII bus for the switch. - -Optional properties: - -- reset-gpios : Should be a gpio specifier for a reset line -- interrupts : Interrupt from the switch -- interrupt-controller : Indicates the switch is itself an interrupt - controller. This is used for the PHY interrupts. -#interrupt-cells =3D <2> : Controller uses two cells, number and flag -- eeprom-length : Set to the length of an EEPROM connected to the - switch. Must be set if the switch can not detect - the presence and/or size of a connected EEPROM, - otherwise optional. -- mdio : Container of PHY and devices on the switches MDIO - bus. -- mdio? : Container of PHYs and devices on the external MDIO - bus. The node must contains a compatible string of - "marvell,mv88e6xxx-mdio-external" - -Example: - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupt-parent =3D <&gpio0>; - interrupts =3D <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells =3D <2>; - - switch0: switch@0 { - compatible =3D "marvell,mv88e6085"; - reg =3D <0>; - reset-gpios =3D <&gpio5 1 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - switch1phy0: switch1phy0@0 { - reg =3D <0>; - interrupt-parent =3D <&switch0>; - interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupt-parent =3D <&gpio0>; - interrupts =3D <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells =3D <2>; - - switch0: switch@0 { - compatible =3D "marvell,mv88e6190"; - reg =3D <0>; - reset-gpios =3D <&gpio5 1 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - switch1phy0: switch1phy0@0 { - reg =3D <0>; - interrupt-parent =3D <&switch0>; - interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - mdio1 { - compatible =3D "marvell,mv88e6xxx-mdio-external"; - #address-cells =3D <1>; - #size-cells =3D <0>; - switch1phy9: switch1phy0@9 { - reg =3D <9>; - }; - }; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..1b4475254d27 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12625,7 +12625,7 @@ MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER M: Andrew Lunn L: netdev@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/net/dsa/marvell.txt +F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml F: Documentation/networking/devlink/mv88e6xxx.rst F: drivers/net/dsa/mv88e6xxx/ F: include/linux/dsa/mv88e6xxx.h --=20 2.34.1 From nobody Thu Jan 1 09:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C328C07545 for ; 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Tue, 24 Oct 2023 06:20:38 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id d5-20020a193845000000b00507ab956ab9sm2147365lfj.147.2023.10.24.06.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 06:20:38 -0700 (PDT) From: Linus Walleij Date: Tue, 24 Oct 2023 15:20:33 +0200 Subject: [PATCH net-next v7 7/7] dt-bindings: marvell: Add Marvell MV88E6060 DSA schema MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231024-marvell-88e6152-wan-led-v7-7-2869347697d1@linaro.org> References: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> In-Reply-To: <20231024-marvell-88e6152-wan-led-v7-0-2869347697d1@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= Cc: Christian Marangi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Linus Walleij , Vladimir Oltean , Rob Herring X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Marvell MV88E6060 is one of the oldest DSA switches from Marvell, and it has DT bindings used in the wild. Let's define them properly. It is different enough from the rest of the MV88E6xxx switches that it deserves its own binding. Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean Reviewed-by: Rob Herring Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- .../bindings/net/dsa/marvell,mv88e6060.yaml | 88 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 89 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.ya= ml b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml new file mode 100644 index 000000000000..4f1adf00431a --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6060.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MV88E6060 DSA switch + +maintainers: + - Andrew Lunn + +description: + The Marvell MV88E6060 switch has been produced and sold by Marvell + since at least 2008. The switch has one pin ADDR4 that controls the + MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus + connected to the switch, the PHYs inside the switch appear as + independent devices on address 0x00-0x04 or 0x10-0x14, so in difference + from many other DSA switches this switch does not have an internal + MDIO bus for the PHY devices. + +properties: + compatible: + const: marvell,mv88e6060 + description: + The MV88E6060 is the oldest Marvell DSA switch product, and + as such a bit limited in features compared to later hardware. + + reg: + maxItems: 1 + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-switch@16 { + compatible =3D "marvell,mv88e6060"; + reg =3D <16>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + ethernet-port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + ethernet-port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + ethernet-port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + ethernet-port@5 { + reg =3D <5>; + phy-mode =3D "rev-mii"; + ethernet =3D <ðc>; + fixed-link { + speed =3D <100>; + full-duplex; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 1b4475254d27..4c933a2a56ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12625,6 +12625,7 @@ MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER M: Andrew Lunn L: netdev@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml F: Documentation/networking/devlink/mv88e6xxx.rst F: drivers/net/dsa/mv88e6xxx/ --=20 2.34.1