From nobody Thu Jan 1 12:24:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E86FC25B47 for ; Mon, 23 Oct 2023 17:29:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbjJWR3z (ORCPT ); Mon, 23 Oct 2023 13:29:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233766AbjJWR3X (ORCPT ); Mon, 23 Oct 2023 13:29:23 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B6601703 for ; Mon, 23 Oct 2023 10:29:02 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6bd0e1b1890so2662147b3a.3 for ; Mon, 23 Oct 2023 10:29:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082141; x=1698686941; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TYQsgV6mmNiNxm7fkk00HaM0IkP9BeYIjrigTOut9Eg=; b=VZrHxlzgKisIWtxm54LawilI7DPNevOtCwZnk8x3KEXTyu3PKVL37k49iiWV2W60n/ DDT6MrHl4RLGkjnpQF9fb53ptasjtfbNDHk8hE6kmeGgd3DTT4JFxDONbRdAVBA8jO5X thbHMAWu+IErt8rxmYvF97yi+2+pNy1TDVDO4m/dWJ+UgOqrkwdJ4xlU82oZBvdnbWS0 xzw/Y9lyZ3io06vekYblOmOkCn/e5i8+1hDcqgRZYkC+B2sxlF+GE8Hm83cC+MtuUvg8 ZF0A9JmAVWyhYTcCHwCKGYxF3JfdLbJ4vKa8tAFBDA42kvyKOMowTuGOIz+4cllIQuHx 4Q+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082141; x=1698686941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TYQsgV6mmNiNxm7fkk00HaM0IkP9BeYIjrigTOut9Eg=; b=dD5sj6rbFzHaDcQsjMZRtTlMm/AHZ0I+v4xlAQ9Lw4ZzMXGM7YEQttFbDm0G4z2Eox CfSQUn40oWyi8hDVV+d+6nkwYuWdyrTHTWElP8g2LE+dNb7qtGOHmhfE1M4nwKWr64r8 P1zTy3NOxDBIUs57+Oe4uqyRy9MgTf4j00OkLtU2o1qqqw6ePtZhv/uuvk3UI4dGa39E dW86Z9F3ApyfQ1i1L9aRS4qwzamdnmT2h2ySMJMFYRmvDWKYLAd5zSDMgvw3t+tk42Jn GP9b8MI452EIY4A2g6lUqsxyyNm8QGHF3Wt/d2VQj0kqB1VagSY16vhkaqjRfmJgsaS/ 9i9A== X-Gm-Message-State: AOJu0Yw2rxI7cbiwFCqp/nXesMV+q0a/kmTKDndcHDAZim5xd/9uS8+p dGp9fZAzieSrfYS1U3Ppb9/c6w== X-Google-Smtp-Source: AGHT+IGIMMkux1pvjImjEqS+sMopDtwHWxzAnrn7oLU2p4uCjlajJOajjhDsnKb13Bpb3rj8Rhtiww== X-Received: by 2002:a05:6a20:7da0:b0:16b:7fcb:4257 with SMTP id v32-20020a056a207da000b0016b7fcb4257mr296169pzj.4.1698082141164; Mon, 23 Oct 2023 10:29:01 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:29:00 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v11 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Date: Mon, 23 Oct 2023 22:57:56 +0530 Message-Id: <20231023172800.315343-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../interrupt-controller/riscv,aplic.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml new file mode 100644 index 000000000000..190a6499c932 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root APLIC domain and a parent APLIC + domain can delegate interrupt sources to it's child APLIC domains. There + is one device tree node for each APLIC domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-i= ntc + node, which has a CPU node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incomi= ng + message signaled interrupt controller (IMSIC). If both "msi-parent" = and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, t= he + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain ch= ild + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegation: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of the parent APLIC domain (= inclusive) + - description: last interrupt number of the parent APLIC domain (i= nclusive) + description: + A interrupt delegation list where each entry is a triple consisting + of child APLIC domain phandle, first interrupt number of the parent + APLIC domain, and last interrupt number of the parent APLIC domain. + Firmware must configure interrupt delegation registers based on + interrupt delegation list. + +dependencies: + riscv,delegation: [ "riscv,children" ] + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +anyOf: + - required: + - interrupts-extended + - required: + - msi-parent + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic1>, <&aplic2>; + riscv,delegation =3D <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg =3D <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_mlevel>; + reg =3D <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic3>; + riscv,delegation =3D <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_slevel>; + reg =3D <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; +... --=20 2.34.1