From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3296FC25B46 for ; Mon, 23 Oct 2023 17:28:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232964AbjJWR2Z (ORCPT ); Mon, 23 Oct 2023 13:28:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233024AbjJWR2V (ORCPT ); Mon, 23 Oct 2023 13:28:21 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF68A10A for ; Mon, 23 Oct 2023 10:28:15 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6ba172c5f3dso2876097b3a.0 for ; Mon, 23 Oct 2023 10:28:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082095; x=1698686895; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SYhetJOGeGWONv0pBZCT4Mywf3EBvVtv+lOqGOUogJM=; b=Y3P9zZQge6Shvk4IfBExdqFHq3Zv9iYUhBdmxzNAc3jURzuxoD30dw/JXK8uywOYjq 8gmO4fUXPcDONlMvUj55EGYpAgR6q0vFP9YKQzxmam6ULYMuygYyqUp60CsSNqENYsKl 765MU/TZHgRHQRxIofTpr8vcPuRAvPQq20l6iDOPlKrkftrk/mxsgB3iMoVVFCsKmgku G2aJMZRSMBlVZghMdch1UKnE9syiwn5AKt44Nh/sYqqgIYk05PsTHX+/JoJUM3pEDQCw EJeHtvL3FrBK3nGHQ03JBqEBcLOxAXsuXfCZQpm0S3htF9yFCRjejtuQcWjCCVboR5C4 va0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082095; x=1698686895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SYhetJOGeGWONv0pBZCT4Mywf3EBvVtv+lOqGOUogJM=; b=FdsZrvaupwfvgqk0eyFne1QWbDeKTW2IX023E0KO3cA3bqTPlCbrDPe6V1ANBQqgeA mfg0tN5caZmKRxKB8tWgzik6z6FufxYGs4KXtfj0Wkz5YMs4nuDtGSZLKZ04u4LV2m99 4wND7FMqhpGWP+3Wr8hBe8K5fqPy+qLWFSKUt5R/KFsqQ5mPhnIYRcMzsvflDNsRFWln dYMcaFk8SAw+Mu7dSQg7Tz/nsZ+TiAdlCs1h5ySC8CfapixagzBEZbmNZl9pnFeUcNl+ gmLzIA6So+bWQEonrw4LBPPAUOwXwta8CbUx2lXNtvFoiNPTCczG/DckdmU5G1DUn7ot pBlw== X-Gm-Message-State: AOJu0YwliqUMq51RpngrZJfaExVQpz0MRDHWhMdoPdwrLwqdWo38e0Wa 62p6WiQICtD48LXiNAXLHqij6Q== X-Google-Smtp-Source: AGHT+IGu+lXy4fpqCbUHElQhH8GUD5tz2EcwDu9oUNJjJ7mXrjL2i+iM+REgc4LlydXeHpBqkSNcvQ== X-Received: by 2002:a05:6a00:248a:b0:68f:ece2:ac2a with SMTP id c10-20020a056a00248a00b0068fece2ac2amr7867812pfv.27.1698082094881; Mon, 23 Oct 2023 10:28:14 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:14 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Atish Patra Subject: [PATCH v11 01/14] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Date: Mon, 23 Oct 2023 22:57:47 +0530 Message-Id: <20231023172800.315343-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails for HARTs disabled in the DT. This results in the following warning thrown by the RISC-V INTC driver for the E-core on SiFive boards: [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt= -controller The riscv_of_parent_hartid() is only expected to read the hartid from the DT so we should directly call of_get_cpu_hwid() instead of calling riscv_of_processor_hartid(). Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c17dacb1141c..157ace8b262c 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct dev= ice_node *node, unsigned lo */ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { - int rc; - for (; node; node =3D node->parent) { if (of_device_is_compatible(node, "riscv")) { - rc =3D riscv_of_processor_hartid(node, hartid); - if (!rc) - return 0; + *hartid =3D (unsigned long)of_get_cpu_hwid(node, 0); + if (*hartid =3D=3D ~0UL) { + pr_warn("Found CPU without hart ID\n"); + return -ENODEV; + } + return 0; } } =20 --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62B88C25B4C for ; Mon, 23 Oct 2023 17:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233422AbjJWR2d (ORCPT ); Mon, 23 Oct 2023 13:28:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232837AbjJWR2Z (ORCPT ); Mon, 23 Oct 2023 13:28:25 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A8FC10E5 for ; Mon, 23 Oct 2023 10:28:20 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6bf03b98b9bso2977123b3a.1 for ; Mon, 23 Oct 2023 10:28:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082100; x=1698686900; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7KBK3NZC+n7aQ9gEOFAwoNpYjPv+cjuqYwdG+XSaoH8=; b=BEMqgJW1giecH+Qg+10tx56SP5QCEtK0Nj3o9nQbSnTLH3aDdpA84jT10NNlE4YAy9 UdLspmpuLRQ+A8LWjghcAVNwmJhPpr07q7TI9aMrbqThlqnaoTEFeAuThgRyqfHdgMQN ttyhRajUhTPlitVuNIr81zsdVkNour8DxeTTdrWK08atoSFJtgMgUGUUQhqpwZmtmETD Xa3BZ+/2SiXpozlN+WBRYpzD0isKHVQ+6j8Y5sbEBWH51ZbHFp2DGw5/Iv0ReMxJjAfo eyW+e/aGa8ncH+3GoCPyMiMqpBJNxLrYFR8pYrexOO9bMvbYjq47PNAbCpXHLi4c6oqf gq0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082100; x=1698686900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7KBK3NZC+n7aQ9gEOFAwoNpYjPv+cjuqYwdG+XSaoH8=; b=eGdZ9auIq6FJ2ngjPCajGMDfsLrCyZ1vMMRJd2K5VOE13tefHmNF6Supk6j1ZhYhFd 7NaoMp0xf2AYkl54SMI1z9ECJ9pRG6aCZD0VGkVFjMuuMnLWhcixMLbOcu3yWUL3Rhlt Lkagl6OJoLJhxnDUOF5aslhI/y9uYtsqpCr1+Vfg4XGVfCW/alLQOKfykt7DYZBb/EvM r1Pmnq0UaTOy8xS/6Q0qwELpMXj+4jJckYR0X2Fs8AhWbHpvomwHS4Fr86RVkNvoeVUQ Ly/QduBzaD/dsTtwLbS/EZhqW1di1LyppjpW73eDJtQPtGFGea+tiswgdHaxdRYiyu8Y pF5w== X-Gm-Message-State: AOJu0YxEXGaPbRjcceb2ypPnvEAzO+GLn99a6uhDuHUC9g2ScLzGl7E1 S5Su2IYsz6XGCpXjaNg7j7AZcg== X-Google-Smtp-Source: AGHT+IEhamlczERwlzDzetrJnAlZ5sdu84K72HLg62pHuk1whfdxvOWdFru0gvqURGDGnkMiM0yB5g== X-Received: by 2002:a05:6a20:4323:b0:15d:1646:285a with SMTP id h35-20020a056a20432300b0015d1646285amr279865pzk.21.1698082100040; Mon, 23 Oct 2023 10:28:20 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:19 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Rob Herring Subject: [PATCH v11 02/14] of: property: Add fw_devlink support for msi-parent Date: Mon, 23 Oct 2023 22:57:48 +0530 Message-Id: <20231023172800.315343-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This allows fw_devlink to create device links between consumers of a MSI and the supplier of the MSI. Signed-off-by: Anup Patel Acked-by: Rob Herring Reviewed-by: Saravana Kannan --- drivers/of/property.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c index cf8dacf3e3b8..afdaefbd03f6 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1267,6 +1267,7 @@ DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells") DEFINE_SIMPLE_PROP(leds, "leds", NULL) DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) DEFINE_SIMPLE_PROP(panel, "panel", NULL) +DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells") DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") =20 @@ -1356,6 +1357,7 @@ static const struct supplier_bindings of_supplier_bin= dings[] =3D { { .parse_prop =3D parse_leds, }, { .parse_prop =3D parse_backlight, }, { .parse_prop =3D parse_panel, }, + { .parse_prop =3D parse_msi_parent, }, { .parse_prop =3D parse_gpio_compat, }, { .parse_prop =3D parse_interrupts, }, { .parse_prop =3D parse_regulators, }, --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66D3EC25B45 for ; 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Mon, 23 Oct 2023 10:28:25 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:24 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 03/14] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Date: Mon, 23 Oct 2023 22:57:49 +0530 Message-Id: <20231023172800.315343-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On multi-socket systems, we will have a separate PLIC in each socket so we should register syscore operation only once for multi-socket systems. Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hi= bernation") Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index e1484905b7bd..5b7bc4fd9517 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -532,17 +532,18 @@ static int __init __plic_init(struct device_node *nod= e, } =20 /* - * We can have multiple PLIC instances so setup cpuhp state only - * when context handler for current/boot CPU is present. + * We can have multiple PLIC instances so setup cpuhp state + * and register syscore operations only when context handler + * for current/boot CPU is present. */ handler =3D this_cpu_ptr(&plic_handlers); if (handler->present && !plic_cpuhp_setup_done) { cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); + register_syscore_ops(&plic_irq_syscore_ops); plic_cpuhp_setup_done =3D true; } - register_syscore_ops(&plic_irq_syscore_ops); =20 pr_info("%pOFP: mapped %d interrupts with %d handlers for" " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28072C25B46 for ; Mon, 23 Oct 2023 17:29:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233713AbjJWR2y (ORCPT ); Mon, 23 Oct 2023 13:28:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233483AbjJWR2j (ORCPT ); Mon, 23 Oct 2023 13:28:39 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F85F10EB for ; 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Mon, 23 Oct 2023 10:28:29 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 04/14] irqchip/sifive-plic: Convert PLIC driver into a platform driver Date: Mon, 23 Oct 2023 22:57:50 +0530 Message-Id: <20231023172800.315343-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PLIC driver does not require very early initialization so let us convert it into a platform driver. As part of the conversion, the PLIC probing undergoes the following changes: 1. Use dev_info(), dev_err() and dev_warn() instead of pr_info(), pr_err() and pr_warn() 2. Use devm_xyz() APIs wherever applicable 3. PLIC is now probed after CPUs are brought-up so we have to setup cpuhp state after context handler of all online CPUs are initialized otherwise we see crash on multi-socket systems Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 239 ++++++++++++++++++------------ 1 file changed, 148 insertions(+), 91 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 5b7bc4fd9517..c8f8a8cdcce1 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ -#define pr_fmt(fmt) "plic: " fmt #include #include #include @@ -64,6 +63,7 @@ #define PLIC_QUIRK_EDGE_INTERRUPT 0 =20 struct plic_priv { + struct device *dev; struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; @@ -85,7 +85,6 @@ struct plic_handler { struct plic_priv *priv; }; static int plic_parent_irq __ro_after_init; -static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); =20 static int plic_irq_set_type(struct irq_data *d, unsigned int type); @@ -371,7 +370,8 @@ static void plic_handle_irq(struct irq_desc *desc) int err =3D generic_handle_domain_irq(handler->priv->irqdomain, hwirq); if (unlikely(err)) - pr_warn_ratelimited("can't find mapping for hwirq %lu\n", + dev_warn_ratelimited(handler->priv->dev, + "can't find mapping for hwirq %lu\n", hwirq); } =20 @@ -406,57 +406,126 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } =20 -static int __init __plic_init(struct device_node *node, - struct device_node *parent, - unsigned long plic_quirks) +static const struct of_device_id plic_match[] =3D { + { .compatible =3D "sifive,plic-1.0.0" }, + { .compatible =3D "riscv,plic0" }, + { .compatible =3D "andestech,nceplic100", + .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + { .compatible =3D "thead,c900-plic", + .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + {} +}; + +static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, + u32 *nr_irqs, u32 *nr_contexts) { - int error =3D 0, nr_contexts, nr_handlers =3D 0, i; - u32 nr_irqs; - struct plic_priv *priv; + struct device *dev =3D &pdev->dev; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_property_read_u32(to_of_node(dev->fwnode), + "riscv,ndev", nr_irqs); + if (rc) { + dev_err(dev, "riscv,ndev property not available\n"); + return rc; + } + + *nr_contexts =3D of_irq_count(to_of_node(dev->fwnode)); + if (WARN_ON(!(*nr_contexts))) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + return 0; +} + +static int plic_parse_context_parent_hwirq(struct platform_device *pdev, + u32 context, u32 *parent_hwirq, + unsigned long *parent_hartid) +{ + struct device *dev =3D &pdev->dev; + struct of_phandle_args parent; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D parent.args[0]; + return 0; +} + +static int plic_probe(struct platform_device *pdev) +{ + int rc, nr_contexts, nr_handlers =3D 0, i, cpu; + unsigned long plic_quirks =3D 0, hartid; + struct device *dev =3D &pdev->dev; struct plic_handler *handler; - unsigned int cpu; + u32 nr_irqs, parent_hwirq; + struct irq_domain *domain; + struct plic_priv *priv; + irq_hw_number_t hwirq; + struct resource *res; + bool cpuhp_setup; + + if (is_of_node(dev->fwnode)) { + const struct of_device_id *id; + + id =3D of_match_node(plic_match, to_of_node(dev->fwnode)); + if (id) + plic_quirks =3D (unsigned long)id->data; + } =20 - priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - + priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; =20 - priv->regs =3D of_iomap(node, 0); - if (WARN_ON(!priv->regs)) { - error =3D -EIO; - goto out_free_priv; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "failed to get MMIO resource\n"); + return -EINVAL; + } + priv->regs =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->regs) { + dev_err(dev, "failed map MMIO registers\n"); + return -EIO; } =20 - error =3D -EINVAL; - of_property_read_u32(node, "riscv,ndev", &nr_irqs); - if (WARN_ON(!nr_irqs)) - goto out_iounmap; - + rc =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + if (rc) { + dev_err(dev, "failed to parse irqs and contexts\n"); + return rc; + } priv->nr_irqs =3D nr_irqs; =20 - priv->prio_save =3D bitmap_alloc(nr_irqs, GFP_KERNEL); + priv->prio_save =3D devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); if (!priv->prio_save) - goto out_free_priority_reg; - - nr_contexts =3D of_irq_count(node); - if (WARN_ON(!nr_contexts)) - goto out_free_priority_reg; - - error =3D -ENOMEM; - priv->irqdomain =3D irq_domain_add_linear(node, nr_irqs + 1, - &plic_irqdomain_ops, priv); - if (WARN_ON(!priv->irqdomain)) - goto out_free_priority_reg; + return -ENOMEM; =20 for (i =3D 0; i < nr_contexts; i++) { - struct of_phandle_args parent; - irq_hw_number_t hwirq; - int cpu; - unsigned long hartid; - - if (of_irq_parse_one(node, i, &parent)) { - pr_err("failed to parse parent for context %d.\n", i); + rc =3D plic_parse_context_parent_hwirq(pdev, i, + &parent_hwirq, &hartid); + if (rc) { + dev_warn(dev, "hwirq for context%d not found\n", i); continue; } =20 @@ -464,7 +533,7 @@ static int __init __plic_init(struct device_node *node, * Skip contexts other than external interrupts for our * privilege level. */ - if (parent.args[0] !=3D RV_IRQ_EXT) { + if (parent_hwirq !=3D RV_IRQ_EXT) { /* Disable S-mode enable bits if running in M-mode. */ if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { void __iomem *enable_base =3D priv->regs + @@ -477,21 +546,17 @@ static int __init __plic_init(struct device_node *nod= e, continue; } =20 - error =3D riscv_of_parent_hartid(parent.np, &hartid); - if (error < 0) { - pr_warn("failed to parse hart ID for context %d.\n", i); - continue; - } - cpu =3D riscv_hartid_to_cpuid(hartid); if (cpu < 0) { - pr_warn("Invalid cpuid for context %d\n", i); + dev_warn(dev, "Invalid cpuid for context %d\n", i); continue; } =20 /* Find parent domain and register chained handler */ - if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq =3D irq_of_parse_and_map(node, i); + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!plic_parent_irq && domain) { + plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); if (plic_parent_irq) irq_set_chained_handler(plic_parent_irq, plic_handle_irq); @@ -504,7 +569,7 @@ static int __init __plic_init(struct device_node *node, */ handler =3D per_cpu_ptr(&plic_handlers, cpu); if (handler->present) { - pr_warn("handler already present for context %d.\n", i); + dev_warn(dev, "handler already present for context%d.\n", i); plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); goto done; } @@ -518,10 +583,13 @@ static int __init __plic_init(struct device_node *nod= e, i * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 - handler->enable_save =3D kcalloc(DIV_ROUND_UP(nr_irqs, 32), - sizeof(*handler->enable_save), GFP_KERNEL); + handler->enable_save =3D devm_kcalloc(dev, + DIV_ROUND_UP(nr_irqs, 32), + sizeof(*handler->enable_save), + GFP_KERNEL); if (!handler->enable_save) - goto out_free_enable_reg; + return -ENOMEM; + done: for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -531,52 +599,41 @@ static int __init __plic_init(struct device_node *nod= e, nr_handlers++; } =20 + priv->irqdomain =3D irq_domain_create_linear(dev->fwnode, nr_irqs + 1, + &plic_irqdomain_ops, priv); + if (WARN_ON(!priv->irqdomain)) + return -ENOMEM; + /* * We can have multiple PLIC instances so setup cpuhp state - * and register syscore operations only when context handler - * for current/boot CPU is present. + * and register syscore operations only after context handlers + * of all online CPUs are initialized. */ - handler =3D this_cpu_ptr(&plic_handlers); - if (handler->present && !plic_cpuhp_setup_done) { + cpuhp_setup =3D true; + for_each_online_cpu(cpu) { + handler =3D per_cpu_ptr(&plic_handlers, cpu); + if (!handler->present) { + cpuhp_setup =3D false; + break; + } + } + if (cpuhp_setup) { cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); register_syscore_ops(&plic_irq_syscore_ops); - plic_cpuhp_setup_done =3D true; } =20 - pr_info("%pOFP: mapped %d interrupts with %d handlers for" - " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); + dev_info(dev, "mapped %d interrupts with %d handlers for" + " %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; - -out_free_enable_reg: - for_each_cpu(cpu, cpu_present_mask) { - handler =3D per_cpu_ptr(&plic_handlers, cpu); - kfree(handler->enable_save); - } -out_free_priority_reg: - kfree(priv->prio_save); -out_iounmap: - iounmap(priv->regs); -out_free_priv: - kfree(priv); - return error; } =20 -static int __init plic_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, 0); -} - -IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); -IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy syst= ems */ - -static int __init plic_edge_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); -} - -IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_in= it); -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); +static struct platform_driver plic_driver =3D { + .driver =3D { + .name =3D "riscv-plic", + .of_match_table =3D plic_match, + }, + .probe =3D plic_probe, +}; +builtin_platform_driver(plic_driver); --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38580C25B46 for ; Mon, 23 Oct 2023 17:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233392AbjJWR3J (ORCPT ); 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Mon, 23 Oct 2023 10:28:34 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Date: Mon, 23 Oct 2023 22:57:51 +0530 Message-Id: <20231023172800.315343-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index e8d01b14ccdd..bab536bbaf2c 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) generic_handle_domain_irq(intc_domain, cause); } =20 +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi =3D csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *r= egs) =20 static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) =20 static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs =3D riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain =3D irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } =20 - rc =3D set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc =3D set_handle_irq(&riscv_intc_aia_irq); + else + rc =3D set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); =20 return 0; } --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64773C25B46 for ; Mon, 23 Oct 2023 17:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233462AbjJWR3M (ORCPT ); Mon, 23 Oct 2023 13:29:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233686AbjJWR2v (ORCPT ); Mon, 23 Oct 2023 13:28:51 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DED610DA for ; Mon, 23 Oct 2023 10:28:42 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6bf03b98b9bso2977438b3a.1 for ; Mon, 23 Oct 2023 10:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082121; x=1698686921; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=MBEAcQNaVfouY4DLGgr4Ttu9xxHBC5rNa6lOMlJAHnBaxyb+yE0DYEdQtESdtWiFAQ DZOFe3+s1Gz+Rxb+ftXsZR64xCMjP+rDaRdTBBTc3/hMpW0vbwtX3ZVcrnm+IDLDITje BnZRu5gFaFOWTKL5Ajk988UzEY5u28NBRLXrRGgZYRrOCP3nwPLqJ3szCTYJ8tqWSdtC Iq/Pk6aAsZneA2tl5HL46hoaWis8Og+Rh/WeoSefKYItwXnj5SsXdiejx/VKa2pa0GWq ubMRl8hF7GrydIpxWPUtoFzI1s4YgR7IlG7ujDdP2VZH2bpeZxXN/qBHlCii2X/Hd2dh MsxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082121; x=1698686921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=Bh0MP2AifiqWXjcQn327Bc6ekRy7q6dyhDCrldoW7XK5fBUSh4MWUh8qYuLF+BKNJF MZpUf7pCrFLN4RhWGTFRHRAPn5AeE75vq3S0lv5YP/hrn1aJAlmeXWi+zLr2iY05h7xJ KPzQAXQIgGmQuparF/lPdk5garsLnSzCF1l5uSDZIkwjn+GIB7XHbq7p9TFL8eAC4jkP cXhh2r158dX13OE9GFvLukqxGGGZpSyUzIlCdY2gDf9Ny+QH6n0aYjxoRbmnPjtKYb/B peRKR91G/lVFltSo7JI/FBftchTS31SntKxkcHFSEHJODLqS4HjHpxwHJfmQ42XFizI/ MK2A== X-Gm-Message-State: AOJu0YzocrCzFjzgWGrFAzVqddW7LVJaX9pMty48SL2WX4zrajiwze6w +BD3a2RdYVJpO5+v4Wyp/FK4UA== X-Google-Smtp-Source: AGHT+IHjZmaPWHJKgHDWOkQn7NYMpmikR1Md77Q77YkCAlgBwgoG4xzlG1Ef9LTYAvvlQB1Zs8aGAw== X-Received: by 2002:a05:6a20:12c5:b0:17b:1f76:86ee with SMTP id v5-20020a056a2012c500b0017b1f7686eemr330797pzg.16.1698082120832; Mon, 23 Oct 2023 10:28:40 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:40 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v11 06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Date: Mon, 23 Oct 2023 22:57:52 +0530 Message-Id: <20231023172800.315343-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for the RISC-V incoming MSI controller (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,imsics.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml new file mode 100644 index 000000000000..84976f17a4a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Incoming MSI Controller (IMSIC) + +maintainers: + - Anup Patel + +description: | + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incom= ing + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V + AIA specification can be found at https://github.com/riscv/riscv-aia. + + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file + for each privilege level (machine or supervisor). The configuration of + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO + space to receive MSIs from devices. Each IMSIC interrupt file supports a + fixed number of interrupt identities (to distinguish MSIs from devices) + which is same for given privilege level across CPUs (or HARTs). + + The device tree of a RISC-V platform will have one IMSIC device tree node + for each privilege level (machine or supervisor) which collectively desc= ribe + IMSIC interrupt files at that privilege level across CPUs (or HARTs). + + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platf= orm + follows a particular scheme defined by the RISC-V AIA specification. A I= MSIC + group is a set of IMSIC interrupt files co-located in MMIO space and we = can + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a + RISC-V platform. The MSI target address of a IMSIC interrupt file at giv= en + privilege level (machine or supervisor) encodes group index, HART index, + and guest index (shown below). + + XLEN-1 > (HART Index MSB) 12 0 + | | | | + ------------------------------------------------------------- + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + ------------------------------------------------------------- + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,imsics + - const: riscv,imsics + + reg: + minItems: 1 + maxItems: 16384 + description: + Base address of each IMSIC group. + + interrupt-controller: true + + "#interrupt-cells": + const: 0 + + msi-controller: true + + "#msi-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + This property represents the set of CPUs (or HARTs) for which given + device tree node describes the IMSIC interrupt files. Each node poin= ted + to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V + HART) as parent. + + riscv,num-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities supported by IMSIC interrupt file. + + riscv,num-guest-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities are supported by IMSIC guest interrupt + file. When not specified it is assumed to be same as specified by the + riscv,num-ids property. + + riscv,guest-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of guest index bits in the MSI target address. + + riscv,hart-index-bits: + minimum: 0 + maximum: 15 + description: + Number of HART index bits in the MSI target address. When not + specified it is calculated based on the interrupts-extended property. + + riscv,group-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of group index bits in the MSI target address. + + riscv,group-index-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 55 + default: 24 + description: + The least significant bit position of the group index bits in the + MSI target address. + +required: + - compatible + - reg + - interrupt-controller + - msi-controller + - "#msi-cells" + - interrupts-extended + - riscv,num-ids + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Machine-level IMSIC files with just one group): + + interrupt-controller@24000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0x28000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + }; + + - | + // Example 2 (Supervisor-level IMSIC files with two groups): + + interrupt-controller@28000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>, + <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0x28000000 0x2000>, /* Group0 IMSICs */ + <0x29000000 0x2000>; /* Group1 IMSICs */ + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + riscv,group-index-bits =3D <1>; + riscv,group-index-shift =3D <24>; + }; +... --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76104C25B46 for ; Mon, 23 Oct 2023 17:29:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232014AbjJWR31 (ORCPT ); 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Mon, 23 Oct 2023 10:28:45 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver Date: Mon, 23 Oct 2023 22:57:53 +0530 Message-Id: <20231023172800.315343-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) specification defines a new MSI controller called incoming message signalled interrupt controller (IMSIC) which manages MSI on per-HART (or per-CPU) basis. It also supports IPIs as software injected MSIs. (For more details refer https://github.com/riscv/riscv-aia) Let us add an early irqchip driver for RISC-V IMSIC which sets up the IMSIC state and provide IPIs. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-imsic-early.c | 235 ++++++ drivers/irqchip/irq-riscv-imsic-state.c | 962 ++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 109 +++ include/linux/irqchip/riscv-imsic.h | 87 +++ 6 files changed, 1400 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-imsic-early.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.c create mode 100644 drivers/irqchip/irq-riscv-imsic-state.h create mode 100644 include/linux/irqchip/riscv-imsic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f7149d0f3d45..bdd80716114d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -546,6 +546,12 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 +config RISCV_IMSIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ffd945fe71aa..d714724387ce 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o +obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c new file mode 100644 index 000000000000..23f689ff5807 --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-imsic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-imsic-state.h" + +static int imsic_parent_irq; + +#ifdef CONFIG_SMP +static irqreturn_t imsic_local_sync_handler(int irq, void *data) +{ + imsic_local_sync(); + return IRQ_HANDLED; +} + +static void imsic_ipi_send(unsigned int cpu) +{ + struct imsic_local_config *local =3D + per_cpu_ptr(imsic->global.local, cpu); + + writel(IMSIC_IPI_ID, local->msi_va); +} + +static void imsic_ipi_starting_cpu(void) +{ + /* Enable IPIs for current CPU. */ + __imsic_id_set_enable(IMSIC_IPI_ID); + + /* Enable virtual IPI used for IMSIC ID synchronization */ + enable_percpu_irq(imsic->ipi_virq, 0); +} + +static void imsic_ipi_dying_cpu(void) +{ + /* + * Disable virtual IPI used for IMSIC ID synchronization so + * that we don't receive ID synchronization requests. + */ + disable_percpu_irq(imsic->ipi_virq); +} + +static int __init imsic_ipi_domain_init(void) +{ + int virq; + + /* Create IMSIC IPI multiplexing */ + virq =3D ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); + if (virq <=3D 0) + return (virq < 0) ? virq : -ENOMEM; + imsic->ipi_virq =3D virq; + + /* First vIRQ is used for IMSIC ID synchronization */ + virq =3D request_percpu_irq(imsic->ipi_virq, imsic_local_sync_handler, + "riscv-imsic-lsync", imsic->global.local); + if (virq) + return virq; + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); + imsic->ipi_lsync_desc =3D irq_to_desc(imsic->ipi_virq); + + /* Set vIRQ range */ + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); + + /* Announce that IMSIC is providing IPIs */ + pr_info("%pfwP: providing IPIs using interrupt %d\n", + imsic->fwnode, IMSIC_IPI_ID); + + return 0; +} +#else +static void imsic_ipi_starting_cpu(void) +{ +} + +static void imsic_ipi_dying_cpu(void) +{ +} + +static int __init imsic_ipi_domain_init(void) +{ + return 0; +} +#endif + +/* + * To handle an interrupt, we read the TOPEI CSR and write zero in one + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to + * Linux interrupt number and let Linux IRQ subsystem handle it. + */ +static void imsic_handle_irq(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + int err, cpu =3D smp_processor_id(); + struct imsic_vector *vec; + unsigned long local_id; + + chained_irq_enter(chip, desc); + + while ((local_id =3D csr_swap(CSR_TOPEI, 0))) { + local_id =3D local_id >> TOPEI_ID_SHIFT; + + if (local_id =3D=3D IMSIC_IPI_ID) { +#ifdef CONFIG_SMP + ipi_mux_process(); +#endif + continue; + } + + if (unlikely(!imsic->base_domain)) + continue; + + vec =3D imsic_vector_from_local_id(cpu, local_id); + if (!vec) { + pr_warn_ratelimited( + "vector not found for local ID 0x%lx\n", + local_id); + continue; + } + + err =3D generic_handle_domain_irq(imsic->base_domain, + vec->hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "hwirq 0x%x mapping not found\n", + vec->hwirq); + } + + chained_irq_exit(chip, desc); +} + +static int imsic_starting_cpu(unsigned int cpu) +{ + /* Enable per-CPU parent interrupt */ + enable_percpu_irq(imsic_parent_irq, + irq_get_trigger_type(imsic_parent_irq)); + + /* Setup IPIs */ + imsic_ipi_starting_cpu(); + + /* + * Interrupts identities might have been enabled/disabled while + * this CPU was not running so sync-up local enable/disable state. + */ + imsic_local_sync(); + + /* Enable local interrupt delivery */ + imsic_local_delivery(true); + + return 0; +} + +static int imsic_dying_cpu(unsigned int cpu) +{ + /* Cleanup IPIs */ + imsic_ipi_dying_cpu(); + + return 0; +} + +static int __init imsic_early_probe(struct fwnode_handle *fwnode) +{ + int rc; + struct irq_domain *domain; + + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + return -ENOENT; + } + imsic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (!imsic_parent_irq) { + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); + return -ENOENT; + } + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); + + /* Initialize IPI domain */ + rc =3D imsic_ipi_domain_init(); + if (rc) { + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); + return rc; + } + + /* + * Setup cpuhp state (must be done after setting imsic_parent_irq) + * + * Don't disable per-CPU IMSIC file when CPU goes offline + * because this affects IPI and the masking/unmasking of + * virtual IPIs is done via generic IPI-Mux + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/imsic:starting", + imsic_starting_cpu, imsic_dying_cpu); + + return 0; +} + +static int __init imsic_early_dt_init(struct device_node *node, + struct device_node *parent) +{ + int rc; + struct fwnode_handle *fwnode =3D &node->fwnode; + + /* Setup IMSIC state */ + rc =3D imsic_setup_state(fwnode); + if (rc) { + pr_err("%pfwP: failed to setup state (error %d)\n", + fwnode, rc); + return rc; + } + + /* Do early setup of IPIs */ + rc =3D imsic_early_probe(fwnode); + if (rc) + return rc; + + /* Ensure that OF platform device gets probed */ + of_node_clear_flag(node, OF_POPULATED); + return 0; +} +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c new file mode 100644 index 000000000000..54465e47851c --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -0,0 +1,962 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-imsic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-imsic-state.h" + +#define IMSIC_DISABLE_EIDELIVERY 0 +#define IMSIC_ENABLE_EIDELIVERY 1 +#define IMSIC_DISABLE_EITHRESHOLD 1 +#define IMSIC_ENABLE_EITHRESHOLD 0 + +#define imsic_csr_write(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_write(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_read(__c) \ +({ \ + unsigned long __v; \ + csr_write(CSR_ISELECT, __c); \ + __v =3D csr_read(CSR_IREG); \ + __v; \ +}) + +#define imsic_csr_read_clear(__c, __v) \ +({ \ + unsigned long __r; \ + csr_write(CSR_ISELECT, __c); \ + __r =3D csr_read_clear(CSR_IREG, __v); \ + __r; \ +}) + +#define imsic_csr_set(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_set(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_clear(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_clear(CSR_IREG, __v); \ +} while (0) + +struct imsic_priv *imsic; + +const struct imsic_global_config *imsic_get_global_config(void) +{ + return (imsic) ? &imsic->global : NULL; +} +EXPORT_SYMBOL_GPL(imsic_get_global_config); + +static bool __imsic_eix_read_clear(unsigned long id, bool pend) +{ + unsigned long isel, imask; + + isel =3D id / BITS_PER_LONG; + isel *=3D BITS_PER_LONG / IMSIC_EIPx_BITS; + isel +=3D (pend) ? IMSIC_EIP0 : IMSIC_EIE0; + imask =3D BIT(id & (__riscv_xlen - 1)); + + return (imsic_csr_read_clear(isel, imask) & imask) ? true : false; +} + +#define __imsic_id_read_clear_enabled(__id) \ + __imsic_eix_read_clear((__id), false) +#define __imsic_id_read_clear_pending(__id) \ + __imsic_eix_read_clear((__id), true) + +void __imsic_eix_update(unsigned long base_id, + unsigned long num_id, bool pend, bool val) +{ + unsigned long i, isel, ireg; + unsigned long id =3D base_id, last_id =3D base_id + num_id; + + while (id < last_id) { + isel =3D id / BITS_PER_LONG; + isel *=3D BITS_PER_LONG / IMSIC_EIPx_BITS; + isel +=3D (pend) ? IMSIC_EIP0 : IMSIC_EIE0; + + ireg =3D 0; + for (i =3D id & (__riscv_xlen - 1); + (id < last_id) && (i < __riscv_xlen); i++) { + ireg |=3D BIT(i); + id++; + } + + /* + * The IMSIC EIEx and EIPx registers are indirectly + * accessed via using ISELECT and IREG CSRs so we + * need to access these CSRs without getting preempted. + * + * All existing users of this function call this + * function with local IRQs disabled so we don't + * need to do anything special here. + */ + if (val) + imsic_csr_set(isel, ireg); + else + imsic_csr_clear(isel, ireg); + } +} + +void imsic_local_sync(void) +{ + struct imsic_local_priv *lpriv =3D this_cpu_ptr(imsic->lpriv); + struct imsic_local_config *mlocal; + struct imsic_vector *mvec; + unsigned long flags; + int i; + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + for (i =3D 1; i <=3D imsic->global.nr_ids; i++) { + if (i =3D=3D IMSIC_IPI_ID) + continue; + + if (test_bit(i, lpriv->ids_enabled_bitmap)) + __imsic_id_set_enable(i); + else + __imsic_id_clear_enable(i); + + mvec =3D lpriv->ids_move[i]; + lpriv->ids_move[i] =3D NULL; + if (mvec) { + if (__imsic_id_read_clear_pending(i)) { + mlocal =3D per_cpu_ptr(imsic->global.local, + mvec->cpu); + writel(mvec->local_id, mlocal->msi_va); + } + + lpriv->vectors[i].hwirq =3D UINT_MAX; + lpriv->vectors[i].order =3D UINT_MAX; + clear_bit(i, lpriv->ids_used_bitmap); + } + + } + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); +} + +void imsic_local_delivery(bool enable) +{ + if (enable) { + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); + } else { + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); + } +} + +#ifdef CONFIG_SMP +static void imsic_remote_sync(unsigned int cpu) +{ + /* + * We simply inject ID synchronization IPI to a target CPU + * if it is not same as the current CPU. The ipi_send_mask() + * implementation of IPI mux will inject ID synchronization + * IPI only for CPUs that have enabled it so offline CPUs + * won't receive IPI. An offline CPU will unconditionally + * synchronize IDs through imsic_starting_cpu() when the + * CPU is brought up. + */ + if (cpu_online(cpu)) { + if (cpu !=3D smp_processor_id()) + __ipi_send_mask(imsic->ipi_lsync_desc, cpumask_of(cpu)); + else + imsic_local_sync(); + } +} +#else +static inline void imsic_remote_sync(unsigned int cpu) +{ + imsic_local_sync(); +} +#endif + +void imsic_vector_mask(struct imsic_vector *vec) +{ + struct imsic_local_priv *lpriv; + unsigned long flags; + + lpriv =3D per_cpu_ptr(imsic->lpriv, vec->cpu); + if (WARN_ON(&lpriv->vectors[vec->local_id] !=3D vec)) + return; + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + bitmap_clear(lpriv->ids_enabled_bitmap, vec->local_id, 1); + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + + imsic_remote_sync(vec->cpu); +} + +void imsic_vector_unmask(struct imsic_vector *vec) +{ + struct imsic_local_priv *lpriv; + unsigned long flags; + + lpriv =3D per_cpu_ptr(imsic->lpriv, vec->cpu); + if (WARN_ON(&lpriv->vectors[vec->local_id] !=3D vec)) + return; + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + bitmap_set(lpriv->ids_enabled_bitmap, vec->local_id, 1); + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + + imsic_remote_sync(vec->cpu); +} + +void imsic_vector_move(struct imsic_vector *old_vec, + struct imsic_vector *new_vec) +{ + struct imsic_local_priv *old_lpriv, *new_lpriv; + struct imsic_vector *ovec, *nvec; + unsigned long flags, flags1; + unsigned int i; + + if (WARN_ON(old_vec->cpu =3D=3D new_vec->cpu || + old_vec->order !=3D new_vec->order || + (old_vec->local_id & IMSIC_VECTOR_MASK(old_vec)) || + (new_vec->local_id & IMSIC_VECTOR_MASK(new_vec)))) + return; + + old_lpriv =3D per_cpu_ptr(imsic->lpriv, old_vec->cpu); + if (WARN_ON(&old_lpriv->vectors[old_vec->local_id] !=3D old_vec)) + return; + + new_lpriv =3D per_cpu_ptr(imsic->lpriv, new_vec->cpu); + if (WARN_ON(&new_lpriv->vectors[new_vec->local_id] !=3D new_vec)) + return; + + raw_spin_lock_irqsave(&old_lpriv->ids_lock, flags); + raw_spin_lock_irqsave(&new_lpriv->ids_lock, flags1); + + /* Move the state of each vector entry */ + for (i =3D 0; i < BIT(old_vec->order); i++) { + ovec =3D old_vec + i; + nvec =3D new_vec + i; + + /* Unmask the new vector entry */ + if (test_bit(ovec->local_id, old_lpriv->ids_enabled_bitmap)) + bitmap_set(new_lpriv->ids_enabled_bitmap, + nvec->local_id, 1); + + /* Mask the old vector entry */ + bitmap_clear(old_lpriv->ids_enabled_bitmap, ovec->local_id, 1); + + /* + * Move and re-trigger the new vector entry based on the + * pending state of the old vector entry because we might + * get a device interrupt on the old vector entry while + * device was being moved to the new vector entry. + */ + old_lpriv->ids_move[ovec->local_id] =3D nvec; + } + + raw_spin_unlock_irqrestore(&new_lpriv->ids_lock, flags1); + raw_spin_unlock_irqrestore(&old_lpriv->ids_lock, flags); + + imsic_remote_sync(old_vec->cpu); + imsic_remote_sync(new_vec->cpu); +} + +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS +void imsic_vector_debug_show(struct seq_file *m, + struct imsic_vector *vec, int ind) +{ + unsigned int mcpu =3D 0, mlocal_id =3D 0; + struct imsic_local_priv *lpriv; + bool move_in_progress =3D false; + struct imsic_vector *mvec; + bool is_enabled =3D false; + unsigned long flags; + + lpriv =3D per_cpu_ptr(imsic->lpriv, vec->cpu); + if (WARN_ON(&lpriv->vectors[vec->local_id] !=3D vec)) + return; + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + if (test_bit(vec->local_id, lpriv->ids_enabled_bitmap)) + is_enabled =3D true; + mvec =3D lpriv->ids_move[vec->local_id]; + if (mvec) { + move_in_progress =3D true; + mcpu =3D mvec->cpu; + mlocal_id =3D mvec->local_id; + } + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + + seq_printf(m, "%*starget_cpu : %5u\n", ind, "", vec->cpu); + seq_printf(m, "%*starget_local_id : %5u\n", ind, "", vec->local_id); + seq_printf(m, "%*sis_reserved : %5u\n", ind, "", + (vec->local_id <=3D IMSIC_IPI_ID) ? 1 : 0); + seq_printf(m, "%*sis_enabled : %5u\n", ind, "", + (move_in_progress) ? 1 : 0); + seq_printf(m, "%*sis_move_pending : %5u\n", ind, "", + (move_in_progress) ? 1 : 0); + if (move_in_progress) { + seq_printf(m, "%*smove_cpu : %5u\n", ind, "", mcpu); + seq_printf(m, "%*smove_local_id : %5u\n", ind, "", mlocal_id); + } +} + +void imsic_vector_debug_show_summary(struct seq_file *m, int ind) +{ + unsigned int cpu, total_avail =3D 0, total_used =3D 0; + struct imsic_global_config *global =3D &imsic->global; + struct imsic_local_priv *lpriv; + unsigned long flags; + + for_each_possible_cpu(cpu) { + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + + total_avail +=3D global->nr_ids; + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + total_used +=3D bitmap_weight(lpriv->ids_used_bitmap, + global->nr_ids + 1) - 1; + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + } + + seq_printf(m, "%*stotal : %5u\n", ind, "", total_avail); + seq_printf(m, "%*sused : %5u\n", ind, "", total_used); + seq_printf(m, "%*s| CPU | tot | usd | vectors\n", ind, " "); + + cpus_read_lock(); + for_each_online_cpu(cpu) { + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + total_used =3D bitmap_weight(lpriv->ids_used_bitmap, + global->nr_ids + 1) - 1; + seq_printf(m, "%*s %4d %4u %4u %*pbl\n", ind, " ", + cpu, global->nr_ids, total_used, + global->nr_ids + 1, lpriv->ids_used_bitmap); + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + } + cpus_read_unlock(); +} +#endif + +struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, + unsigned int local_id) +{ + struct imsic_local_priv *lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + + if (!lpriv || imsic->global.nr_ids < local_id) + return NULL; + + return &lpriv->vectors[local_id]; +} + +static unsigned int imsic_vector_best_cpu(const struct cpumask *mask, + unsigned int order) +{ + struct imsic_global_config *global =3D &imsic->global; + unsigned int cpu, best_cpu, free, maxfree =3D 0; + struct imsic_local_priv *lpriv; + unsigned long flags; + + best_cpu =3D UINT_MAX; + for_each_cpu(cpu, mask) { + if (!cpu_online(cpu)) + continue; + + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + free =3D bitmap_weight(lpriv->ids_used_bitmap, + global->nr_ids + 1); + free =3D (global->nr_ids + 1) - free; + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + + if (free < BIT(order) || free <=3D maxfree) + continue; + + best_cpu =3D cpu; + maxfree =3D free; + } + + return best_cpu; +} + +struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, + const struct cpumask *mask, + unsigned int order) +{ + struct imsic_vector *vec =3D NULL; + struct imsic_local_priv *lpriv; + unsigned long flags; + unsigned int cpu; + int i, local_id; + + if (!mask || cpumask_empty(mask)) + return NULL; + + cpu =3D imsic_vector_best_cpu(mask, order); + if (cpu =3D=3D UINT_MAX) + return NULL; + + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + local_id =3D bitmap_find_free_region(lpriv->ids_used_bitmap, + imsic->global.nr_ids + 1, + order); + if (local_id > 0) { + for (i =3D 0; i < BIT(order); i++) { + vec =3D &lpriv->vectors[local_id + i]; + vec->hwirq =3D hwirq + i; + vec->order =3D order; + } + vec =3D &lpriv->vectors[local_id]; + } + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); + + return vec; +} + +void imsic_vector_free(struct imsic_vector *vec) +{ + unsigned int i, local_id, order; + struct imsic_local_priv *lpriv; + struct imsic_vector *tvec; + unsigned long flags; + + if (WARN_ON(vec->hwirq =3D=3D UINT_MAX || vec->order =3D=3D UINT_MAX)) + return; + + lpriv =3D per_cpu_ptr(imsic->lpriv, vec->cpu); + if (WARN_ON(&lpriv->vectors[vec->local_id] !=3D vec)) + return; + + order =3D vec->order; + local_id =3D IMSIC_VECTOR_BASE_LOCAL_ID(vec); + + raw_spin_lock_irqsave(&lpriv->ids_lock, flags); + for (i =3D 0; i < BIT(order); i++) { + tvec =3D &lpriv->vectors[local_id + i]; + tvec->hwirq =3D UINT_MAX; + tvec->order =3D UINT_MAX; + } + bitmap_release_region(lpriv->ids_used_bitmap, local_id, order); + raw_spin_unlock_irqrestore(&lpriv->ids_lock, flags); +} + +static void __init imsic_local_cleanup(void) +{ + int cpu; + struct imsic_local_priv *lpriv; + + for_each_possible_cpu(cpu) { + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + + bitmap_free(lpriv->ids_enabled_bitmap); + bitmap_free(lpriv->ids_used_bitmap); + kfree(lpriv->ids_move); + kfree(lpriv->vectors); + } + + free_percpu(imsic->lpriv); +} + +static int __init imsic_local_init(void) +{ + struct imsic_global_config *global =3D &imsic->global; + struct imsic_local_priv *lpriv; + struct imsic_vector *vec; + int cpu, i; + + /* Allocate per-CPU private state */ + imsic->lpriv =3D alloc_percpu(typeof(*(imsic->lpriv))); + if (!imsic->lpriv) + return -ENOMEM; + + /* Setup per-CPU private state */ + for_each_possible_cpu(cpu) { + lpriv =3D per_cpu_ptr(imsic->lpriv, cpu); + + raw_spin_lock_init(&lpriv->ids_lock); + + /* Allocate used bitmap */ + lpriv->ids_used_bitmap =3D bitmap_zalloc(global->nr_ids + 1, + GFP_KERNEL); + if (!lpriv->ids_used_bitmap) { + imsic_local_cleanup(); + return -ENOMEM; + } + + /* Allocate enabled bitmap */ + lpriv->ids_enabled_bitmap =3D bitmap_zalloc(global->nr_ids + 1, + GFP_KERNEL); + if (!lpriv->ids_enabled_bitmap) { + imsic_local_cleanup(); + return -ENOMEM; + } + + /* Allocate move array */ + lpriv->ids_move =3D kcalloc(global->nr_ids + 1, + sizeof(*lpriv->ids_move), GFP_KERNEL); + if (!lpriv->ids_move) { + imsic_local_cleanup(); + return -ENOMEM; + } + + /* Reserve ID#0 because it is special and never implemented */ + bitmap_set(lpriv->ids_used_bitmap, 0, 1); + + /* Reserve IPI ID because it is special and used internally */ + bitmap_set(lpriv->ids_used_bitmap, IMSIC_IPI_ID, 1); + + /* Allocate vector array */ + lpriv->vectors =3D kcalloc(global->nr_ids + 1, + sizeof(*lpriv->vectors), GFP_KERNEL); + if (!lpriv->vectors) { + imsic_local_cleanup(); + return -ENOMEM; + } + + /* Setup vector array */ + for (i =3D 0; i <=3D global->nr_ids; i++) { + vec =3D &lpriv->vectors[i]; + vec->cpu =3D cpu; + vec->local_id =3D i; + vec->hwirq =3D UINT_MAX; + vec->order =3D UINT_MAX; + } + } + + return 0; +} + +int imsic_hwirqs_alloc(unsigned int order) +{ + int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->hwirqs_lock, flags); + ret =3D bitmap_find_free_region(imsic->hwirqs_used_bitmap, + imsic->nr_hwirqs, order); + raw_spin_unlock_irqrestore(&imsic->hwirqs_lock, flags); + + return ret; +} + +void imsic_hwirqs_free(unsigned int base_hwirq, unsigned int order) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->hwirqs_lock, flags); + bitmap_release_region(imsic->hwirqs_used_bitmap, base_hwirq, order); + raw_spin_unlock_irqrestore(&imsic->hwirqs_lock, flags); +} + +static int __init imsic_hwirqs_init(void) +{ + struct imsic_global_config *global =3D &imsic->global; + + imsic->nr_hwirqs =3D num_possible_cpus() * global->nr_ids; + + raw_spin_lock_init(&imsic->hwirqs_lock); + + imsic->hwirqs_used_bitmap =3D bitmap_zalloc(imsic->nr_hwirqs, + GFP_KERNEL); + if (!imsic->hwirqs_used_bitmap) + return -ENOMEM; + + return 0; +} + +static void __init imsic_hwirqs_cleanup(void) +{ + bitmap_free(imsic->hwirqs_used_bitmap); +} + +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, + u32 index, unsigned long *hartid) +{ + int rc; + struct of_phandle_args parent; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(fwnode)) + return -EINVAL; + + rc =3D of_irq_parse_one(to_of_node(fwnode), index, &parent); + if (rc) + return rc; + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (parent.args[0] !=3D RV_IRQ_EXT) + return -EINVAL; + + return riscv_of_parent_hartid(parent.np, hartid); +} + +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, + u32 index, struct resource *res) +{ + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(fwnode)) + return -EINVAL; + + return of_address_to_resource(to_of_node(fwnode), index, res); +} + +static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, + struct imsic_global_config *global, + u32 *nr_parent_irqs, + u32 *nr_mmios) +{ + unsigned long hartid; + struct resource res; + int rc; + u32 i; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(fwnode)) + return -EINVAL; + + *nr_parent_irqs =3D 0; + *nr_mmios =3D 0; + + /* Find number of parent interrupts */ + *nr_parent_irqs =3D 0; + while (!imsic_get_parent_hartid(fwnode, *nr_parent_irqs, &hartid)) + (*nr_parent_irqs)++; + if (!(*nr_parent_irqs)) { + pr_err("%pfwP: no parent irqs available\n", fwnode); + return -EINVAL; + } + + /* Find number of guest index bits in MSI address */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits =3D 0; + + /* Find number of HART index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits =3D __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } + + /* Find number of group index bits */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits =3D 0; + + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-shift", + &global->group_index_shift); + if (rc) + global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", + fwnode); + return rc; + } + + /* Find number of guest interrupt identities */ + rc =3D of_property_read_u32(to_of_node(fwnode), + "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids =3D global->nr_ids; + + /* Sanity check guest index bits */ + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; + if (i < global->guest_index_bits) { + pr_err("%pfwP: guest index bits too big\n", fwnode); + return -EINVAL; + } + + /* Sanity check HART index bits */ + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; + if (i < global->hart_index_bits) { + pr_err("%pfwP: HART index bits too big\n", fwnode); + return -EINVAL; + } + + /* Sanity check group index bits */ + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - + global->guest_index_bits - global->hart_index_bits; + if (i < global->group_index_bits) { + pr_err("%pfwP: group index bits too big\n", fwnode); + return -EINVAL; + } + + /* Sanity check group index shift */ + i =3D global->group_index_bits + global->group_index_shift - 1; + if (i >=3D BITS_PER_LONG) { + pr_err("%pfwP: group index shift too big\n", fwnode); + return -EINVAL; + } + + /* Sanity check number of interrupt identities */ + if ((global->nr_ids < IMSIC_MIN_ID) || + (global->nr_ids >=3D IMSIC_MAX_ID) || + ((global->nr_ids & IMSIC_MIN_ID) !=3D IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of interrupt identities\n", + fwnode); + return -EINVAL; + } + + /* Sanity check number of guest interrupt identities */ + if ((global->nr_guest_ids < IMSIC_MIN_ID) || + (global->nr_guest_ids >=3D IMSIC_MAX_ID) || + ((global->nr_guest_ids & IMSIC_MIN_ID) !=3D IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of guest interrupt identities\n", + fwnode); + return -EINVAL; + } + + /* Compute base address */ + rc =3D imsic_get_mmio_resource(fwnode, 0, &res); + if (rc) { + pr_err("%pfwP: first MMIO resource not found\n", fwnode); + return -EINVAL; + } + global->base_addr =3D res.start; + global->base_addr &=3D ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + global->base_addr &=3D ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + + /* Find number of MMIO register sets */ + while (!imsic_get_mmio_resource(fwnode, *nr_mmios, &res)) + (*nr_mmios)++; + + return 0; +} + +int __init imsic_setup_state(struct fwnode_handle *fwnode) +{ + int rc, cpu; + phys_addr_t base_addr; + void __iomem **mmios_va =3D NULL; + struct resource *mmios =3D NULL; + struct imsic_local_config *local; + struct imsic_global_config *global; + unsigned long reloff, hartid; + u32 i, j, index, nr_parent_irqs, nr_mmios, nr_handlers =3D 0; + + /* + * Only one IMSIC instance allowed in a platform for clean + * implementation of SMP IRQ affinity and per-CPU IPIs. + * + * This means on a multi-socket (or multi-die) platform we + * will have multiple MMIO regions for one IMSIC instance. + */ + if (imsic) { + pr_err("%pfwP: already initialized hence ignoring\n", + fwnode); + return -EALREADY; + } + + if (!riscv_isa_extension_available(NULL, SxAIA)) { + pr_err("%pfwP: AIA support not available\n", fwnode); + return -ENODEV; + } + + imsic =3D kzalloc(sizeof(*imsic), GFP_KERNEL); + if (!imsic) + return -ENOMEM; + imsic->fwnode =3D fwnode; + global =3D &imsic->global; + + global->local =3D alloc_percpu(typeof(*(global->local))); + if (!global->local) { + rc =3D -ENOMEM; + goto out_free_priv; + } + + /* Parse IMSIC fwnode */ + rc =3D imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios); + if (rc) + goto out_free_local; + + /* Allocate MMIO resource array */ + mmios =3D kcalloc(nr_mmios, sizeof(*mmios), GFP_KERNEL); + if (!mmios) { + rc =3D -ENOMEM; + goto out_free_local; + } + + /* Allocate MMIO virtual address array */ + mmios_va =3D kcalloc(nr_mmios, sizeof(*mmios_va), GFP_KERNEL); + if (!mmios_va) { + rc =3D -ENOMEM; + goto out_iounmap; + } + + /* Parse and map MMIO register sets */ + for (i =3D 0; i < nr_mmios; i++) { + rc =3D imsic_get_mmio_resource(fwnode, i, &mmios[i]); + if (rc) { + pr_err("%pfwP: unable to parse MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + + base_addr =3D mmios[i].start; + base_addr &=3D ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + base_addr &=3D ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + if (base_addr !=3D global->base_addr) { + rc =3D -EINVAL; + pr_err("%pfwP: address mismatch for regset %d\n", + fwnode, i); + goto out_iounmap; + } + + mmios_va[i] =3D ioremap(mmios[i].start, resource_size(&mmios[i])); + if (!mmios_va[i]) { + rc =3D -EIO; + pr_err("%pfwP: unable to map MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + } + + /* Initialize HW interrupt numbers */ + rc =3D imsic_hwirqs_init(); + if (rc) { + pr_err("%pfwP: failed to initialize HW interrupts numbers\n", + fwnode); + goto out_iounmap; + } + + /* Initialize local (or per-CPU )state */ + rc =3D imsic_local_init(); + if (rc) { + pr_err("%pfwP: failed to initialize local state\n", + fwnode); + goto out_hwirqs_cleanup; + } + + /* Configure handlers for target CPUs */ + for (i =3D 0; i < nr_parent_irqs; i++) { + rc =3D imsic_get_parent_hartid(fwnode, i, &hartid); + if (rc) { + pr_warn("%pfwP: hart ID for parent irq%d not found\n", + fwnode, i); + continue; + } + + cpu =3D riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", + fwnode, i); + continue; + } + + /* Find MMIO location of MSI page */ + index =3D nr_mmios; + reloff =3D i * BIT(global->guest_index_bits) * + IMSIC_MMIO_PAGE_SZ; + for (j =3D 0; nr_mmios; j++) { + if (reloff < resource_size(&mmios[j])) { + index =3D j; + break; + } + + /* + * MMIO region size may not be aligned to + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ + * if holes are present. + */ + reloff -=3D ALIGN(resource_size(&mmios[j]), + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); + } + if (index >=3D nr_mmios) { + pr_warn("%pfwP: MMIO not found for parent irq%d\n", + fwnode, i); + continue; + } + + local =3D per_cpu_ptr(global->local, cpu); + local->msi_pa =3D mmios[index].start + reloff; + local->msi_va =3D mmios_va[index] + reloff; + + nr_handlers++; + } + + /* If no CPU handlers found then can't take interrupts */ + if (!nr_handlers) { + pr_err("%pfwP: No CPU handlers found\n", fwnode); + rc =3D -ENODEV; + goto out_local_cleanup; + } + + /* We don't need MMIO arrays anymore so let's free-up */ + kfree(mmios_va); + kfree(mmios); + + return 0; + +out_local_cleanup: + imsic_local_cleanup(); +out_hwirqs_cleanup: + imsic_hwirqs_cleanup(); +out_iounmap: + for (i =3D 0; i < nr_mmios; i++) { + if (mmios_va[i]) + iounmap(mmios_va[i]); + } + kfree(mmios_va); + kfree(mmios); +out_free_local: + free_percpu(imsic->global.local); +out_free_priv: + kfree(imsic); + imsic =3D NULL; + return rc; +} diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h new file mode 100644 index 000000000000..82911b8b08b4 --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#ifndef _IRQ_RISCV_IMSIC_STATE_H +#define _IRQ_RISCV_IMSIC_STATE_H + +#include +#include +#include + +/* + * The IMSIC driver uses 1 IPI for ID synchronization and + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the + * total number of IPIs to 8. + */ +#define IMSIC_IPI_ID 1 +#define IMSIC_NR_IPI 8 + +struct imsic_vector { + /* Fixed details of the vector */ + unsigned int cpu; + unsigned int local_id; + /* Details saved by driver in the vector */ + unsigned int hwirq; + unsigned int order; +}; + +#define IMSIC_VECTOR_MASK(__v) \ + (BIT((__v)->order) - 1UL) +#define IMSIC_VECTOR_BASE_LOCAL_ID(__v) \ + ((__v)->local_id & ~IMSIC_VECTOR_MASK(__v)) +#define IMSIC_VECTOR_BASE_HWIRQ(__v) \ + ((__v)->hwirq & ~IMSIC_VECTOR_MASK(__v)) + +struct imsic_local_priv { + /* Local state of interrupt identities */ + raw_spinlock_t ids_lock; + unsigned long *ids_used_bitmap; + unsigned long *ids_enabled_bitmap; + struct imsic_vector **ids_move; + + /* Local vector table */ + struct imsic_vector *vectors; +}; + +struct imsic_priv { + /* Device details */ + struct fwnode_handle *fwnode; + + /* Global configuration common for all HARTs */ + struct imsic_global_config global; + + /* Dummy HW interrupt numbers */ + unsigned int nr_hwirqs; + raw_spinlock_t hwirqs_lock; + unsigned long *hwirqs_used_bitmap; + + /* Per-CPU state */ + struct imsic_local_priv __percpu *lpriv; + + /* IPI interrupt identity and synchronization */ + int ipi_virq; + struct irq_desc *ipi_lsync_desc; + + /* IRQ domains (created by platform driver) */ + struct irq_domain *base_domain; + struct irq_domain *plat_domain; +}; + +extern struct imsic_priv *imsic; + +void __imsic_eix_update(unsigned long base_id, + unsigned long num_id, bool pend, bool val); + +#define __imsic_id_set_enable(__id) \ + __imsic_eix_update((__id), 1, false, true) +#define __imsic_id_clear_enable(__id) \ + __imsic_eix_update((__id), 1, false, false) + +void imsic_local_sync(void); +void imsic_local_delivery(bool enable); + +void imsic_vector_mask(struct imsic_vector *vec); +void imsic_vector_unmask(struct imsic_vector *vec); +void imsic_vector_move(struct imsic_vector *old_vec, + struct imsic_vector *new_vec); + +struct imsic_vector *imsic_vector_from_local_id(unsigned int cpu, + unsigned int local_id); + +struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, + const struct cpumask *mask, + unsigned int order); +void imsic_vector_free(struct imsic_vector *vector); + +void imsic_vector_debug_show(struct seq_file *m, + struct imsic_vector *vec, int ind); + +void imsic_vector_debug_show_summary(struct seq_file *m, int ind); + +int imsic_hwirqs_alloc(unsigned int order); +void imsic_hwirqs_free(unsigned int base_hwirq, unsigned int order); + +int imsic_setup_state(struct fwnode_handle *fwnode); + +#endif diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h new file mode 100644 index 000000000000..cbb7bcd0e4dd --- /dev/null +++ b/include/linux/irqchip/riscv-imsic.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H +#define __LINUX_IRQCHIP_RISCV_IMSIC_H + +#include +#include +#include + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ BIT(IMSIC_MMIO_PAGE_SHIFT) +#define IMSIC_MMIO_PAGE_LE 0x00 +#define IMSIC_MMIO_PAGE_BE 0x04 + +#define IMSIC_MIN_ID 63 +#define IMSIC_MAX_ID 2048 + +#define IMSIC_EIDELIVERY 0x70 + +#define IMSIC_EITHRESHOLD 0x72 + +#define IMSIC_EIP0 0x80 +#define IMSIC_EIP63 0xbf +#define IMSIC_EIPx_BITS 32 + +#define IMSIC_EIE0 0xc0 +#define IMSIC_EIE63 0xff +#define IMSIC_EIEx_BITS 32 + +#define IMSIC_FIRST IMSIC_EIDELIVERY +#define IMSIC_LAST IMSIC_EIE63 + +#define IMSIC_MMIO_SETIPNUM_LE 0x00 +#define IMSIC_MMIO_SETIPNUM_BE 0x04 + +struct imsic_local_config { + phys_addr_t msi_pa; + void __iomem *msi_va; +}; + +struct imsic_global_config { + /* + * MSI Target Address Scheme + * + * XLEN-1 12 0 + * | | | + * ------------------------------------------------------------- + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + * ------------------------------------------------------------- + */ + + /* Bits representing Guest index, HART index, and Group index */ + u32 guest_index_bits; + u32 hart_index_bits; + u32 group_index_bits; + u32 group_index_shift; + + /* Global base address matching all target MSI addresses */ + phys_addr_t base_addr; + + /* Number of interrupt identities */ + u32 nr_ids; + + /* Number of guest interrupt identities */ + u32 nr_guest_ids; + + /* Per-CPU IMSIC addresses */ + struct imsic_local_config __percpu *local; +}; + +#ifdef CONFIG_RISCV_IMSIC + +extern const struct imsic_global_config *imsic_get_global_config(void); + +#else + +static inline const struct imsic_global_config *imsic_get_global_config(vo= id) +{ + return NULL; +} + +#endif + +#endif --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE80C25B46 for ; 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Mon, 23 Oct 2023 10:28:51 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:50 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Date: Mon, 23 Oct 2023 22:57:54 +0530 Message-Id: <20231023172800.315343-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux platform MSI support requires a platform MSI irqdomain so let us add a platform irqchip driver for RISC-V IMSIC which provides a base IRQ domain and platform MSI domain. This driver assumes that the IMSIC state is already initialized by the IMSIC early driver. Signed-off-by: Anup Patel --- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-riscv-imsic-platform.c | 309 +++++++++++++++++++++ 2 files changed, 310 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index d714724387ce..abca445a3229 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o -obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o +obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c new file mode 100644 index 000000000000..23d286cb017e --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-imsic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-imsic-state.h" + +static int imsic_cpu_page_phys(unsigned int cpu, + unsigned int guest_index, + phys_addr_t *out_msi_pa) +{ + struct imsic_global_config *global; + struct imsic_local_config *local; + + global =3D &imsic->global; + local =3D per_cpu_ptr(global->local, cpu); + + if (BIT(global->guest_index_bits) <=3D guest_index) + return -EINVAL; + + if (out_msi_pa) + *out_msi_pa =3D local->msi_pa + + (guest_index * IMSIC_MMIO_PAGE_SZ); + + return 0; +} + +static void imsic_irq_mask(struct irq_data *d) +{ + imsic_vector_mask(irq_data_get_irq_chip_data(d)); +} + +static void imsic_irq_unmask(struct irq_data *d) +{ + imsic_vector_unmask(irq_data_get_irq_chip_data(d)); +} + +static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, + struct msi_msg *msg) +{ + phys_addr_t msi_addr; + int err; + + if (WARN_ON(vec =3D=3D NULL)) + return; + + err =3D imsic_cpu_page_phys(vec->cpu, 0, &msi_addr); + if (WARN_ON(err)) + return; + + msg->address_hi =3D upper_32_bits(msi_addr); + msg->address_lo =3D lower_32_bits(msi_addr); + msg->data =3D IMSIC_VECTOR_BASE_LOCAL_ID(vec); +} + +static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *msg) +{ + imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg); +} + +#ifdef CONFIG_SMP +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *= vec) +{ + struct msi_msg msg[2] =3D { [1] =3D { }, }; + + imsic_irq_compose_vector_msg(vec, msg); + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg); +} + +static int imsic_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + struct imsic_vector *old_vec, *new_vec; + struct irq_data *pd =3D d->parent_data; + unsigned int i, virq, hwirq; + + old_vec =3D irq_data_get_irq_chip_data(pd); + if (WARN_ON(old_vec =3D=3D NULL)) + return -ENOENT; + + /* Find-out base virq, hwirq and order of the old vector */ + hwirq =3D IMSIC_VECTOR_BASE_HWIRQ(old_vec); + virq =3D pd->irq - (old_vec->hwirq - hwirq); + + /* Ensure old vector points to the first entry */ + if (old_vec->hwirq !=3D hwirq) { + pd =3D irq_domain_get_irq_data(imsic->base_domain, virq); + old_vec =3D irq_data_get_irq_chip_data(pd); + } + + /* Get a new vector on the desired set of CPUs */ + new_vec =3D imsic_vector_alloc(hwirq, mask_val, old_vec->order); + if (!new_vec) + return -ENOSPC; + + /* If old vector belongs to the desired CPU then do nothing */ + if (old_vec->cpu =3D=3D new_vec->cpu) { + imsic_vector_free(new_vec); + return IRQ_SET_MASK_OK_DONE; + } + + /* Point device to the new vector */ + imsic_msi_update_msg(d, new_vec); + + /* Update irq descriptors */ + for (i =3D 0; i < BIT(old_vec->order); i++) { + pd =3D irq_domain_get_irq_data(imsic->base_domain, virq + i); + + /* Save the new vector entry in irq descriptor*/ + pd->chip_data =3D new_vec + i; + + /* Update effective affinity of parent irq data */ + irq_data_update_effective_affinity(pd, + cpumask_of(new_vec->cpu)); + } + + /* Move state of the old vector to the new vector */ + imsic_vector_move(old_vec, new_vec); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip imsic_irq_base_chip =3D { + .name =3D "IMSIC-BASE", + .irq_mask =3D imsic_irq_mask, + .irq_unmask =3D imsic_irq_unmask, + .irq_compose_msi_msg =3D imsic_irq_compose_msg, + .flags =3D IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int imsic_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct imsic_vector *vec; + int i, hwirq; + + hwirq =3D imsic_hwirqs_alloc(get_count_order(nr_irqs)); + if (hwirq < 0) + return hwirq; + + vec =3D imsic_vector_alloc(hwirq, cpu_online_mask, + get_count_order(nr_irqs)); + if (!vec) { + imsic_hwirqs_free(hwirq, get_count_order(nr_irqs)); + return -ENOSPC; + } + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &imsic_irq_base_chip, vec + i, + handle_simple_irq, NULL, NULL); + irq_set_noprobe(virq + i); + irq_set_affinity(virq + i, cpu_online_mask); + /* + * IMSIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an IMSIC + * interrupt. This means IMSIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all IMSIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static void imsic_irq_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + + imsic_vector_free(irq_data_get_irq_chip_data(d)); + imsic_hwirqs_free(d->hwirq, get_count_order(nr_irqs)); + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS +static void imsic_irq_debug_show(struct seq_file *m, struct irq_domain *d, + struct irq_data *irqd, int ind) +{ + if (!irqd) { + imsic_vector_debug_show_summary(m, ind); + return; + } + + imsic_vector_debug_show(m, irq_data_get_irq_chip_data(irqd), ind); +} +#endif + +static const struct irq_domain_ops imsic_base_domain_ops =3D { + .alloc =3D imsic_irq_domain_alloc, + .free =3D imsic_irq_domain_free, +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS + .debug_show =3D imsic_irq_debug_show, +#endif +}; + +static struct irq_chip imsic_plat_irq_chip =3D { + .name =3D "IMSIC-PLAT", +#ifdef CONFIG_SMP + .irq_set_affinity =3D imsic_irq_set_affinity, +#endif +}; + +static struct msi_domain_ops imsic_plat_domain_ops =3D { +}; + +static struct msi_domain_info imsic_plat_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops =3D &imsic_plat_domain_ops, + .chip =3D &imsic_plat_irq_chip, +}; + +static int imsic_irq_domains_init(struct fwnode_handle *fwnode) +{ + /* Create Base IRQ domain */ + imsic->base_domain =3D irq_domain_create_tree(fwnode, + &imsic_base_domain_ops, imsic); + if (!imsic->base_domain) { + pr_err("%pfwP: failed to create IMSIC base domain\n", + fwnode); + return -ENOMEM; + } + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); + + /* Create Platform MSI domain */ + imsic->plat_domain =3D platform_msi_create_irq_domain(fwnode, + &imsic_plat_domain_info, + imsic->base_domain); + if (!imsic->plat_domain) { + pr_err("%pfwP: failed to create IMSIC platform domain\n", + fwnode); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } + + return 0; +} + +static int imsic_platform_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct imsic_global_config *global; + int rc; + + if (!imsic) { + dev_err(dev, "early driver not probed\n"); + return -ENODEV; + } + + if (imsic->base_domain) { + dev_err(dev, "irq domain already created\n"); + return -ENODEV; + } + + global =3D &imsic->global; + + /* Initialize IRQ and MSI domains */ + rc =3D imsic_irq_domains_init(dev->fwnode); + if (rc) { + dev_err(dev, "failed to initialize IRQ and MSI domains\n"); + return rc; + } + + dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", + global->hart_index_bits, global->guest_index_bits); + dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", + global->group_index_bits, global->group_index_shift); + dev_info(dev, " per-CPU IDs %d at base PPN %pa\n", + global->nr_ids, &global->base_addr); + dev_info(dev, " total %d interrupts available\n", + imsic->nr_hwirqs); + + return 0; +} + +static const struct of_device_id imsic_platform_match[] =3D { + { .compatible =3D "riscv,imsics" }, + {} +}; + +static struct platform_driver imsic_platform_driver =3D { + .driver =3D { + .name =3D "riscv-imsic", + .of_match_table =3D imsic_platform_match, + }, + .probe =3D imsic_platform_probe, +}; +builtin_platform_driver(imsic_platform_driver); --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1696C25B45 for ; Mon, 23 Oct 2023 17:29:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233732AbjJWR3v (ORCPT ); Mon, 23 Oct 2023 13:29:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232174AbjJWR3T (ORCPT ); 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Mon, 23 Oct 2023 10:28:55 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 09/14] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Mon, 23 Oct 2023 22:57:55 +0530 Message-Id: <20231023172800.315343-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++ drivers/irqchip/irq-riscv-imsic-platform.c | 51 ++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 3 files changed, 59 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bdd80716114d..c1d69b418dfb 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -552,6 +552,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ =20 +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 23d286cb017e..cdb659401199 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -215,6 +216,42 @@ static const struct irq_domain_ops imsic_base_domain_o= ps =3D { #endif }; =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip =3D { + .name =3D "IMSIC-PCI", + .irq_mask =3D imsic_pci_mask_irq, + .irq_unmask =3D imsic_pci_unmask_irq, +#ifdef CONFIG_SMP + .irq_set_affinity =3D imsic_irq_set_affinity, +#endif + .irq_eoi =3D irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops =3D { +}; + +static struct msi_domain_info imsic_pci_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops =3D &imsic_pci_domain_ops, + .chip =3D &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip =3D { .name =3D "IMSIC-PLAT", #ifdef CONFIG_SMP @@ -243,6 +280,18 @@ static int imsic_irq_domains_init(struct fwnode_handle= *fwnode) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain =3D pci_msi_create_irq_domain(fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + pr_err("%pfwP: failed to create IMSIC PCI domain\n", fwnode); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain =3D platform_msi_create_irq_domain(fwnode, &imsic_plat_domain_info, @@ -250,6 +299,8 @@ static int imsic_irq_domains_init(struct fwnode_handle = *fwnode) if (!imsic->plat_domain) { pr_err("%pfwP: failed to create IMSIC platform domain\n", fwnode); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 82911b8b08b4..8d209e77432e 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -67,6 +67,7 @@ struct imsic_priv { =20 /* IRQ domains (created by platform driver) */ struct irq_domain *base_domain; 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Mon, 23 Oct 2023 10:29:00 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v11 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Date: Mon, 23 Oct 2023 22:57:56 +0530 Message-Id: <20231023172800.315343-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../interrupt-controller/riscv,aplic.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml new file mode 100644 index 000000000000..190a6499c932 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root APLIC domain and a parent APLIC + domain can delegate interrupt sources to it's child APLIC domains. There + is one device tree node for each APLIC domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-i= ntc + node, which has a CPU node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incomi= ng + message signaled interrupt controller (IMSIC). If both "msi-parent" = and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, t= he + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain ch= ild + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegation: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of the parent APLIC domain (= inclusive) + - description: last interrupt number of the parent APLIC domain (i= nclusive) + description: + A interrupt delegation list where each entry is a triple consisting + of child APLIC domain phandle, first interrupt number of the parent + APLIC domain, and last interrupt number of the parent APLIC domain. + Firmware must configure interrupt delegation registers based on + interrupt delegation list. + +dependencies: + riscv,delegation: [ "riscv,children" ] + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +anyOf: + - required: + - interrupts-extended + - required: + - msi-parent + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic1>, <&aplic2>; + riscv,delegation =3D <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg =3D <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_mlevel>; + reg =3D <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic3>; + riscv,delegation =3D <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_slevel>; + reg =3D <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; +... --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABAD7C25B46 for ; Mon, 23 Oct 2023 17:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233394AbjJWRaE (ORCPT ); Mon, 23 Oct 2023 13:30:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233331AbjJWR30 (ORCPT ); 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Mon, 23 Oct 2023 10:29:06 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:29:05 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 11/14] irqchip: Add RISC-V advanced PLIC driver for direct-mode Date: Mon, 23 Oct 2023 22:57:57 +0530 Message-Id: <20231023172800.315343-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) specification defines advanced platform-level interrupt controller (APLIC) which has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) as a local external interrupt. We add a platform irqchip driver for the RISC-V APLIC direct-mode to support RISC-V platforms having only wired interrupts. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-aplic-direct.c | 343 +++++++++++++++++++++++ drivers/irqchip/irq-riscv-aplic-main.c | 232 +++++++++++++++ drivers/irqchip/irq-riscv-aplic-main.h | 45 +++ include/linux/irqchip/riscv-aplic.h | 119 ++++++++ 6 files changed, 745 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-aplic-direct.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.c create mode 100644 drivers/irqchip/irq-riscv-aplic-main.h create mode 100644 include/linux/irqchip/riscv-aplic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c1d69b418dfb..1996cc6f666a 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -546,6 +546,11 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 +config RISCV_APLIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + config RISCV_IMSIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index abca445a3229..7f8289790ed8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o +obj-$(CONFIG_RISCV_APLIC) +=3D irq-riscv-aplic-main.o irq-riscv-aplic-dir= ect.o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq= -riscv-aplic-direct.c new file mode 100644 index 000000000000..9ed2666bfb5e --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-aplic-main.h" + +#define APLIC_DISABLE_IDELIVERY 0 +#define APLIC_ENABLE_IDELIVERY 1 +#define APLIC_DISABLE_ITHRESHOLD 1 +#define APLIC_ENABLE_ITHRESHOLD 0 + +struct aplic_direct { + struct aplic_priv priv; + struct irq_domain *irqdomain; + struct cpumask lmask; +}; + +struct aplic_idc { + unsigned int hart_index; + void __iomem *regs; + struct aplic_direct *direct; +}; + +static unsigned int aplic_direct_parent_irq; +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); + +static void aplic_direct_irq_eoi(struct irq_data *d) +{ + /* + * The fasteoi_handler requires irq_eoi() callback hence + * provide a dummy handler. + */ +} + +#ifdef CONFIG_SMP +static int aplic_direct_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + struct aplic_direct *direct =3D + container_of(priv, struct aplic_direct, priv); + struct aplic_idc *idc; + unsigned int cpu, val; + struct cpumask amask; + void __iomem *target; + + cpumask_and(&amask, &direct->lmask, mask_val); + + if (force) + cpu =3D cpumask_first(&amask); + else + cpu =3D cpumask_any_and(&amask, cpu_online_mask); + + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + idc =3D per_cpu_ptr(&aplic_idcs, cpu); + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + val =3D idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<=3D APLIC_TARGET_HART_IDX_SHIFT; + val |=3D APLIC_DEFAULT_PRIORITY; + writel(val, target); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip aplic_direct_chip =3D { + .name =3D "APLIC-DIRECT", + .irq_mask =3D aplic_irq_mask, + .irq_unmask =3D aplic_irq_unmask, + .irq_set_type =3D aplic_irq_set_type, + .irq_eoi =3D aplic_direct_irq_eoi, +#ifdef CONFIG_SMP + .irq_set_affinity =3D aplic_direct_set_affinity, +#endif + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int aplic_direct_irqdomain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv =3D d->host_data; + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, + hwirq, type); +} + +static int aplic_direct_irqdomain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec =3D arg; + struct aplic_priv *priv =3D domain->host_data; + struct aplic_direct *direct =3D + container_of(priv, struct aplic_direct, priv); + + ret =3D aplic_irqdomain_translate(fwspec, priv->gsi_base, + &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_direct_chip, priv, + handle_fasteoi_irq, NULL, NULL); + irq_set_affinity(virq + i, &direct->lmask); + /* See the reason described in aplic_msi_irqdomain_alloc() */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_direct_irqdomain_ops =3D { + .translate =3D aplic_direct_irqdomain_translate, + .alloc =3D aplic_direct_irqdomain_alloc, + .free =3D irq_domain_free_irqs_top, +}; + +/* + * To handle an APLIC direct interrupts, we just read the CLAIMI register + * which will return highest priority pending interrupt and clear the + * pending bit of the interrupt. This process is repeated until CLAIMI + * register return zero value. + */ +static void aplic_direct_handle_irq(struct irq_desc *desc) +{ + struct aplic_idc *idc =3D this_cpu_ptr(&aplic_idcs); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct irq_domain *irqdomain =3D idc->direct->irqdomain; + irq_hw_number_t hw_irq; + int irq; + + chained_irq_enter(chip, desc); + + while ((hw_irq =3D readl(idc->regs + APLIC_IDC_CLAIMI))) { + hw_irq =3D hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; + irq =3D irq_find_mapping(irqdomain, hw_irq); + + if (unlikely(irq <=3D 0)) + dev_warn_ratelimited(idc->direct->priv.dev, + "hw_irq %lu mapping not found\n", + hw_irq); + else + generic_handle_irq(irq); + } + + chained_irq_exit(chip, desc); +} + +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) +{ + u32 de =3D (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; + u32 th =3D (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; + + /* Priority must be less than threshold for interrupt triggering */ + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); + + /* Delivery must be set to 1 for interrupt triggering */ + writel(de, idc->regs + APLIC_IDC_IDELIVERY); +} + +static int aplic_direct_dying_cpu(unsigned int cpu) +{ + if (aplic_direct_parent_irq) + disable_percpu_irq(aplic_direct_parent_irq); + + return 0; +} + +static int aplic_direct_starting_cpu(unsigned int cpu) +{ + if (aplic_direct_parent_irq) + enable_percpu_irq(aplic_direct_parent_irq, + irq_get_trigger_type(aplic_direct_parent_irq)); + + return 0; +} + +static int aplic_direct_parse_parent_hwirq(struct device *dev, + u32 index, u32 *parent_hwirq, + unsigned long *parent_hartid) +{ + struct of_phandle_args parent; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_irq_parse_one(to_of_node(dev->fwnode), index, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D parent.args[0]; + return 0; +} + +int aplic_direct_setup(struct device *dev, void __iomem *regs) +{ + int i, j, rc, cpu, setup_count =3D 0; + struct aplic_direct *direct; + struct aplic_priv *priv; + struct irq_domain *domain; + unsigned long hartid; + struct aplic_idc *idc; + u32 val, hwirq; + + direct =3D kzalloc(sizeof(*direct), GFP_KERNEL); + if (!direct) + return -ENOMEM; + priv =3D &direct->priv; + + rc =3D aplic_setup_priv(priv, dev, regs); + if (rc) { + dev_err(dev, "failed to create APLIC context\n"); + kfree(direct); + return rc; + } + + /* Setup per-CPU IDC and target CPU mask */ + for (i =3D 0; i < priv->nr_idcs; i++) { + rc =3D aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid); + if (rc) { + dev_warn(dev, "parent irq for IDC%d not found\n", i); + continue; + } + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (hwirq !=3D RV_IRQ_EXT) + continue; + + cpu =3D riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + dev_warn(dev, "invalid cpuid for IDC%d\n", i); + continue; + } + + cpumask_set_cpu(cpu, &direct->lmask); + + idc =3D per_cpu_ptr(&aplic_idcs, cpu); + idc->hart_index =3D i; + idc->regs =3D priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + idc->direct =3D direct; + + aplic_idc_set_delivery(idc, true); + + /* + * Boot cpu might not have APLIC hart_index =3D 0 so check + * and update target registers of all interrupts. + */ + if (cpu =3D=3D smp_processor_id() && idc->hart_index) { + val =3D idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<=3D APLIC_TARGET_HART_IDX_SHIFT; + val |=3D APLIC_DEFAULT_PRIORITY; + for (j =3D 1; j <=3D priv->nr_irqs; j++) + writel(val, priv->regs + APLIC_TARGET_BASE + + (j - 1) * sizeof(u32)); + } + + setup_count++; + } + + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!aplic_direct_parent_irq && domain) { + aplic_direct_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (aplic_direct_parent_irq) { + irq_set_chained_handler(aplic_direct_parent_irq, + aplic_direct_handle_irq); + + /* + * Setup CPUHP notifier to enable parent + * interrupt on all CPUs + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/aplic:starting", + aplic_direct_starting_cpu, + aplic_direct_dying_cpu); + } + } + + /* Fail if we were not able to setup IDC for any CPU */ + if (!setup_count) { + kfree(direct); + return -ENODEV; + } + + /* Setup global config and interrupt delivery */ + aplic_init_hw_global(priv, false); + + /* Create irq domain instance for the APLIC */ + direct->irqdomain =3D irq_domain_create_linear(dev->fwnode, + priv->nr_irqs + 1, + &aplic_direct_irqdomain_ops, + priv); + if (!direct->irqdomain) { + dev_err(dev, "failed to create direct irq domain\n"); + kfree(direct); + return -ENOMEM; + } + + /* Advertise the interrupt controller */ + dev_info(dev, "%d interrupts directly connected to %d CPUs\n", + priv->nr_irqs, priv->nr_idcs); + + return 0; +} diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-r= iscv-aplic-main.c new file mode 100644 index 000000000000..87450708a733 --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-aplic-main.h" + +void aplic_irq_unmask(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_SETIENUM); +} + +void aplic_irq_mask(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); +} + +int aplic_irq_set_type(struct irq_data *d, unsigned int type) +{ + u32 val =3D 0; + void __iomem *sourcecfg; + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + switch (type) { + case IRQ_TYPE_NONE: + val =3D APLIC_SOURCECFG_SM_INACTIVE; + break; + case IRQ_TYPE_LEVEL_LOW: + val =3D APLIC_SOURCECFG_SM_LEVEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + val =3D APLIC_SOURCECFG_SM_LEVEL_HIGH; + break; + case IRQ_TYPE_EDGE_FALLING: + val =3D APLIC_SOURCECFG_SM_EDGE_FALL; + break; + case IRQ_TYPE_EDGE_RISING: + val =3D APLIC_SOURCECFG_SM_EDGE_RISE; + break; + default: + return -EINVAL; + } + + sourcecfg =3D priv->regs + APLIC_SOURCECFG_BASE; + sourcecfg +=3D (d->hwirq - 1) * sizeof(u32); + writel(val, sourcecfg); + + return 0; +} + +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + unsigned long *hwirq, unsigned int *type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + if (WARN_ON(!fwspec->param[0])) + return -EINVAL; + + /* For DT, gsi_base is always zero. */ + *hwirq =3D fwspec->param[0] - gsi_base; + *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + WARN_ON(*type =3D=3D IRQ_TYPE_NONE); + + return 0; +} + +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) +{ + u32 val; +#ifdef CONFIG_RISCV_M_MODE + u32 valH; + + if (msi_mode) { + val =3D priv->msicfg.base_ppn; + valH =3D ((u64)priv->msicfg.base_ppn >> 32) & + APLIC_xMSICFGADDRH_BAPPN_MASK; + valH |=3D (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) + << APLIC_xMSICFGADDRH_LHXW_SHIFT; + valH |=3D (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) + << APLIC_xMSICFGADDRH_HHXW_SHIFT; + valH |=3D (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) + << APLIC_xMSICFGADDRH_LHXS_SHIFT; + valH |=3D (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) + << APLIC_xMSICFGADDRH_HHXS_SHIFT; + writel(val, priv->regs + APLIC_xMSICFGADDR); + writel(valH, priv->regs + APLIC_xMSICFGADDRH); + } +#endif + + /* Setup APLIC domaincfg register */ + val =3D readl(priv->regs + APLIC_DOMAINCFG); + val |=3D APLIC_DOMAINCFG_IE; + if (msi_mode) + val |=3D APLIC_DOMAINCFG_DM; + writel(val, priv->regs + APLIC_DOMAINCFG); + if (readl(priv->regs + APLIC_DOMAINCFG) !=3D val) + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", + val); +} + +static void aplic_init_hw_irqs(struct aplic_priv *priv) +{ + int i; + + /* Disable all interrupts */ + for (i =3D 0; i <=3D priv->nr_irqs; i +=3D 32) + writel(-1U, priv->regs + APLIC_CLRIE_BASE + + (i / 32) * sizeof(u32)); + + /* Set interrupt type and default priority for all interrupts */ + for (i =3D 1; i <=3D priv->nr_irqs; i++) { + writel(0, priv->regs + APLIC_SOURCECFG_BASE + + (i - 1) * sizeof(u32)); + writel(APLIC_DEFAULT_PRIORITY, + priv->regs + APLIC_TARGET_BASE + + (i - 1) * sizeof(u32)); + } + + /* Clear APLIC domaincfg */ + writel(0, priv->regs + APLIC_DOMAINCFG); +} + +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, + void __iomem *regs) +{ + struct of_phandle_args parent; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + /* Save device pointer and register base */ + priv->dev =3D dev; + priv->regs =3D regs; + + /* Find out number of interrupt sources */ + rc =3D of_property_read_u32(to_of_node(dev->fwnode), + "riscv,num-sources", + &priv->nr_irqs); + if (rc) { + dev_err(dev, "failed to get number of interrupt sources\n"); + return rc; + } + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { + while (!of_irq_parse_one(to_of_node(dev->fwnode), + priv->nr_idcs, &parent)) + priv->nr_idcs++; + } + + /* Setup initial state APLIC interrupts */ + aplic_init_hw_irqs(priv); + + return 0; +} + +static int aplic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + bool msi_mode =3D false; + struct resource *res; + void __iomem *regs; + int rc; + + /* Map the MMIO registers */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "failed to get MMIO resource\n"); + return -EINVAL; + } + regs =3D devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!regs) { + dev_err(dev, "failed map MMIO registers\n"); + return -ENOMEM; + } + + /* + * If msi-parent property is present then setup APLIC MSI + * mode otherwise setup APLIC direct mode. + */ + if (is_of_node(dev->fwnode)) + msi_mode =3D of_property_present(to_of_node(dev->fwnode), + "msi-parent"); + if (msi_mode) + rc =3D -ENODEV; + else + rc =3D aplic_direct_setup(dev, regs); + if (rc) { + dev_err(dev, "failed setup APLIC in %s mode\n", + msi_mode ? "MSI" : "direct"); + return rc; + } + + return 0; +} + +static const struct of_device_id aplic_match[] =3D { + { .compatible =3D "riscv,aplic" }, + {} +}; + +static struct platform_driver aplic_driver =3D { + .driver =3D { + .name =3D "riscv-aplic", + .of_match_table =3D aplic_match, + }, + .probe =3D aplic_probe, +}; +builtin_platform_driver(aplic_driver); diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-r= iscv-aplic-main.h new file mode 100644 index 000000000000..474a04229334 --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#ifndef _IRQ_RISCV_APLIC_MAIN_H +#define _IRQ_RISCV_APLIC_MAIN_H + +#include +#include +#include +#include +#include + +#define APLIC_DEFAULT_PRIORITY 1 + +struct aplic_msicfg { + phys_addr_t base_ppn; + u32 hhxs; + u32 hhxw; + u32 lhxs; + u32 lhxw; +}; + +struct aplic_priv { + struct device *dev; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + void __iomem *regs; + struct aplic_msicfg msicfg; +}; + +void aplic_irq_unmask(struct irq_data *d); +void aplic_irq_mask(struct irq_data *d); +int aplic_irq_set_type(struct irq_data *d, unsigned int type); +int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + unsigned long *hwirq, unsigned int *type); +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); +int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, + void __iomem *regs); +int aplic_direct_setup(struct device *dev, void __iomem *regs); + +#endif diff --git a/include/linux/irqchip/riscv-aplic.h b/include/linux/irqchip/ri= scv-aplic.h new file mode 100644 index 000000000000..97e198ea0109 --- /dev/null +++ b/include/linux/irqchip/riscv-aplic.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H +#define __LINUX_IRQCHIP_RISCV_APLIC_H + +#include + +#define APLIC_MAX_IDC BIT(14) +#define APLIC_MAX_SOURCE 1024 + +#define APLIC_DOMAINCFG 0x0000 +#define APLIC_DOMAINCFG_RDONLY 0x80000000 +#define APLIC_DOMAINCFG_IE BIT(8) +#define APLIC_DOMAINCFG_DM BIT(2) +#define APLIC_DOMAINCFG_BE BIT(0) + +#define APLIC_SOURCECFG_BASE 0x0004 +#define APLIC_SOURCECFG_D BIT(10) +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff +#define APLIC_SOURCECFG_SM_MASK 0x00000007 +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 +#define APLIC_SOURCECFG_SM_DETACH 0x1 +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 + +#define APLIC_MMSICFGADDR 0x1bc0 +#define APLIC_MMSICFGADDRH 0x1bc4 +#define APLIC_SMSICFGADDR 0x1bc8 +#define APLIC_SMSICFGADDRH 0x1bcc + +#ifdef CONFIG_RISCV_M_MODE +#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH +#else +#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH +#endif + +#define APLIC_xMSICFGADDRH_L BIT(31) +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff + +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 + +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ + (BIT(__lhxs) - 1) + +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ + (BIT(__lhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ + ((__lhxs)) +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) + +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ + (BIT(__hhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) + +#define APLIC_IRQBITS_PER_REG 32 + +#define APLIC_SETIP_BASE 0x1c00 +#define APLIC_SETIPNUM 0x1cdc + +#define APLIC_CLRIP_BASE 0x1d00 +#define APLIC_CLRIPNUM 0x1ddc + +#define APLIC_SETIE_BASE 0x1e00 +#define APLIC_SETIENUM 0x1edc + +#define APLIC_CLRIE_BASE 0x1f00 +#define APLIC_CLRIENUM 0x1fdc + +#define APLIC_SETIPNUM_LE 0x2000 +#define APLIC_SETIPNUM_BE 0x2004 + +#define APLIC_GENMSI 0x3000 + +#define APLIC_TARGET_BASE 0x3004 +#define APLIC_TARGET_HART_IDX_SHIFT 18 +#define APLIC_TARGET_HART_IDX_MASK 0x3fff +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f +#define APLIC_TARGET_IPRIO_MASK 0xff +#define APLIC_TARGET_EIID_MASK 0x7ff + +#define APLIC_IDC_BASE 0x4000 +#define APLIC_IDC_SIZE 32 + +#define APLIC_IDC_IDELIVERY 0x00 + +#define APLIC_IDC_IFORCE 0x04 + +#define APLIC_IDC_ITHRESHOLD 0x08 + +#define APLIC_IDC_TOPI 0x18 +#define APLIC_IDC_TOPI_ID_SHIFT 16 +#define APLIC_IDC_TOPI_ID_MASK 0x3ff +#define APLIC_IDC_TOPI_PRIO_MASK 0xff + +#define APLIC_IDC_CLAIMI 0x1c + +#endif --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97688C25B46 for ; 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Mon, 23 Oct 2023 10:29:11 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:29:10 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 12/14] irqchip/riscv-aplic: Add support for MSI-mode Date: Mon, 23 Oct 2023 22:57:58 +0530 Message-Id: <20231023172800.315343-13-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced platform-level interrupt controller (APLIC) has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC MSI-mode, wired interrupts are forwared as message signaled interrupts (MSIs) to CPUs via IMSIC. We extend the existing APLIC irqchip driver to support MSI-mode for RISC-V platforms having both wired interrupts and MSIs. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-aplic-main.c | 2 +- drivers/irqchip/irq-riscv-aplic-main.h | 8 + drivers/irqchip/irq-riscv-aplic-msi.c | 285 +++++++++++++++++++++++++ 5 files changed, 301 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-riscv-aplic-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 1996cc6f666a..7adc4dbe07ff 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -551,6 +551,12 @@ config RISCV_APLIC depends on RISCV select IRQ_DOMAIN_HIERARCHY =20 +config RISCV_APLIC_MSI + bool + depends on RISCV_APLIC + select GENERIC_MSI_IRQ + default RISCV_APLIC + config RISCV_IMSIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 7f8289790ed8..47995fdb2c60 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -96,6 +96,7 @@ obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o obj-$(CONFIG_RISCV_APLIC) +=3D irq-riscv-aplic-main.o irq-riscv-aplic-dir= ect.o +obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi.o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-r= iscv-aplic-main.c index 87450708a733..d1b342b66551 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.c +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -205,7 +205,7 @@ static int aplic_probe(struct platform_device *pdev) msi_mode =3D of_property_present(to_of_node(dev->fwnode), "msi-parent"); if (msi_mode) - rc =3D -ENODEV; + rc =3D aplic_msi_setup(dev, regs); else rc =3D aplic_direct_setup(dev, regs); if (rc) { diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-r= iscv-aplic-main.h index 474a04229334..78267ec58098 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.h +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -41,5 +41,13 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool = msi_mode); int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs); int aplic_direct_setup(struct device *dev, void __iomem *regs); +#ifdef CONFIG_RISCV_APLIC_MSI +int aplic_msi_setup(struct device *dev, void __iomem *regs); +#else +static inline int aplic_msi_setup(struct device *dev, void __iomem *regs) +{ + return -ENODEV; +} +#endif =20 #endif diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-ri= scv-aplic-msi.c new file mode 100644 index 000000000000..086d00e0429e --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-aplic-main.h" + +static void aplic_msi_irq_unmask(struct irq_data *d) +{ + aplic_irq_unmask(d); + irq_chip_unmask_parent(d); +} + +static void aplic_msi_irq_mask(struct irq_data *d) +{ + aplic_irq_mask(d); + irq_chip_mask_parent(d); +} + +static void aplic_msi_irq_eoi(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + u32 reg_off, reg_mask; + + /* + * EOI handling only required only for level-triggered + * interrupts in APLIC MSI mode. + */ + + reg_off =3D APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4); + reg_mask =3D BIT(d->hwirq % APLIC_IRQBITS_PER_REG); + switch (irqd_get_trigger_type(d)) { + case IRQ_TYPE_LEVEL_LOW: + if (!(readl(priv->regs + reg_off) & reg_mask)) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + case IRQ_TYPE_LEVEL_HIGH: + if (readl(priv->regs + reg_off) & reg_mask) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + } +} + +static struct irq_chip aplic_msi_chip =3D { + .name =3D "APLIC-MSI", + .irq_mask =3D aplic_msi_irq_mask, + .irq_unmask =3D aplic_msi_irq_unmask, + .irq_set_type =3D aplic_irq_set_type, + .irq_eoi =3D aplic_msi_irq_eoi, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int aplic_msi_irqdomain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv =3D platform_msi_get_host_data(d); + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, hwirq, type); +} + +static int aplic_msi_irqdomain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec =3D arg; + struct aplic_priv *priv =3D platform_msi_get_host_data(domain); + + ret =3D aplic_irqdomain_translate(fwspec, priv->gsi_base, &hwirq, &type); + if (ret) + return ret; + + ret =3D platform_msi_device_domain_alloc(domain, virq, nr_irqs); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_msi_chip, priv, handle_fasteoi_irq, + NULL, NULL); + /* + * APLIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an APLIC + * interrupt. This means APLIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all APLIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_msi_irqdomain_ops =3D { + .translate =3D aplic_msi_irqdomain_translate, + .alloc =3D aplic_msi_irqdomain_alloc, + .free =3D platform_msi_device_domain_free, +}; + +static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + unsigned int group_index, hart_index, guest_index, val; + struct irq_data *d =3D irq_get_irq_data(desc->irq); + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + struct aplic_msicfg *mc =3D &priv->msicfg; + phys_addr_t tppn, tbppn, msg_addr; + void __iomem *target; + + /* For zeroed MSI, simply write zero into the target register */ + if (!msg->address_hi && !msg->address_lo && !msg->data) { + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + writel(0, target); + return; + } + + /* Sanity check on message data */ + WARN_ON(msg->data > APLIC_TARGET_EIID_MASK); + + /* Compute target MSI address */ + msg_addr =3D (((u64)msg->address_hi) << 32) | msg->address_lo; + tppn =3D msg_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + + /* Compute target HART Base PPN */ + tbppn =3D tppn; + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + WARN_ON(tbppn !=3D mc->base_ppn); + + /* Compute target group and hart indexes */ + group_index =3D (tppn >> APLIC_xMSICFGADDR_PPN_HHX_SHIFT(mc->hhxs)) & + APLIC_xMSICFGADDR_PPN_HHX_MASK(mc->hhxw); + hart_index =3D (tppn >> APLIC_xMSICFGADDR_PPN_LHX_SHIFT(mc->lhxs)) & + APLIC_xMSICFGADDR_PPN_LHX_MASK(mc->lhxw); + hart_index |=3D (group_index << mc->lhxw); + WARN_ON(hart_index > APLIC_TARGET_HART_IDX_MASK); + + /* Compute target guest index */ + guest_index =3D tppn & APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + WARN_ON(guest_index > APLIC_TARGET_GUEST_IDX_MASK); + + /* Update IRQ TARGET register */ + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + val =3D (hart_index & APLIC_TARGET_HART_IDX_MASK) + << APLIC_TARGET_HART_IDX_SHIFT; + val |=3D (guest_index & APLIC_TARGET_GUEST_IDX_MASK) + << APLIC_TARGET_GUEST_IDX_SHIFT; + val |=3D (msg->data & APLIC_TARGET_EIID_MASK); + writel(val, target); +} + +int aplic_msi_setup(struct device *dev, void __iomem *regs) +{ + const struct imsic_global_config *imsic_global; + struct irq_domain *irqdomain; + struct aplic_priv *priv; + struct aplic_msicfg *mc; + phys_addr_t pa; + int rc; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + rc =3D aplic_setup_priv(priv, dev, regs); + if (!priv) { + dev_err(dev, "failed to create APLIC context\n"); + return rc; + } + mc =3D &priv->msicfg; + + /* + * The APLIC outgoing MSI config registers assume target MSI + * controller to be RISC-V AIA IMSIC controller. + */ + imsic_global =3D imsic_get_global_config(); + if (!imsic_global) { + dev_err(dev, "IMSIC global config not found\n"); + return -ENODEV; + } + + /* Find number of guest index bits (LHXS) */ + mc->lhxs =3D imsic_global->guest_index_bits; + if (APLIC_xMSICFGADDRH_LHXS_MASK < mc->lhxs) { + dev_err(dev, "IMSIC guest index bits big for APLIC LHXS\n"); + return -EINVAL; + } + + /* Find number of HART index bits (LHXW) */ + mc->lhxw =3D imsic_global->hart_index_bits; + if (APLIC_xMSICFGADDRH_LHXW_MASK < mc->lhxw) { + dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); + return -EINVAL; + } + + /* Find number of group index bits (HHXW) */ + mc->hhxw =3D imsic_global->group_index_bits; + if (APLIC_xMSICFGADDRH_HHXW_MASK < mc->hhxw) { + dev_err(dev, "IMSIC group index bits big for APLIC HHXW\n"); + return -EINVAL; + } + + /* Find first bit position of group index (HHXS) */ + mc->hhxs =3D imsic_global->group_index_shift; + if (mc->hhxs < (2 * APLIC_xMSICFGADDR_PPN_SHIFT)) { + dev_err(dev, "IMSIC group index shift should be >=3D %d\n", + (2 * APLIC_xMSICFGADDR_PPN_SHIFT)); + return -EINVAL; + } + mc->hhxs -=3D (2 * APLIC_xMSICFGADDR_PPN_SHIFT); + if (APLIC_xMSICFGADDRH_HHXS_MASK < mc->hhxs) { + dev_err(dev, "IMSIC group index shift big for APLIC HHXS\n"); + return -EINVAL; + } + + /* Compute PPN base */ + mc->base_ppn =3D imsic_global->base_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + + /* Setup global config and interrupt delivery */ + aplic_init_hw_global(priv, true); + + /* Set the APLIC device MSI domain if not available */ + if (!dev_get_msi_domain(dev)) { + /* + * The device MSI domain for OF devices is only set at the + * time of populating/creating OF device. If the device MSI + * domain is discovered later after the OF device is created + * then we need to set it explicitly before using any platform + * MSI functions. + * + * In case of APLIC device, the parent MSI domain is always + * IMSIC and the IMSIC MSI domains are created later through + * the platform driver probing so we set it explicitly here. + */ + if (is_of_node(dev->fwnode)) + of_msi_configure(dev, to_of_node(dev->fwnode)); + } + + /* Create irq domain instance for the APLIC MSI-mode */ + irqdomain =3D platform_msi_create_device_domain( + dev, priv->nr_irqs + 1, + aplic_msi_write_msg, + &aplic_msi_irqdomain_ops, + priv); + if (!irqdomain) { + dev_err(dev, "failed to create MSI irq domain\n"); + return -ENOMEM; + } + + /* Advertise the interrupt controller */ + pa =3D priv->msicfg.base_ppn << APLIC_xMSICFGADDR_PPN_SHIFT; + dev_info(dev, "%d interrupts forwared to MSI base %pa\n", + priv->nr_irqs, &pa); + + return 0; +} --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 291C6C25B45 for ; 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Mon, 23 Oct 2023 10:29:16 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:29:15 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v11 13/14] RISC-V: Select APLIC and IMSIC drivers Date: Mon, 23 Oct 2023 22:57:59 +0530 Message-Id: <20231023172800.315343-14-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The QEMU virt machine supports AIA emulation and we also have quite a few RISC-V platforms with AIA support under development so let us select APLIC and IMSIC drivers for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..45c660f1219d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -153,6 +153,8 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL + select RISCV_APLIC + select RISCV_IMSIC select RISCV_INTC select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC --=20 2.34.1 From nobody Thu Jan 1 10:40:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A23EC25B46 for ; Mon, 23 Oct 2023 17:30:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230027AbjJWRaa (ORCPT ); Mon, 23 Oct 2023 13:30:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233815AbjJWR3w (ORCPT ); Mon, 23 Oct 2023 13:29:52 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5EB61739 for ; Mon, 23 Oct 2023 10:29:21 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5ae99bb5ccdso1816132a12.1 for ; Mon, 23 Oct 2023 10:29:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082161; x=1698686961; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Z+lM1psdaIr4vqzMn22M1QYDstohuJWu+yz55IiCnA=; b=FWz9cTzTFoLUyU1GHdasai+atLj/rWbT3oQ+M3vgLxZi/eM8bABmnW1QhAPo7yczEl qa7RleVFtWl4SSuPF800ubDAKJS11TDLKHEz5L94FZf6KTnM3YWBp1EDgC8RM/s4zgMo B1gXNzva7fSzXgxwpzg4zSGIp104FPe2PIum4+KcNHxIfhIWbzAcf1J/XTkub2kwPByE g2xFq70etWLIZWC9ncgPO3T/I98A0h0aPLRqd3T5YWuVikcbniDAWJwvAZV6QpJC7t7G 7oXpDk2JvjCDnYALPyNJ0CUx52N4hOFSzJIglMS0oUJBiuXnTWGKH6zEPOZsA8qKmYYP F4uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082161; x=1698686961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Z+lM1psdaIr4vqzMn22M1QYDstohuJWu+yz55IiCnA=; b=b56gvPAsIfliU3KxbgHDtoMS4dBEmSdfH4q+Qcc3D8xL7Fabdc9pEZFgTtUTn70OUF EDhsT5esZsnyugCb2xt3Ohf+DaeuvUgSoaloud/Ng9QRnncvxIa4pCPHeF8XBFV/1rT9 ZAR0G8Cx8U32vpo7dbW3vYplYZB6MkZMP2VqURrFr/KjSMidj/kDxeCRYdzKkjsfekW8 K92yq0QljCwvuXCpHIG0jXAcNRDfq7ow+MrMV2NLWo/jVbzN8wpUG6C7+JvPsZ663kED lwb1f9VUmfz7kOM5Xov0dntDiSJzWbsEukhzJ6uC0ZJYtD1H87o8dsoFIxKlZHFZvY3y LgHw== X-Gm-Message-State: AOJu0YyscRLDxwtfAK5Dw83zsItFgsX7vyOvEmLwEGPYzxsAppPe3wXu NuxlK5CK0FcDwTStto4SM0I3pQ== X-Google-Smtp-Source: AGHT+IHo6USP3pcRlXKuqJ79woJTXEsC0Rq2g43o4Sr9KzMGrxRYLsluIqp45MjwhV/47Ir+x9eEvA== X-Received: by 2002:a05:6a20:daa3:b0:157:609f:6057 with SMTP id iy35-20020a056a20daa300b00157609f6057mr319511pzb.27.1698082161065; Mon, 23 Oct 2023 10:29:21 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:29:20 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 14/14] MAINTAINERS: Add entry for RISC-V AIA drivers Date: Mon, 23 Oct 2023 22:58:00 +0530 Message-Id: <20231023172800.315343-15-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add myself as maintainer for RISC-V AIA drivers including the RISC-V INTC driver which supports both AIA and non-AIA platforms. Signed-off-by: Anup Patel --- MAINTAINERS | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 801a2f44182c..4557675c6086 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18410,6 +18410,20 @@ S: Maintained F: drivers/mtd/nand/raw/r852.c F: drivers/mtd/nand/raw/r852.h =20 +RISC-V AIA DRIVERS +M: Anup Patel +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +F: drivers/irqchip/irq-riscv-aplic-*.c +F: drivers/irqchip/irq-riscv-aplic-*.h +F: drivers/irqchip/irq-riscv-imsic-*.c +F: drivers/irqchip/irq-riscv-imsic-*.h +F: drivers/irqchip/irq-riscv-intc.c +F: include/linux/irqchip/riscv-aplic.h +F: include/linux/irqchip/riscv-imsic.h + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt --=20 2.34.1