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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id 1-20020a05600c228100b0040596352951sm13593275wmf.5.2023.10.23.03.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 03:22:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/7] irqchip/renesas-rzg2l: add macros to retrieve TITSR index and associated selector Date: Mon, 23 Oct 2023 13:22:19 +0300 Message-Id: <20231023102223.1309614-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231023102223.1309614-1-claudiu.beznea.uj@bp.renesas.com> References: <20231023102223.1309614-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add macros to retrieve TITSR register index and associated selector. Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index fe8d516f3614..9ce0d6d67486 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -45,6 +44,8 @@ #define TITSR_TITSEL_EDGE_FALLING 1 #define TITSR_TITSEL_LEVEL_HIGH 2 #define TITSR_TITSEL_LEVEL_LOW 3 +#define TITSR_HWIRQ_TO_INDEX(hwirq) ((hwirq) >> TITSR0_MAX_INT) +#define TITSR_HWIRQ_TO_SEL(hwirq) ((hwirq) & 0xF) /* 0xF =3D TITSR0_MAX_I= NT - 1*/ =20 #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) #define IITSR_IITSEL_LEVEL_LOW 0 @@ -185,12 +186,10 @@ static int rzg2l_irq_set_type(struct irq_data *d, uns= igned int type) =20 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { + unsigned int hwirq =3D irqd_to_hwirq(d) - IRQC_TINT_START; struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); - unsigned int hwirq =3D irqd_to_hwirq(d); - u32 titseln =3D hwirq - IRQC_TINT_START; - u32 offset; + u32 index, sel, reg; u8 sense; - u32 reg; =20 switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -205,17 +204,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - offset =3D TITSR0; - if (titseln >=3D TITSR0_MAX_INT) { - titseln -=3D TITSR0_MAX_INT; - offset =3D TITSR1; - } + index =3D TITSR_HWIRQ_TO_INDEX(hwirq); + sel =3D TITSR_HWIRQ_TO_SEL(hwirq); =20 raw_spin_lock(&priv->lock); - reg =3D readl_relaxed(priv->base + offset); - reg &=3D ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); - reg |=3D sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + reg =3D readl_relaxed(priv->base + TITSR(index)); + reg &=3D ~(IRQ_MASK << (sel * TITSEL_WIDTH)); + reg |=3D sense << (sel * TITSEL_WIDTH); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); =20 return 0; --=20 2.39.2