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charset="utf-8" Add MACsec statistics callbacks. The statistic registers must be set to 0 if the SC/SA is deleted to read relevant values next time when the SC/SA is used. Signed-off-by: Radu Pirea (NXP OSS) --- Changes in v5-v8: - none Changes in v4: - Added nxp_c45_macsec_read32_64 function to read 32b counters into u64 variables. - Added nxp_c45_macsec_read64 function to read 64b counters. Changes in v3: - reworked the implementation around struct nxp_c45_sa - changed the way how OutOctetsEncrypted are propagated to the userspace - changed the way how OutOctetsProtected are propagated to the userspace - read and clear OutOctetsProtected Changes in v2: - split the patch from "net: phy: nxp-c45-tja11xx: add MACsec support" drivers/net/phy/nxp-c45-tja11xx-macsec.c | 345 +++++++++++++++++++++++ 1 file changed, 345 insertions(+) diff --git a/drivers/net/phy/nxp-c45-tja11xx-macsec.c b/drivers/net/phy/nxp= -c45-tja11xx-macsec.c index 821f8926f7f2..4dd10ea6e06c 100644 --- a/drivers/net/phy/nxp-c45-tja11xx-macsec.c +++ b/drivers/net/phy/nxp-c45-tja11xx-macsec.c @@ -137,6 +137,35 @@ #define ADAPTER_EN BIT(6) #define MACSEC_EN BIT(5) =20 +#define MACSEC_INOV1HS 0x0140 +#define MACSEC_INOV2HS 0x0144 +#define MACSEC_INOD1HS 0x0148 +#define MACSEC_INOD2HS 0x014C +#define MACSEC_RXSCIPUS 0x0150 +#define MACSEC_RXSCIPDS 0x0154 +#define MACSEC_RXSCIPLS 0x0158 +#define MACSEC_RXAN0INUSS 0x0160 +#define MACSEC_RXAN0IPUSS 0x0170 +#define MACSEC_RXSA_A_IPOS 0x0194 +#define MACSEC_RXSA_A_IPIS 0x01B0 +#define MACSEC_RXSA_A_IPNVS 0x01B4 +#define MACSEC_RXSA_B_IPOS 0x01D4 +#define MACSEC_RXSA_B_IPIS 0x01F0 +#define MACSEC_RXSA_B_IPNVS 0x01F4 +#define MACSEC_OPUS 0x021C +#define MACSEC_OPTLS 0x022C +#define MACSEC_OOP1HS 0x0240 +#define MACSEC_OOP2HS 0x0244 +#define MACSEC_OOE1HS 0x0248 +#define MACSEC_OOE2HS 0x024C +#define MACSEC_TXSA_A_OPPS 0x028C +#define MACSEC_TXSA_A_OPES 0x0290 +#define MACSEC_TXSA_B_OPPS 0x02CC +#define MACSEC_TXSA_B_OPES 0x02D0 +#define MACSEC_INPWTS 0x0630 +#define MACSEC_INPBTS 0x0638 +#define MACSEC_IPSNFS 0x063C + enum nxp_c45_sa_type { TX_SA, RX_SA, @@ -175,6 +204,11 @@ struct nxp_c45_sa_regs { u16 ka; u16 ssci; u16 salt; + u16 ipis; + u16 ipnvs; + u16 ipos; + u16 opps; + u16 opes; }; =20 static const struct nxp_c45_sa_regs rx_sa_a_regs =3D { @@ -186,6 +220,9 @@ static const struct nxp_c45_sa_regs rx_sa_a_regs =3D { .ka =3D MACSEC_RXSA_A_KA, .ssci =3D MACSEC_RXSA_A_SSCI, .salt =3D MACSEC_RXSA_A_SALT, + .ipis =3D MACSEC_RXSA_A_IPIS, + .ipnvs =3D MACSEC_RXSA_A_IPNVS, + .ipos =3D MACSEC_RXSA_A_IPOS, }; =20 static const struct nxp_c45_sa_regs rx_sa_b_regs =3D { @@ -197,6 +234,9 @@ static const struct nxp_c45_sa_regs rx_sa_b_regs =3D { .ka =3D MACSEC_RXSA_B_KA, .ssci =3D MACSEC_RXSA_B_SSCI, .salt =3D MACSEC_RXSA_B_SALT, + .ipis =3D MACSEC_RXSA_B_IPIS, + .ipnvs =3D MACSEC_RXSA_B_IPNVS, + .ipos =3D MACSEC_RXSA_B_IPOS, }; =20 static const struct nxp_c45_sa_regs tx_sa_a_regs =3D { @@ -206,6 +246,8 @@ static const struct nxp_c45_sa_regs tx_sa_a_regs =3D { .ka =3D MACSEC_TXSA_A_KA, .ssci =3D MACSEC_TXSA_A_SSCI, .salt =3D MACSEC_TXSA_A_SALT, + .opps =3D MACSEC_TXSA_A_OPPS, + .opes =3D MACSEC_TXSA_A_OPES, }; =20 static const struct nxp_c45_sa_regs tx_sa_b_regs =3D { @@ -215,6 +257,8 @@ static const struct nxp_c45_sa_regs tx_sa_b_regs =3D { .ka =3D MACSEC_TXSA_B_KA, .ssci =3D MACSEC_TXSA_B_SSCI, .salt =3D MACSEC_TXSA_B_SALT, + .opps =3D MACSEC_TXSA_B_OPPS, + .opes =3D MACSEC_TXSA_B_OPES, }; =20 static const @@ -284,6 +328,26 @@ static int nxp_c45_macsec_read(struct phy_device *phyd= ev, u16 addr, u32 *value) return 0; } =20 +static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr, + u64 *value) +{ + u32 lvalue; + + nxp_c45_macsec_read(phydev, addr, &lvalue); + *value =3D lvalue; +} + +static void nxp_c45_macsec_read64(struct phy_device *phydev, u16 addr, + u64 *value) +{ + u32 lvalue; + + nxp_c45_macsec_read(phydev, addr, &lvalue); + *value =3D (u64)lvalue << 32; + nxp_c45_macsec_read(phydev, addr + 4, &lvalue); + *value |=3D lvalue; +} + static void nxp_c45_secy_irq_en(struct phy_device *phydev, struct nxp_c45_secy *phy_secy, bool en) { @@ -432,6 +496,41 @@ static void nxp_c45_sa_set_key(struct macsec_context *= ctx, nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A); } =20 +static void nxp_c45_rx_sa_clear_stats(struct phy_device *phydev, + struct nxp_c45_sa *sa) +{ + nxp_c45_macsec_write(phydev, sa->regs->ipis, 0); + nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0); + nxp_c45_macsec_write(phydev, sa->regs->ipos, 0); + + nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0); + nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0); +} + +static void nxp_c45_rx_sa_read_stats(struct phy_device *phydev, + struct nxp_c45_sa *sa, + struct macsec_rx_sa_stats *stats) +{ + nxp_c45_macsec_read(phydev, sa->regs->ipis, &stats->InPktsInvalid); + nxp_c45_macsec_read(phydev, sa->regs->ipnvs, &stats->InPktsNotValid); + nxp_c45_macsec_read(phydev, sa->regs->ipos, &stats->InPktsOK); +} + +static void nxp_c45_tx_sa_clear_stats(struct phy_device *phydev, + struct nxp_c45_sa *sa) +{ + nxp_c45_macsec_write(phydev, sa->regs->opps, 0); + nxp_c45_macsec_write(phydev, sa->regs->opes, 0); +} + +static void nxp_c45_tx_sa_read_stats(struct phy_device *phydev, + struct nxp_c45_sa *sa, + struct macsec_tx_sa_stats *stats) +{ + nxp_c45_macsec_read(phydev, sa->regs->opps, &stats->OutPktsProtected); + nxp_c45_macsec_read(phydev, sa->regs->opes, &stats->OutPktsEncrypted); +} + static void nxp_c45_rx_sa_update(struct phy_device *phydev, struct nxp_c45_sa *sa, bool en) { @@ -646,6 +745,23 @@ static void nxp_c45_tx_sc_update(struct phy_device *ph= ydev, nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg); } =20 +static void nxp_c45_tx_sc_clear_stats(struct phy_device *phydev, + struct nxp_c45_secy *phy_secy) +{ + struct nxp_c45_sa *pos, *tmp; + + list_for_each_entry_safe(pos, tmp, &phy_secy->sa_list, list) + if (pos->type =3D=3D TX_SA) + nxp_c45_tx_sa_clear_stats(phydev, pos); + + nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0); + nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0); + nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0); + nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0); + nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0); + nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0); +} + static void nxp_c45_set_rx_sc0_impl(struct phy_device *phydev, bool enable) { @@ -735,6 +851,32 @@ static void nxp_c45_rx_sc_update(struct phy_device *ph= ydev, nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg); } =20 +static void nxp_c45_rx_sc_clear_stats(struct phy_device *phydev, + struct nxp_c45_secy *phy_secy) +{ + struct nxp_c45_sa *pos, *tmp; + int i; + + list_for_each_entry_safe(pos, tmp, &phy_secy->sa_list, list) + if (pos->type =3D=3D RX_SA) + nxp_c45_rx_sa_clear_stats(phydev, pos); + + nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0); + nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0); + + nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0); + nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0); + + nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0); + nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0); + nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0); + + for (i =3D 0; i < MACSEC_NUM_AN; i++) { + nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0); + nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0); + } +} + static void nxp_c45_rx_sc_del(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { @@ -744,11 +886,20 @@ static void nxp_c45_rx_sc_del(struct phy_device *phyd= ev, nxp_c45_macsec_write(phydev, MACSEC_RPW, 0); nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, 0); =20 + nxp_c45_rx_sc_clear_stats(phydev, phy_secy); + list_for_each_entry_safe(pos, tmp, &phy_secy->sa_list, list) if (pos->type =3D=3D RX_SA) nxp_c45_rx_sa_update(phydev, pos, false); } =20 +static void nxp_c45_clear_global_stats(struct phy_device *phydev) +{ + nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0); + nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0); + nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0); +} + static void nxp_c45_macsec_en(struct phy_device *phydev, bool en) { u32 reg; @@ -939,6 +1090,7 @@ static int nxp_c45_mdo_del_secy(struct macsec_context = *ctx) nxp_c45_mdo_dev_stop(ctx); nxp_c45_tx_sa_next(phy_secy, &next_sa, encoding_sa); nxp_c45_tx_sa_update(phydev, &next_sa, false); + nxp_c45_tx_sc_clear_stats(phydev, phy_secy); if (phy_secy->rx_sc) nxp_c45_rx_sc_del(phydev, phy_secy); =20 @@ -949,6 +1101,9 @@ static int nxp_c45_mdo_del_secy(struct macsec_context = *ctx) clear_bit(phy_secy->secy_id, priv->macsec->tx_sc_bitmap); nxp_c45_secy_free(phy_secy); =20 + if (list_empty(&priv->macsec->secy_list)) + nxp_c45_clear_global_stats(phydev); + return 0; } =20 @@ -1106,6 +1261,7 @@ static int nxp_c45_mdo_del_rxsa(struct macsec_context= *ctx) =20 nxp_c45_select_secy(phydev, phy_secy->secy_id); nxp_c45_rx_sa_update(phydev, sa, false); + nxp_c45_rx_sa_clear_stats(phydev, sa); =20 nxp_c45_sa_free(sa); =20 @@ -1195,12 +1351,196 @@ static int nxp_c45_mdo_del_txsa(struct macsec_cont= ext *ctx) nxp_c45_select_secy(phydev, phy_secy->secy_id); if (ctx->secy->tx_sc.encoding_sa =3D=3D sa->an) nxp_c45_tx_sa_update(phydev, sa, false); + nxp_c45_tx_sa_clear_stats(phydev, sa); =20 nxp_c45_sa_free(sa); =20 return 0; } =20 +static int nxp_c45_mdo_get_dev_stats(struct macsec_context *ctx) +{ + struct phy_device *phydev =3D ctx->phydev; + struct nxp_c45_phy *priv =3D phydev->priv; + struct macsec_dev_stats *dev_stats; + struct nxp_c45_secy *phy_secy; + + phy_secy =3D nxp_c45_find_secy(&priv->macsec->secy_list, ctx->secy->sci); + if (IS_ERR(phy_secy)) + return PTR_ERR(phy_secy); + + dev_stats =3D ctx->stats.dev_stats; + nxp_c45_select_secy(phydev, phy_secy->secy_id); + + nxp_c45_macsec_read32_64(phydev, MACSEC_OPUS, + &dev_stats->OutPktsUntagged); + nxp_c45_macsec_read32_64(phydev, MACSEC_OPTLS, + &dev_stats->OutPktsTooLong); + nxp_c45_macsec_read32_64(phydev, MACSEC_INPBTS, + &dev_stats->InPktsBadTag); + + if (phy_secy->secy->validate_frames =3D=3D MACSEC_VALIDATE_STRICT) + nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS, + &dev_stats->InPktsNoTag); + else + nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS, + &dev_stats->InPktsUntagged); + + if (phy_secy->secy->validate_frames =3D=3D MACSEC_VALIDATE_STRICT) + nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS, + &dev_stats->InPktsNoSCI); + else + nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS, + &dev_stats->InPktsUnknownSCI); + + /* Always 0. */ + dev_stats->InPktsOverrun =3D 0; + + return 0; +} + +static int nxp_c45_mdo_get_tx_sc_stats(struct macsec_context *ctx) +{ + struct phy_device *phydev =3D ctx->phydev; + struct nxp_c45_phy *priv =3D phydev->priv; + struct macsec_tx_sa_stats tx_sa_stats; + struct macsec_tx_sc_stats *stats; + struct nxp_c45_secy *phy_secy; + struct nxp_c45_sa *pos, *tmp; + + phy_secy =3D nxp_c45_find_secy(&priv->macsec->secy_list, ctx->secy->sci); + if (IS_ERR(phy_secy)) + return PTR_ERR(phy_secy); + + stats =3D ctx->stats.tx_sc_stats; + nxp_c45_select_secy(phydev, phy_secy->secy_id); + + nxp_c45_macsec_read64(phydev, MACSEC_OOE1HS, + &stats->OutOctetsEncrypted); + nxp_c45_macsec_read64(phydev, MACSEC_OOP1HS, + &stats->OutOctetsProtected); + list_for_each_entry_safe(pos, tmp, &phy_secy->sa_list, list) { + if (pos->type !=3D TX_SA) + continue; + + memset(&tx_sa_stats, 0, sizeof(tx_sa_stats)); + nxp_c45_tx_sa_read_stats(phydev, pos, &tx_sa_stats); + + stats->OutPktsEncrypted +=3D tx_sa_stats.OutPktsEncrypted; + stats->OutPktsProtected +=3D tx_sa_stats.OutPktsProtected; + } + + return 0; +} + +static int nxp_c45_mdo_get_tx_sa_stats(struct macsec_context *ctx) +{ + struct phy_device *phydev =3D ctx->phydev; + struct nxp_c45_phy *priv =3D phydev->priv; + struct macsec_tx_sa_stats *stats; + struct nxp_c45_secy *phy_secy; + u8 an =3D ctx->sa.assoc_num; + struct nxp_c45_sa *sa; + + phy_secy =3D nxp_c45_find_secy(&priv->macsec->secy_list, ctx->secy->sci); + if (IS_ERR(phy_secy)) + return PTR_ERR(phy_secy); + + sa =3D nxp_c45_find_sa(&phy_secy->sa_list, TX_SA, an); + if (IS_ERR(sa)) + return PTR_ERR(sa); + + stats =3D ctx->stats.tx_sa_stats; + nxp_c45_select_secy(phydev, phy_secy->secy_id); + nxp_c45_tx_sa_read_stats(phydev, sa, stats); + + return 0; +} + +static int nxp_c45_mdo_get_rx_sc_stats(struct macsec_context *ctx) +{ + struct phy_device *phydev =3D ctx->phydev; + struct nxp_c45_phy *priv =3D phydev->priv; + struct macsec_rx_sa_stats rx_sa_stats; + struct macsec_rx_sc_stats *stats; + struct nxp_c45_secy *phy_secy; + struct nxp_c45_sa *pos, *tmp; + u32 reg =3D 0; + int i; + + phy_secy =3D nxp_c45_find_secy(&priv->macsec->secy_list, ctx->secy->sci); + if (IS_ERR(phy_secy)) + return PTR_ERR(phy_secy); + + if (phy_secy->rx_sc !=3D ctx->rx_sc) + return -EINVAL; + + stats =3D ctx->stats.rx_sc_stats; + nxp_c45_select_secy(phydev, phy_secy->secy_id); + + list_for_each_entry_safe(pos, tmp, &phy_secy->sa_list, list) { + if (pos->type !=3D RX_SA) + continue; + + memset(&rx_sa_stats, 0, sizeof(rx_sa_stats)); + nxp_c45_rx_sa_read_stats(phydev, pos, &rx_sa_stats); + + stats->InPktsInvalid +=3D rx_sa_stats.InPktsInvalid; + stats->InPktsNotValid +=3D rx_sa_stats.InPktsNotValid; + stats->InPktsOK +=3D rx_sa_stats.InPktsOK; + } + + for (i =3D 0; i < MACSEC_NUM_AN; i++) { + nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + i * 4, ®); + stats->InPktsNotUsingSA +=3D reg; + nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + i * 4, ®); + stats->InPktsUnusedSA +=3D reg; + } + + nxp_c45_macsec_read64(phydev, MACSEC_INOD1HS, + &stats->InOctetsDecrypted); + nxp_c45_macsec_read64(phydev, MACSEC_INOV1HS, + &stats->InOctetsValidated); + + nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPDS, + &stats->InPktsDelayed); + nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPLS, + &stats->InPktsLate); + nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPUS, + &stats->InPktsUnchecked); + + return 0; +} + +static int nxp_c45_mdo_get_rx_sa_stats(struct macsec_context *ctx) +{ + struct phy_device *phydev =3D ctx->phydev; + struct nxp_c45_phy *priv =3D phydev->priv; + struct macsec_rx_sa_stats *stats; + struct nxp_c45_secy *phy_secy; + u8 an =3D ctx->sa.assoc_num; + struct nxp_c45_sa *sa; + + phy_secy =3D nxp_c45_find_secy(&priv->macsec->secy_list, ctx->secy->sci); + if (IS_ERR(phy_secy)) + return PTR_ERR(phy_secy); + + sa =3D nxp_c45_find_sa(&phy_secy->sa_list, RX_SA, an); + if (IS_ERR(sa)) + return PTR_ERR(sa); + + stats =3D ctx->stats.rx_sa_stats; + nxp_c45_select_secy(phydev, phy_secy->secy_id); + + nxp_c45_rx_sa_read_stats(phydev, sa, stats); + nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + an * 4, + &stats->InPktsNotUsingSA); + nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + an * 4, + &stats->InPktsUnusedSA); + + return 0; +} + static const struct macsec_ops nxp_c45_macsec_ops =3D { .mdo_dev_open =3D nxp_c45_mdo_dev_open, .mdo_dev_stop =3D nxp_c45_mdo_dev_stop, @@ -1216,6 +1556,11 @@ static const struct macsec_ops nxp_c45_macsec_ops = =3D { .mdo_add_txsa =3D nxp_c45_mdo_add_txsa, .mdo_upd_txsa =3D nxp_c45_mdo_upd_txsa, .mdo_del_txsa =3D nxp_c45_mdo_del_txsa, + .mdo_get_dev_stats =3D nxp_c45_mdo_get_dev_stats, + .mdo_get_tx_sc_stats =3D nxp_c45_mdo_get_tx_sc_stats, + .mdo_get_tx_sa_stats =3D nxp_c45_mdo_get_tx_sa_stats, + .mdo_get_rx_sc_stats =3D nxp_c45_mdo_get_rx_sc_stats, + .mdo_get_rx_sa_stats =3D nxp_c45_mdo_get_rx_sa_stats, }; =20 int nxp_c45_macsec_config_init(struct phy_device *phydev) --=20 2.34.1