From nobody Fri Sep 20 07:26:40 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E90F5C07545 for ; Mon, 23 Oct 2023 03:07:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229475AbjJWDHO (ORCPT ); Sun, 22 Oct 2023 23:07:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjJWDG7 (ORCPT ); Sun, 22 Oct 2023 23:06:59 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7589ED41; Sun, 22 Oct 2023 20:06:52 -0700 (PDT) X-UUID: 3346eb74715111eea33bb35ae8d461a2-20231023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=9YVIRwmFT8KYFj002+Q2SJxtVfpVydhliFb7K5MsQ7g=; b=hhbaAD2XJKypAxOiqyWZys8xaAfeCfI6aP2PdKr0R49UO3rY6LetZrK0/7r89Z+sQfpNdp5drfpZUvvJKskQIqOqFbmO5MB9kSlNqXlrozpDMvnz6PKkhAh36E6efYpdcwtvBA6Vy3H5ir9FwkLWoBJXEmWaMeJmALXVx4tvlL0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:fb96c431-51e0-4244-b699-d79254134414,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:5a95067d-ccd9-4df5-91ce-9df5fea3ae01,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 3346eb74715111eea33bb35ae8d461a2-20231023 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1702391185; Mon, 23 Oct 2023 11:06:46 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 11:06:44 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 11:06:43 +0800 From: Yunfei Dong To: Sebastian Fricke , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH v2,2/7] media: mediatek: vcodec: Set the supported h264 level for each platform Date: Mon, 23 Oct 2023 11:06:35 +0800 Message-ID: <20231023030640.16393-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231023030640.16393-1-yunfei.dong@mediatek.com> References: <20231023030640.16393-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Set the maximum H264 codec level for each platform. The various mediatek platforms support different levels for decoding, the level of the codec limits among others the maximum resolution, bit rate and frame rate for the decoder. Signed-off-by: Yunfei Dong Reviewed-by: Sebastian Fricke Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index e29c9c58f3da..7aaf0db13a76 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -56,6 +56,15 @@ static const struct mtk_stateless_control mtk_stateless_= controls[] =3D { }, .codec_type =3D V4L2_PIX_FMT_H264_SLICE, }, + { + .cfg =3D { + .id =3D V4L2_CID_MPEG_VIDEO_H264_LEVEL, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .def =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + }, + .codec_type =3D V4L2_PIX_FMT_H264_SLICE, + }, { .cfg =3D { .id =3D V4L2_CID_STATELESS_H264_DECODE_MODE, @@ -519,6 +528,40 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_= ops =3D { .s_ctrl =3D mtk_vdec_s_ctrl, }; =20 +static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8192: + case MTK_VDEC_MT8188: + cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; + break; + case MTK_VDEC_MT8195: + cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; + break; + case MTK_VDEC_MT8183: + case MTK_VDEC_MT8186: + cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; + break; + default: + cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1; + break; + }; +} + +static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (cfg->id) { + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: + mtk_vcodec_dec_fill_h264_level(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, c= fg->def); + break; + default: + break; + }; +} + static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) { unsigned int i; @@ -532,6 +575,8 @@ static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec= _dec_ctx *ctx) for (i =3D 0; i < NUM_CTRLS; i++) { struct v4l2_ctrl_config cfg =3D mtk_stateless_controls[i].cfg; cfg.ops =3D &mtk_vcodec_dec_ctrl_ops; + + mtk_vcodec_dec_reset_controls(&cfg, ctx); v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL); if (ctx->ctrl_hdl.error) { mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i, --=20 2.18.0