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Fri, 10 Jan 2025 05:31:27 -0800 (PST) From: Alexandre Mergnat Date: Fri, 10 Jan 2025 14:31:15 +0100 Subject: [PATCH v7 5/6] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v7-5-6703f3e26831@baylibre.com> References: <20231023-display-support-v7-0-6703f3e26831@baylibre.com> In-Reply-To: <20231023-display-support-v7-0-6703f3e26831@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++= ++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 9c91fe8ea0f9..fdd570ca2d20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -19,6 +20,19 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + aal0 =3D &aal0; + ccorr0 =3D &ccorr0; + color0 =3D &color0; + dither0 =3D &dither0; + dpi0 =3D &dpi0; + dsi0 =3D &dsi0; + gamma0 =3D &gamma0; + ovl0 =3D &ovl0; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -608,6 +622,15 @@ spi: spi@1100a000 { status =3D "disabled"; }; =20 + disp_pwm: pwm@1100e000 { + compatible =3D "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + clock-names =3D "main", "mm"; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PW= M>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + }; + i2c3: i2c@1100f000 { compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg =3D <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -704,6 +727,15 @@ ethernet: ethernet@112a0000 { status =3D "disabled"; }; =20 + mipi_tx0: dsi-phy@11c00000 { + compatible =3D "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c00000 0 0x800>; + clock-output-names =3D "mipi_tx0_pll"; + clocks =3D <&clk26m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + }; + u3phy: t-phy@11cc0000 { compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells =3D <1>; @@ -731,6 +763,26 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8365-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8365-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; }; =20 smi_common: smi@14002000 { @@ -756,6 +808,290 @@ larb0: larb@14003000 { mediatek,larb-id =3D <0>; }; =20 + ovl0: ovl@1400b000 { + compatible =3D "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ovl0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ovl0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible =3D "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible =3D "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccor= r"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ccorr0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ccorr0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible =3D "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x14011000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + aal0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + aal0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible =3D "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamm= a"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + gamma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + gamma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible =3D "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x14013000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dither0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dither0_out: endpoint@0 { + reg =3D <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg =3D <0 0x14014000 0 0x1000>; + clock-names =3D "engine", "digital", "hs"; + clocks =3D <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts =3D ; + phy-names =3D "dphy"; + phys =3D <&mipi_tx0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14016000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size =3D <2048>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma1_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma1_out: endpoint@1 { + reg =3D <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible =3D "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg =3D <0 0x14018000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + status =3D "disabled"; + }; + camsys: syscon@15000000 { compatible =3D "mediatek,mt8365-imgsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.25.1