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Thu, 09 Jan 2025 02:38:04 -0800 (PST) From: Alexandre Mergnat Date: Thu, 09 Jan 2025 11:37:59 +0100 Subject: [PATCH v6 6/6] arm64: dts: mediatek: add display support for mt8365-evk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v6-6-c6af4f34f4d8@baylibre.com> References: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> In-Reply-To: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 236 ++++++++++++++++++++++++= ++++ 1 file changed, 236 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts index 7d90112a7e27..70bd49a9d02f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -27,6 +27,21 @@ chosen { stdout-path =3D "serial0:921600n8"; }; =20 + connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "d"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + hdmi_connector_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible =3D "linaro,optee-tz"; @@ -104,6 +119,16 @@ sound: sound { pinctrl-5 =3D <&aud_mosi_on_pins>; mediatek,platform =3D <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "vsys_lcm"; + }; + }; =20 &afe { @@ -131,6 +156,88 @@ &cpu3 { sram-supply =3D <&mt6357_vsram_proc_reg>; }; =20 +&dither0_out { + remote-endpoint =3D <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 =3D <&dpi_default_pins>; + pinctrl-1 =3D <&dpi_idle_pins>; + pinctrl-names =3D "default", "sleep"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dpi0_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dpi0_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "startek,kd070fhfid015"; + reg =3D <0>; + enable-gpios =3D <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply =3D <&mt6357_vsim1_reg>; + power-supply =3D <&vsys_lcm_reg>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dsi0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dsi0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 =3D <ðernet_pins>; pinctrl-names =3D "default"; @@ -161,6 +268,56 @@ &i2c0 { status =3D "okay"; }; =20 +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-div =3D <2>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + it66121_hdmi: hdmi@4c { + compatible =3D "ite,it66121"; + reg =3D <0x4c>; + #sound-dai-cells =3D <0>; + interrupt-parent =3D <&pio>; + interrupts =3D <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&ite_pins>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply =3D <&mt6357_vsim2_reg>; + vcn33-supply =3D <&mt6357_vibr_reg>; + vrf12-supply =3D <&mt6357_vrf12_reg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + it66121_in: endpoint@0 { + reg =3D <0>; + bus-width =3D <12>; + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hdmi_connector_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -205,6 +362,11 @@ &mt6357_pmic { mediatek,micbias1-microvolt =3D <1700000>; }; =20 +&mt6357_vsim1_reg { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -267,6 +429,49 @@ clk-dat-pins { }; }; =20 + dpi_default_pins: dpi-default-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength =3D <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux =3D ; @@ -308,6 +513,33 @@ pins { }; }; =20 + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux =3D , + ; + output-high; + }; + + rst_ite_pins { + pinmux =3D ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux =3D ; @@ -463,6 +695,10 @@ &pwm { status =3D "okay"; }; =20 +&rdma1_out { + remote-endpoint =3D <&dpi0_in>; +}; + &ssusb { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; --=20 2.25.1