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Thu, 09 Jan 2025 02:37:58 -0800 (PST) From: amergnat@baylibre.com Date: Thu, 09 Jan 2025 11:37:54 +0100 Subject: [PATCH v6 1/6] dt-bindings: display: mediatek: dpi: add power-domains example Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v6-1-c6af4f34f4d8@baylibre.com> References: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> In-Reply-To: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat , Fabien Parent X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 From: Fabien Parent DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding example. Fixes: 9273cf7d3942 ("dt-bindings: display: mediatek: convert the dpi bindi= ngs to yaml") Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Reviewed-by: CK Hu Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index 0f1e556dc8ef..d5ee52ea479b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -116,11 +116,13 @@ examples: - | #include #include + #include =20 dpi: dpi@1401d000 { compatible =3D "mediatek,mt8173-dpi"; reg =3D <0x1401d000 0x1000>; interrupts =3D ; + power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; 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Thu, 09 Jan 2025 02:37:59 -0800 (PST) From: Alexandre Mergnat Date: Thu, 09 Jan 2025 11:37:55 +0100 Subject: [PATCH v6 2/6] drm/mediatek: dsi: Improves the DSI lane setup robustness Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v6-2-c6af4f34f4d8@baylibre.com> References: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> In-Reply-To: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered before mtk_dsi_poweron. lanes_ready flag toggle to true during mtk_dsi_lane_ready function, and the DSI module is set up during mtk_dsi_poweron. Later, during panel driver init, mtk_dsi_lane_ready is triggered but does nothing because lanes are considered ready. Unfortunately, when the panel driver try to communicate, the DSI returns a timeout. The solution found here is to put lanes_ready flag to false after the DSI module setup into mtk_dsi_poweron to init the DSI lanes after the power / setup of the DSI module. Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index e61b9bc68e9a..dcf0d93881b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -724,6 +724,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); =20 + dsi->lanes_ready =3D false; + return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk); --=20 2.25.1 From nobody Sun Feb 8 04:12:25 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01723215F71 for ; Thu, 9 Jan 2025 10:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 From: Fabien Parent Add DRM support for MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 0829ceb9967c..5471ef744cc1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -328,6 +328,10 @@ static const struct mtk_mmsys_driver_data mt8195_vdosy= s1_driver_data =3D { .min_height =3D 1, }; =20 +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =3D { + .mmsys_dev_num =3D 1, +}; + static const struct of_device_id mtk_drm_of_ids[] =3D { { .compatible =3D "mediatek,mt2701-mmsys", .data =3D &mt2701_mmsys_driver_data}, @@ -355,6 +359,8 @@ static const struct of_device_id mtk_drm_of_ids[] =3D { .data =3D &mt8195_vdosys0_driver_data}, { .compatible =3D "mediatek,mt8195-vdosys1", .data =3D &mt8195_vdosys1_driver_data}, + { .compatible =3D "mediatek,mt8365-mmsys", + .data =3D &mt8365_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); @@ -751,6 +757,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8195-disp-mutex", .data =3D (void *)MTK_DISP_MUTEX }, + { .compatible =3D "mediatek,mt8365-disp-mutex", + .data =3D (void *)MTK_DISP_MUTEX }, { .compatible =3D "mediatek,mt8173-disp-od", .data =3D (void *)MTK_DISP_OD }, { .compatible =3D "mediatek,mt2701-disp-ovl", --=20 2.25.1 From nobody Sun Feb 8 04:12:25 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3DAF216605 for ; Thu, 9 Jan 2025 10:38:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736419086; cv=none; b=F2ULbC7R/zvKPku5emItAh4SN32RRk/tqDwmYQoUMq6OOM3MjWDFAAouVrwu3VXJU+4ELv9dk0/LEkIlhEzcWSW+eS7UlZ365YxvDdHZQFMizNytx0FHe8ys85rg0hwY2pEGmMVwXkHeLDY1l6z1cKaY5vcjHXlNPw881M/r3TU= ARC-Message-Signature: i=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Enable the DRM HDMI connector support. Enable the MIPI-DSI display Startek KD070FHFID015 panel. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c62831e61586..1e2963a13500 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -897,9 +897,11 @@ CONFIG_DRM_PANEL_NOVATEK_NT36672E=3Dm CONFIG_DRM_PANEL_RAYDIUM_RM67191=3Dm CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=3Dm CONFIG_DRM_PANEL_SITRONIX_ST7703=3Dm +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=3Dm CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=3Dm CONFIG_DRM_PANEL_VISIONOX_VTDR6130=3Dm CONFIG_DRM_FSL_LDB=3Dm +CONFIG_DRM_DISPLAY_CONNECTOR=3Dm CONFIG_DRM_LONTIUM_LT8912B=3Dm CONFIG_DRM_LONTIUM_LT9611=3Dm CONFIG_DRM_LONTIUM_LT9611UXC=3Dm --=20 2.25.1 From nobody Sun Feb 8 04:12:25 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A036201017 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++= ++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 9c91fe8ea0f9..fdd570ca2d20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -19,6 +20,19 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + aal0 =3D &aal0; + ccorr0 =3D &ccorr0; + color0 =3D &color0; + dither0 =3D &dither0; + dpi0 =3D &dpi0; + dsi0 =3D &dsi0; + gamma0 =3D &gamma0; + ovl0 =3D &ovl0; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -608,6 +622,15 @@ spi: spi@1100a000 { status =3D "disabled"; }; =20 + disp_pwm: pwm@1100e000 { + compatible =3D "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + clock-names =3D "main", "mm"; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PW= M>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + }; + i2c3: i2c@1100f000 { compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg =3D <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -704,6 +727,15 @@ ethernet: ethernet@112a0000 { status =3D "disabled"; }; =20 + mipi_tx0: dsi-phy@11c00000 { + compatible =3D "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c00000 0 0x800>; + clock-output-names =3D "mipi_tx0_pll"; + clocks =3D <&clk26m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + }; + u3phy: t-phy@11cc0000 { compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells =3D <1>; @@ -731,6 +763,26 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8365-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8365-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; }; =20 smi_common: smi@14002000 { @@ -756,6 +808,290 @@ larb0: larb@14003000 { mediatek,larb-id =3D <0>; }; =20 + ovl0: ovl@1400b000 { + compatible =3D "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ovl0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ovl0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible =3D "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible =3D "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccor= r"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ccorr0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ccorr0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible =3D "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x14011000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + aal0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + aal0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible =3D "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamm= a"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + gamma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + gamma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible =3D "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x14013000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dither0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dither0_out: endpoint@0 { + reg =3D <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg =3D <0 0x14014000 0 0x1000>; + clock-names =3D "engine", "digital", "hs"; + clocks =3D <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts =3D ; + phy-names =3D "dphy"; + phys =3D <&mipi_tx0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14016000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size =3D <2048>; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 236 ++++++++++++++++++++++++= ++++ 1 file changed, 236 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts index 7d90112a7e27..70bd49a9d02f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -27,6 +27,21 @@ chosen { stdout-path =3D "serial0:921600n8"; }; =20 + connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "d"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + hdmi_connector_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible =3D "linaro,optee-tz"; @@ -104,6 +119,16 @@ sound: sound { pinctrl-5 =3D <&aud_mosi_on_pins>; mediatek,platform =3D <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "vsys_lcm"; + }; + }; =20 &afe { @@ -131,6 +156,88 @@ &cpu3 { sram-supply =3D <&mt6357_vsram_proc_reg>; }; =20 +&dither0_out { + remote-endpoint =3D <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 =3D <&dpi_default_pins>; + pinctrl-1 =3D <&dpi_idle_pins>; + pinctrl-names =3D "default", "sleep"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dpi0_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dpi0_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "startek,kd070fhfid015"; + reg =3D <0>; + enable-gpios =3D <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply =3D <&mt6357_vsim1_reg>; + power-supply =3D <&vsys_lcm_reg>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dsi0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dsi0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 =3D <ðernet_pins>; pinctrl-names =3D "default"; @@ -161,6 +268,56 @@ &i2c0 { status =3D "okay"; }; =20 +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-div =3D <2>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + it66121_hdmi: hdmi@4c { + compatible =3D "ite,it66121"; + reg =3D <0x4c>; + #sound-dai-cells =3D <0>; + interrupt-parent =3D <&pio>; + interrupts =3D <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&ite_pins>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply =3D <&mt6357_vsim2_reg>; + vcn33-supply =3D <&mt6357_vibr_reg>; + vrf12-supply =3D <&mt6357_vrf12_reg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + it66121_in: endpoint@0 { + reg =3D <0>; + bus-width =3D <12>; + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hdmi_connector_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -205,6 +362,11 @@ &mt6357_pmic { mediatek,micbias1-microvolt =3D <1700000>; }; =20 +&mt6357_vsim1_reg { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -267,6 +429,49 @@ clk-dat-pins { }; }; =20 + dpi_default_pins: dpi-default-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength =3D <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux =3D ; @@ -308,6 +513,33 @@ pins { }; }; =20 + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux =3D , + ; + output-high; + }; + + rst_ite_pins { + pinmux =3D ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux =3D ; @@ -463,6 +695,10 @@ &pwm { status =3D "okay"; }; =20 +&rdma1_out { + remote-endpoint =3D <&dpi0_in>; +}; + &ssusb { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; --=20 2.25.1