From nobody Fri Dec 19 20:34:18 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F362204089 for ; Wed, 8 Jan 2025 16:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736352959; cv=none; b=TZobRNj0fLTFiIrNVZATOtcslUtPPBeWJVYvMhYk6KlBI4t5L4JyCnHFAzOQ/5FFGt8axCeF/6PJoXN7w9UZCN4mmlqwbxNePzdP2vuU/YNk2M0GhRa5DxS6qPEVIGx3vSI+fLiXpsQXJfED1nyT4iQuxt2ZBZhsawj31+eNULo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736352959; c=relaxed/simple; bh=oiBrgFDEH8oR9i80NmibPY4/A6M1F7T8QsUsAz/D+YY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VL8HnFroZAjKO09m6n5JMcPWN0fmy2SikMerz3owemVeum7506ZgezmmOzHs35CbugyB5NAAmQZ/WG9FymmJb5W1sWOcPm1WHh2r5ESXTSGT5vNJ/9RA3kOze/oZwuCL9I+/E4GEhtvXy6SmMGQnSiepFJM1dnzTwzrPPSycQm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Hm8j9Tzz; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Hm8j9Tzz" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43625c4a50dso158495e9.0 for ; Wed, 08 Jan 2025 08:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1736352956; x=1736957756; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZCHTeF6R0fGhSKfSt6MjkqVYus+rrnV1ENn9wfkH0OE=; b=Hm8j9TzzotXNoIzX5KpPhLrs6bkY4o98WhICbluClwep3jQt4yJ41EGarO/+IG/AEj R/w4gzgsY69gxv0H2Codli+POXeNt7Xglx4aggiCntqlry39CtxLg5bDI26OeVnUjlhI vR4DyW7pXKbGxmJs+dttqWjH/CXltxjrUZm+fe/yIRk9WFFyGyA64tV2CgqAZlu5k1TD lX5uDtR5OzntqsuH7cJvKcmBJfDBGtS3dxOJi2mKvur9Y931GKd+FN3ART8xUTirOgyE NzQVsNQDoHVpE4CWwt9laR0ZKOgC+EfYcUTqKXKd5aILwgxIRsR+qQayTLXjQ0acJljN 6K8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736352956; x=1736957756; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZCHTeF6R0fGhSKfSt6MjkqVYus+rrnV1ENn9wfkH0OE=; b=XXi4PLIRE5bpFKdE3OZ772ow6U5M+mxDANS6EMtsuB4kypsm+s648g1f/SvqLLX+G4 MPur0+cuVxSQzn+NWV+6DgiEgHF8Tb7RBBgRIfD8h8ludNRRtX126ACKHkpw7quSFDjx nblxpP7o6xlGkofLhPgIHr5FaF2oprchutg8+Oj3XMBrAktC/eN4s9/PTmL/67oMSwY+ CKalpLdnVxNtsDQHc3TYrbMVR2z9gWfJpLFEQ3DxeZMt0TyPCmjrJPV0EjDRJ3pKG74C iCqSgst26vTQ+KFuRV496NO2PreBWC3vQ8uiiZcCXT9LACpciFBAJFMWHDYZzqh82z6E 95aw== X-Forwarded-Encrypted: i=1; AJvYcCUpcJRt3EzjWFg789n+e5lbY3eqHGNqV0qUTfeoLMA3Jn09cRk9LdkNDuvyRqAfHVMBzlCPRjpTsBUGLTg=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6Z/9DcMPeLKETx+H7rJxBO04gQ5wGdgK5bIDraWtEYX+4xKHl squZzu3wpV+TYqoJ+GD/21MH51v/myxWTJrkdtTHu8mc9xDvUUhdqGMBinm1r1k= X-Gm-Gg: ASbGnct3f6+DzyjXtP0yNwvS9qf80X19p+BjG7HlqmNnL8c7SQiPfFDGkmvOB0L4Boe nF7mdlWteJd5nXU+cY/lXuWyiKrWwr6K7stAY7e0akp4kKszlmg7reWlFa8/jOdedVZ+3CjvkYx P7ERwCx6RHoX1jRWX2qew2fJchbAMl95+SyEYxVYf3U5oNNnQhC0IRmV1zr+w6KfqKjjZ1XI/Gq oWDdfGKlGZ/r/Yt31vOdlrds/51nXtfBRly6pVCMvObGwTavwJZ4laAQkE5 X-Google-Smtp-Source: AGHT+IHEILDWRs/8ApjgnIf3rSHJHPFt1S4VS+egmv2pZWmzR8KQn/GFSJiwtiZAUp1S8eGd/C13oA== X-Received: by 2002:a05:600c:3c85:b0:434:a802:e99a with SMTP id 5b1f17b1804b1-436e267821emr29030295e9.4.1736352955584; Wed, 08 Jan 2025 08:15:55 -0800 (PST) Received: from [127.0.1.1] ([2a01:e0a:5ee:79d0:a6ac:e6d2:88e3:8ea1]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436dd14dfcasm44378105e9.1.2025.01.08.08.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 08:15:55 -0800 (PST) From: Alexandre Mergnat Date: Wed, 08 Jan 2025 17:15:49 +0100 Subject: [PATCH v5 7/7] arm64: dts: mediatek: add display support for mt8365-evk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v5-7-3905f1e4b835@baylibre.com> References: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> In-Reply-To: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7455; i=amergnat@baylibre.com; h=from:subject:message-id; bh=oiBrgFDEH8oR9i80NmibPY4/A6M1F7T8QsUsAz/D+YY=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBnfqSyi4f+hfO2Xem78DOLGc6XqILcDRe5cULnYQi1 OgtZHHyJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZ36ksgAKCRArRkmdfjHURTdREA CY4yXPx/AEV2nA/rnJ7EXj25fNHH7L/Agasp+OirSRe0XBZ+UJbRKSKfDGhqRYnOZeE3kVhrT1HxhY upyqqZRuRBX2Al677eHWM8gphdCS36bGEJvfGZVF74ZhRB3BJvJ+FYrT08CWQnZ2FW6zonb3lRhfup 9LX7qmG5B5p7eFtA/i9JDJOhld0c13OzbWboBOdYQMB9VoMs7uzixqb4pvLMy+lTpLiiwWLgLLNmmA z7LTKZ8kSFeFjYIr8zNhKagj8xenWPSKU83ffIfOeWMPW0+h5jLUPwwMmJ+m5s0++D5f6FZlU3aGUZ XlnSXp2NzaW2576+QSbC1SA+woGOm6pF79Ko+9RttTzNAmq+lCM4oqCLveluu91YTldbC8awX75Dps 3Z8ZZ2utsumKVPOB00p+pRVLa9NAZvezd1TFtwAdu5CAplw5NfBFDsxhqeprRDB7KqzjQKotmDCWPy b1OE/SoJFlA2vYcCQclJslYbVt/uKfFH4QmeslLXBm7bsn75MObUDs9itOmJSUkdYpW/s3pGIk3grx X+m48DFDSDx8A+FqrEFc7yVv/NK1pbBxDIUVkUG+2LYrAIPB98I9lPDJkxHUIc7SOkbX56sB+DM77Y lu6MbzowJnXAmFOhEs2QxREIslKwiADDCfJNrgMOGGF6qFjffBNDExOpMMIg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 236 ++++++++++++++++++++++++= ++++ 1 file changed, 236 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts index 7d90112a7e27..61a58a1faee1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -27,6 +27,21 @@ chosen { stdout-path =3D "serial0:921600n8"; }; =20 + connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "d"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + hdmi_connector_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible =3D "linaro,optee-tz"; @@ -104,6 +119,16 @@ sound: sound { pinctrl-5 =3D <&aud_mosi_on_pins>; mediatek,platform =3D <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "vsys_lcm"; + }; + }; =20 &afe { @@ -131,6 +156,88 @@ &cpu3 { sram-supply =3D <&mt6357_vsram_proc_reg>; }; =20 +&dither0_out { + remote-endpoint =3D <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 =3D <&dpi_default_pins>; + pinctrl-1 =3D <&dpi_idle_pins>; + pinctrl-names =3D "default", "sleep"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dpi0_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dpi0_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "startek,kd070fhfid015"; + reg =3D <0>; + enable-gpios =3D <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply =3D <&mt6357_vsim1_reg>; + power-supply =3D <&vsys_lcm_reg>; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dsi0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dsi0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 =3D <ðernet_pins>; pinctrl-names =3D "default"; @@ -161,6 +268,56 @@ &i2c0 { status =3D "okay"; }; =20 +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-div =3D <2>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + it66121_hdmi: hdmi@4c { + #sound-dai-cells =3D <0>; + compatible =3D "ite,it66121"; + interrupt-parent =3D <&pio>; + interrupts =3D <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&ite_pins>; + pinctrl-names =3D "default"; + reg =3D <0x4c>; + reset-gpios =3D <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply =3D <&mt6357_vsim2_reg>; + vcn33-supply =3D <&mt6357_vibr_reg>; + vrf12-supply =3D <&mt6357_vrf12_reg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + it66121_in: endpoint@0 { + reg =3D <0>; + bus-width =3D <12>; + remote-endpoint =3D <&dpi0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hdmi_connector_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -205,6 +362,11 @@ &mt6357_pmic { mediatek,micbias1-microvolt =3D <1700000>; }; =20 +&mt6357_vsim1_reg { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -267,6 +429,49 @@ clk-dat-pins { }; }; =20 + dpi_default_pins: dpi-default-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength =3D <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux =3D ; @@ -308,6 +513,33 @@ pins { }; }; =20 + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux =3D , + ; + output-high; + }; + + rst_ite_pins { + pinmux =3D ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux =3D ; @@ -463,6 +695,10 @@ &pwm { status =3D "okay"; }; =20 +&rdma1_out { + remote-endpoint =3D <&dpi0_in>; +}; + &ssusb { dr_mode =3D "otg"; maximum-speed =3D "high-speed"; --=20 2.25.1