From nobody Mon Feb 9 05:22:23 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07E20200BA8 for ; Wed, 8 Jan 2025 16:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736352958; cv=none; b=TDMhluv4fSBt6MMwCiKHQk3RZSKMl/BJcUWKSaIoewMQXFwxOGR5xuka64QdMqWKFlS4729QlG/3b5zEKe5l7LsxdIwnhuUDkoG4cUpYxzivcm8jiMjFAc7TnpE3qIWrlyZMO7l3HAdrvew1dJDcbRBa+HTeWe646ygP/YAMjbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736352958; c=relaxed/simple; bh=yWk8HLzOpkZhXK2l7uxJYBkmU29C+tC9uY/Wa+pPUI8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IdWLlY5OjazfvlLy0toB4jg0QIBv0HCCnh/JtYRQb01SYLPzNiLv22dHFpzO87vf/xZ13nKOl4l8ooR5Q9FRTfwxfaaIb7bWxYK9H8ZQ2sOCf3qbcHEEh13aau1l6mxFD1AEyD3yRkCp+U0z6nBRXD6ktNO27yRY+mCKAUKsUAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=CQV//IfF; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="CQV//IfF" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4363dc916ceso6934125e9.0 for ; Wed, 08 Jan 2025 08:15:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1736352954; x=1736957754; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wn0z/hnPHRXKbB0BiiICrVZl9kYhQ/tTXH5ga1zPWyc=; b=CQV//IfFJDC0KHp2XQRJ4Eh1XNAzqehLZ7/6futtrLF6VXzfPalVlPybNMEDZk/QE5 soUfi4LGnio2G70VOPN2D85QrD7oNKXwEecqkMbICY6oMurFzU4urdf3WkkQ+Gjytm+g JsLLYAzS7AWZl9l/zsoWm0DDjACuWLsoR1DBWiyvyAQKzYXvTDAyKfiNdbJY1nBDWuzD CwR+TRWRntOrNJnYJm7pUo5mzRgkYuPY9XqEN4OWrJzqUaUA1rizv8SEEfgch9g1BbRf dQ3ehs4Yg818chcBS+KttG8BCxF0+LEa8T46wlxJpsvHa74ApN+KOnPeI5UVuqGHTXJJ itQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736352954; x=1736957754; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wn0z/hnPHRXKbB0BiiICrVZl9kYhQ/tTXH5ga1zPWyc=; b=I9eYvO/HT8BsgPxqD1ZRONYUehL7HI0K34Vt0U3Z7CJuRhW38Qd0tcVClFPPVXMU7r pTwCfl1Yxg2yiGdh50xFJVihY8o+ZkSf+0PdOFNLG5l/069BbAa6jO6lFJ40eazbDo9B ZgcMimEqIq5fMtutSKNtI4lJNwQ3U9Uazox+5c0N5wccvJYrad0L4t7CC71s1PAI08p9 TBYwFW/ttpNFtCgFzTxgaIBAapPwFzhAgWhZMB5E8cTN5kPrswiij3XBdxORNButfB51 glVAfLXE43SnmeAKgTJKFDbcMYHzSLIjfbzbeY5VlDT+TjKXSN4oTVitEwPKmixdnQjv h1Sw== X-Forwarded-Encrypted: i=1; AJvYcCWiiBf3S0uensqoJdfM8n7TjW26KxJPEKbxqfSmofs4ERfk+gJPjnGF/ee6r0D8JqqWIlupwgY0HvAF3ik=@vger.kernel.org X-Gm-Message-State: AOJu0YzKK/IH68DnDIIvYIvD2d3YWCx6F4lKwY4g/K9TXjaIw7YNcAOS L++5um14VJBUiGStSflQFPQSNARbxniHkAVbKc3g5Za4E/RC5dmtgEunJ99wBFY= X-Gm-Gg: ASbGncsqrAOIhFrrszvzE9SFWA9SwQux1jvTMrj6j9ByEj3eau2oaasAkz/u5r32l7S kc3NzQREc8/2xLgMN+ePDYIT9fPjA2Njn7NfpEoNfUFT1k3TL3FPcYoW0B3BoAGRAxrKv7ETrkH iP1luERIuZ+mo49+iiGTxFXS+D1cPfaCPrlMp3eged1mXVCEQsB7XEr3SYyvBEdFIscR6ODb9Rx 677mtFeO3ZI05wRVY/IxetjuQwdVAegyxTP2T10h2SIjHRn2RMTGLZiOMRc X-Google-Smtp-Source: AGHT+IHcsbLGPbCsRVGvojohrTvEnyypNhqIuN7WVwirYVpfixaNp8c/Hkxpo9jV/elwYELpq5m9lA== X-Received: by 2002:a05:600c:1d11:b0:434:e892:1033 with SMTP id 5b1f17b1804b1-436dc1b95ebmr61286195e9.2.1736352954396; Wed, 08 Jan 2025 08:15:54 -0800 (PST) Received: from [127.0.1.1] ([2a01:e0a:5ee:79d0:a6ac:e6d2:88e3:8ea1]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436dd14dfcasm44378105e9.1.2025.01.08.08.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 08:15:53 -0800 (PST) From: Alexandre Mergnat Date: Wed, 08 Jan 2025 17:15:48 +0100 Subject: [PATCH v5 6/7] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231023-display-support-v5-6-3905f1e4b835@baylibre.com> References: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> In-Reply-To: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10846; i=amergnat@baylibre.com; h=from:subject:message-id; bh=yWk8HLzOpkZhXK2l7uxJYBkmU29C+tC9uY/Wa+pPUI8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBnfqSyzrt8ChVQ58c0u08e+XuEpdHbrq5PUizBV5YT N4r2AKqJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZ36ksgAKCRArRkmdfjHURZ2WD/ 0bs+zZU7Pak9RQ/RDLmf62ST/AUr1yNNRAzqybobUSZCl6seRBKUZRgV2RoHVEWdG5axUXT5aIMoIY DC7bvTKdypRLwTUpCXCAjPNg9dhDDe6CTicpsGia68igb5HT4dB1xTKVzU1GVDjKDLtRAvEnK5IT2l 3dSc+FnBui0xq2cRgFeAu9ITqy0T02j9Vnyojqx02F+JFDdrUrY8BAF8c9SuQjxboOPLPVPkbwzzKY dXAX0H+RNcz+r8wkLqJbqgBf1G47VzczvaQc6SQbaMewA9ovsQiUMycAPco4EiXdLs8F2v4V9ZaItk +2+SLacwGgKEV9+Tj3WbvEvCDLe3pWX+RsxotkZFcj1gBJq8O8TiMrYpXrOSYWWvRTmMWcB8SIf8pf EzH2/TDJpPyGI/JerWayYZmeMEFAW1rMsa5M3uiK2OMACpN1oEAVEJ1oYsbTxSNK2PecOrbE9V3K0x 3EFLfWF49POdn73Wmm1ueYhFrWAAN9mw60O4flQvEhiSQUfXILStzQFwGz09SkbukBnr0cny63KYak A+r3fYSqpZYTuPNHR1HxbKdgqcTIheb43e/jsbyYty6B7ip/RaZ2T0LBH2/idyzpo+hGzpvdfDWxjx P/NF1HYEEopTHiWQomgXxFgNGCM6sWHXbW3nunLX/9IcnCu2x9ynJD9NQtiQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++= ++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 9c91fe8ea0f9..fdd570ca2d20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -19,6 +20,19 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + aal0 =3D &aal0; + ccorr0 =3D &ccorr0; + color0 =3D &color0; + dither0 =3D &dither0; + dpi0 =3D &dpi0; + dsi0 =3D &dsi0; + gamma0 =3D &gamma0; + ovl0 =3D &ovl0; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -608,6 +622,15 @@ spi: spi@1100a000 { status =3D "disabled"; }; =20 + disp_pwm: pwm@1100e000 { + compatible =3D "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg =3D <0 0x1100e000 0 0x1000>; + clock-names =3D "main", "mm"; + clocks =3D <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PW= M>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells =3D <2>; + }; + i2c3: i2c@1100f000 { compatible =3D "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg =3D <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -704,6 +727,15 @@ ethernet: ethernet@112a0000 { status =3D "disabled"; }; =20 + mipi_tx0: dsi-phy@11c00000 { + compatible =3D "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c00000 0 0x800>; + clock-output-names =3D "mipi_tx0_pll"; + clocks =3D <&clk26m>; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + }; + u3phy: t-phy@11cc0000 { compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells =3D <1>; @@ -731,6 +763,26 @@ mmsys: syscon@14000000 { compatible =3D "mediatek,mt8365-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mmsys_main: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8365-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; }; =20 smi_common: smi@14002000 { @@ -756,6 +808,290 @@ larb0: larb@14003000 { mediatek,larb-id =3D <0>; }; =20 + ovl0: ovl@1400b000 { + compatible =3D "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_OVL0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ovl0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&mmsys_main>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ovl0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size =3D <5120>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ovl0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible =3D "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&rdma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible =3D "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccor= r"; + reg =3D <0 0x14010000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + ccorr0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&color0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + ccorr0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible =3D "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x14011000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + aal0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + aal0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible =3D "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamm= a"; + reg =3D <0 0x14012000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + gamma0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&aal0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + gamma0_out: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible =3D "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x14013000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + dither0_in: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&gamma0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + dither0_out: endpoint@0 { + reg =3D <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg =3D <0 0x14014000 0 0x1000>; + clock-names =3D "engine", "digital", "hs"; + clocks =3D <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts =3D ; + phy-names =3D "dphy"; + phys =3D <&mipi_tx0>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible =3D "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14016000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size =3D <2048>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + rdma1_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + rdma1_out: endpoint@1 { + reg =3D <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible =3D "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg =3D <0 0x14018000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8365_POWER_DOMAIN_MM>; + status =3D "disabled"; + }; + camsys: syscon@15000000 { compatible =3D "mediatek,mt8365-imgsys", "syscon"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.25.1